1 // SPDX-License-Identifier: GPL-2.0+
3 * National Semiconductor PHY drivers
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
13 #define DP83630_PHY_PAGESEL_REG 0x13
14 #define DP83630_PHY_PTP_COC_REG 0x14
15 #define DP83630_PHY_PTP_CLKOUT_EN (1<<15)
16 #define DP83630_PHY_RBR_REG 0x17
18 static int dp83630_config(struct phy_device *phydev)
22 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
23 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6);
24 ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE,
25 DP83630_PHY_PTP_COC_REG);
26 ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN;
27 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG,
29 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0);
31 genphy_config_aneg(phydev);
36 static struct phy_driver DP83630_driver = {
37 .name = "NatSemi DP83630",
40 .features = PHY_BASIC_FEATURES,
41 .config = &dp83630_config,
42 .startup = &genphy_startup,
43 .shutdown = &genphy_shutdown,
47 /* DP83865 Link and Auto-Neg Status Register */
48 #define MIIM_DP83865_LANR 0x11
49 #define MIIM_DP83865_SPD_MASK 0x0018
50 #define MIIM_DP83865_SPD_1000 0x0010
51 #define MIIM_DP83865_SPD_100 0x0008
52 #define MIIM_DP83865_DPX_FULL 0x0002
56 static int dp838xx_config(struct phy_device *phydev)
58 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
59 genphy_config_aneg(phydev);
64 static int dp83865_parse_status(struct phy_device *phydev)
68 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR);
70 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
72 case MIIM_DP83865_SPD_1000:
73 phydev->speed = SPEED_1000;
76 case MIIM_DP83865_SPD_100:
77 phydev->speed = SPEED_100;
81 phydev->speed = SPEED_10;
86 if (mii_reg & MIIM_DP83865_DPX_FULL)
87 phydev->duplex = DUPLEX_FULL;
89 phydev->duplex = DUPLEX_HALF;
94 static int dp83865_startup(struct phy_device *phydev)
98 ret = genphy_update_link(phydev);
102 return dp83865_parse_status(phydev);
106 static struct phy_driver DP83865_driver = {
107 .name = "NatSemi DP83865",
110 .features = PHY_GBIT_FEATURES,
111 .config = &dp838xx_config,
112 .startup = &dp83865_startup,
113 .shutdown = &genphy_shutdown,
116 /* NatSemi DP83848 */
117 static int dp83848_parse_status(struct phy_device *phydev)
121 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
123 if(mii_reg & (BMSR_100FULL | BMSR_100HALF)) {
124 phydev->speed = SPEED_100;
126 phydev->speed = SPEED_10;
129 if (mii_reg & (BMSR_10FULL | BMSR_100FULL)) {
130 phydev->duplex = DUPLEX_FULL;
132 phydev->duplex = DUPLEX_HALF;
138 static int dp83848_startup(struct phy_device *phydev)
142 ret = genphy_update_link(phydev);
146 return dp83848_parse_status(phydev);
149 static struct phy_driver DP83848_driver = {
150 .name = "NatSemi DP83848",
153 .features = PHY_BASIC_FEATURES,
154 .config = &dp838xx_config,
155 .startup = &dp83848_startup,
156 .shutdown = &genphy_shutdown,
159 int phy_natsemi_init(void)
161 phy_register(&DP83630_driver);
162 phy_register(&DP83865_driver);
163 phy_register(&DP83848_driver);