1 // SPDX-License-Identifier: GPL-2.0+
4 * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
9 #include <linux/errno.h>
10 #include <mv88e6352.h>
12 #define SMI_HDR ((0x8 | 0x1) << 12)
13 #define SMI_BUSY_MASK (0x8000)
14 #define SMIRD_OP (0x2 << 10)
15 #define SMIWR_OP (0x1 << 10)
22 /* global registers */
25 #define GLOBAL_STATUS 0x00
26 #define PPU_STATE 0x8000
28 #define GLOBAL_CTRL 0x04
29 #define SW_RESET 0x8000
30 #define PPU_ENABLE 0x4000
32 static int sw_wait_rdy(const char *devname, u8 phy_addr)
38 /* wait till the SMI is not busy */
40 /* read command register */
41 ret = miiphy_read(devname, phy_addr, COMMAND_REG, &command);
43 printf("%s: Error reading command register\n",
48 printf("Err..(%s) SMI busy timeout\n", __func__);
51 } while (command & SMI_BUSY_MASK);
56 static int sw_reg_read(const char *devname, u8 phy_addr, u8 port,
62 ret = sw_wait_rdy(devname, phy_addr);
66 command = SMI_HDR | SMIRD_OP | ((port&SMI_MASK) << PORT_SHIFT) |
68 debug("%s: write to command: %#x\n", __func__, command);
69 ret = miiphy_write(devname, phy_addr, COMMAND_REG, command);
73 ret = sw_wait_rdy(devname, phy_addr);
77 ret = miiphy_read(devname, phy_addr, DATA_REG, data);
82 static int sw_reg_write(const char *devname, u8 phy_addr, u8 port,
88 ret = sw_wait_rdy(devname, phy_addr);
92 debug("%s: write to data: %#x\n", __func__, data);
93 ret = miiphy_write(devname, phy_addr, DATA_REG, data);
97 value = SMI_HDR | SMIWR_OP | ((port & SMI_MASK) << PORT_SHIFT) |
99 debug("%s: write to command: %#x\n", __func__, value);
100 ret = miiphy_write(devname, phy_addr, COMMAND_REG, value);
104 ret = sw_wait_rdy(devname, phy_addr);
111 static int ppu_enable(const char *devname, u8 phy_addr)
116 ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®);
118 printf("%s: Error reading global ctrl reg\n", __func__);
124 ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
126 printf("%s: Error writing global ctrl reg\n", __func__);
130 for (i = 0; i < 1000; i++) {
131 sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
133 if ((reg & 0xc000) == 0xc000)
141 static int ppu_disable(const char *devname, u8 phy_addr)
146 ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®);
148 printf("%s: Error reading global ctrl reg\n", __func__);
154 ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
156 printf("%s: Error writing global ctrl reg\n", __func__);
160 for (i = 0; i < 1000; i++) {
161 sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
163 if ((reg & 0xc000) != 0xc000)
171 int mv88e_sw_program(const char *devname, u8 phy_addr,
172 struct mv88e_sw_reg *regs, int regs_nb)
176 /* first we need to disable the PPU */
177 ret = ppu_disable(devname, phy_addr);
179 printf("%s: Error disabling PPU\n", __func__);
183 for (i = 0; i < regs_nb; i++) {
184 ret = sw_reg_write(devname, phy_addr, regs[i].port,
185 regs[i].reg, regs[i].value);
187 printf("%s: Error configuring switch\n", __func__);
188 ppu_enable(devname, phy_addr);
193 /* re-enable the PPU */
194 ret = ppu_enable(devname, phy_addr);
196 printf("%s: Error enabling PPU\n", __func__);
203 int mv88e_sw_reset(const char *devname, u8 phy_addr)
208 ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®);
210 printf("%s: Error reading global ctrl reg\n", __func__);
214 reg = SW_RESET | PPU_ENABLE | 0x0400;
216 ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
218 printf("%s: Error writing global ctrl reg\n", __func__);
222 for (i = 0; i < 1000; i++) {
223 sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
225 if ((reg & 0xc800) != 0xc800)
233 int do_mvsw_reg_read(const char *name, int argc, char * const argv[])
235 u16 value = 0, phyaddr, reg, port;
238 phyaddr = simple_strtoul(argv[1], NULL, 10);
239 port = simple_strtoul(argv[2], NULL, 10);
240 reg = simple_strtoul(argv[3], NULL, 10);
242 ret = sw_reg_read(name, phyaddr, port, reg, &value);
243 printf("%#x\n", value);
248 int do_mvsw_reg_write(const char *name, int argc, char * const argv[])
250 u16 value = 0, phyaddr, reg, port;
253 phyaddr = simple_strtoul(argv[1], NULL, 10);
254 port = simple_strtoul(argv[2], NULL, 10);
255 reg = simple_strtoul(argv[3], NULL, 10);
256 value = simple_strtoul(argv[4], NULL, 16);
258 ret = sw_reg_write(name, phyaddr, port, reg, value);
264 int do_mvsw_reg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
267 const char *cmd, *ethname;
270 return cmd_usage(cmdtp);
276 if (strcmp(cmd, "read") == 0) {
278 return cmd_usage(cmdtp);
282 ret = do_mvsw_reg_read(ethname, argc, argv);
283 } else if (strcmp(cmd, "write") == 0) {
285 return cmd_usage(cmdtp);
289 ret = do_mvsw_reg_write(ethname, argc, argv);
291 return cmd_usage(cmdtp);
297 mvsw_reg, 7, 1, do_mvsw_reg,
298 "marvell 88e6352 switch register access",
299 "write ethname phyaddr port reg value\n"
300 "mvsw_reg read ethname phyaddr port reg\n"