3 * Elecsys Corporation <www.elecsyscorp.com>
4 * Kevin Smith <kevin.smith@elecsyscorp.com>
8 * Marvell Semiconductor <www.marvell.com>
9 * Prafulla Wadaskar <prafulla@marvell.com>
11 * SPDX-License-Identifier: GPL-2.0+
15 * PHY driver for mv88e61xx ethernet switches.
17 * This driver configures the mv88e61xx for basic use as a PHY. The switch
18 * supports a VLAN configuration that determines how traffic will be routed
19 * between the ports. This driver uses a simple configuration that routes
20 * traffic from each PHY port only to the CPU port, and from the CPU port to
23 * The configuration determines which PHY ports to activate using the
24 * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit
25 * 1 activates port 1, etc. Do not set the bit for the port the CPU is
26 * connected to unless it is connected over a PHY interface (not MII).
28 * This driver was written for and tested on the mv88e6176 with an SGMII
29 * connection. Other configurations should be supported, but some additions or
30 * changes may be required.
41 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
44 #define PORT_MASK ((1 << PORT_COUNT) - 1)
46 /* Device addresses */
47 #define DEVADDR_PHY(p) (p)
48 #define DEVADDR_PORT(p) (0x10 + (p))
49 #define DEVADDR_SERDES 0x0F
50 #define DEVADDR_GLOBAL_1 0x1B
51 #define DEVADDR_GLOBAL_2 0x1C
53 /* SMI indirection registers for multichip addressing mode */
54 #define SMI_CMD_REG 0x00
55 #define SMI_DATA_REG 0x01
57 /* Global registers */
58 #define GLOBAL1_STATUS 0x00
59 #define GLOBAL1_CTRL 0x04
60 #define GLOBAL1_MON_CTRL 0x1A
62 /* Global 2 registers */
63 #define GLOBAL2_REG_PHY_CMD 0x18
64 #define GLOBAL2_REG_PHY_DATA 0x19
67 #define PORT_REG_STATUS 0x00
68 #define PORT_REG_PHYS_CTRL 0x01
69 #define PORT_REG_SWITCH_ID 0x03
70 #define PORT_REG_CTRL 0x04
71 #define PORT_REG_VLAN_MAP 0x06
72 #define PORT_REG_VLAN_ID 0x07
75 #define PHY_REG_CTRL1 0x10
76 #define PHY_REG_STATUS1 0x11
77 #define PHY_REG_PAGE 0x16
79 /* Serdes registers */
80 #define SERDES_REG_CTRL_1 0x10
82 /* Phy page numbers */
83 #define PHY_PAGE_COPPER 0
84 #define PHY_PAGE_SERDES 1
87 #define GLOBAL1_CTRL_SWRESET BIT(15)
89 #define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
90 #define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
92 #define PORT_REG_STATUS_LINK BIT(11)
93 #define PORT_REG_STATUS_DUPLEX BIT(10)
95 #define PORT_REG_STATUS_SPEED_SHIFT 8
96 #define PORT_REG_STATUS_SPEED_WIDTH 2
97 #define PORT_REG_STATUS_SPEED_10 0
98 #define PORT_REG_STATUS_SPEED_100 1
99 #define PORT_REG_STATUS_SPEED_1000 2
101 #define PORT_REG_STATUS_CMODE_MASK 0xF
102 #define PORT_REG_STATUS_CMODE_100BASE_X 0x8
103 #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
104 #define PORT_REG_STATUS_CMODE_SGMII 0xa
106 #define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
107 #define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
109 #define PORT_REG_CTRL_PSTATE_SHIFT 0
110 #define PORT_REG_CTRL_PSTATE_WIDTH 2
112 #define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
113 #define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
115 #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0
116 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
118 #define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
120 #define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8
121 #define PHY_REG_CTRL1_ENERGY_DET_WIDTH 2
124 #define PORT_REG_CTRL_PSTATE_DISABLED 0
125 #define PORT_REG_CTRL_PSTATE_FORWARD 3
127 #define PHY_REG_CTRL1_ENERGY_DET_OFF 0
128 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2
129 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3
131 /* PHY Status Register */
132 #define PHY_REG_STATUS1_SPEED 0xc000
133 #define PHY_REG_STATUS1_GBIT 0x8000
134 #define PHY_REG_STATUS1_100 0x4000
135 #define PHY_REG_STATUS1_DUPLEX 0x2000
136 #define PHY_REG_STATUS1_SPDDONE 0x0800
137 #define PHY_REG_STATUS1_LINK 0x0400
138 #define PHY_REG_STATUS1_ENERGY 0x0010
141 * Macros for building commands for indirect addressing modes. These are valid
142 * for both the indirect multichip addressing mode and the PHY indirection
143 * required for the writes to any PHY register.
145 #define SMI_BUSY BIT(15)
146 #define SMI_CMD_CLAUSE_22 BIT(12)
147 #define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
148 #define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
150 #define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
151 SMI_CMD_CLAUSE_22_OP_READ)
152 #define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
153 SMI_CMD_CLAUSE_22_OP_WRITE)
155 #define SMI_CMD_ADDR_SHIFT 5
156 #define SMI_CMD_ADDR_WIDTH 5
157 #define SMI_CMD_REG_SHIFT 0
158 #define SMI_CMD_REG_WIDTH 5
160 /* Check for required macros */
161 #ifndef CONFIG_MV88E61XX_PHY_PORTS
162 #error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
165 #ifndef CONFIG_MV88E61XX_CPU_PORT
166 #error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
169 /* ID register values for different switch models */
170 #define PORT_SWITCH_ID_6096 0x0980
171 #define PORT_SWITCH_ID_6097 0x0990
172 #define PORT_SWITCH_ID_6172 0x1720
173 #define PORT_SWITCH_ID_6176 0x1760
174 #define PORT_SWITCH_ID_6240 0x2400
175 #define PORT_SWITCH_ID_6352 0x3520
177 struct mv88e61xx_phy_priv {
178 struct mii_dev *mdio_bus;
183 static inline int smi_cmd(int cmd, int addr, int reg)
185 cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
187 cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
191 static inline int smi_cmd_read(int addr, int reg)
193 return smi_cmd(SMI_CMD_READ, addr, reg);
196 static inline int smi_cmd_write(int addr, int reg)
198 return smi_cmd(SMI_CMD_WRITE, addr, reg);
201 __weak int mv88e61xx_hw_reset(struct phy_device *phydev)
206 /* Wait for the current SMI indirect command to complete */
207 static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
213 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
214 if (val >= 0 && (val & SMI_BUSY) == 0)
220 puts("SMI busy timeout\n");
225 * The mv88e61xx has three types of addresses: the smi bus address, the device
226 * address, and the register address. The smi bus address distinguishes it on
227 * the smi bus from other PHYs or switches. The device address determines
228 * which on-chip register set you are reading/writing (the various PHYs, their
229 * associated ports, or global configuration registers). The register address
230 * is the offset of the register you are reading/writing.
232 * When the mv88e61xx is hardware configured to have address zero, it behaves in
233 * single-chip addressing mode, where it responds to all SMI addresses, using
234 * the smi address as its device address. This obviously only works when this
235 * is the only chip on the SMI bus. This allows the driver to access device
236 * registers without using indirection. When the chip is configured to a
237 * non-zero address, it only responds to that SMI address and requires indirect
238 * writes to access the different device addresses.
240 static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
242 struct mv88e61xx_phy_priv *priv = phydev->priv;
243 struct mii_dev *mdio_bus = priv->mdio_bus;
244 int smi_addr = priv->smi_addr;
247 /* In single-chip mode, the device can be addressed directly */
249 return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
251 /* Wait for the bus to become free */
252 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
256 /* Issue the read command */
257 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
258 smi_cmd_read(dev, reg));
262 /* Wait for the read command to complete */
263 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
268 res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
272 return bitfield_extract(res, 0, 16);
275 /* See the comment above mv88e61xx_reg_read */
276 static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
279 struct mv88e61xx_phy_priv *priv = phydev->priv;
280 struct mii_dev *mdio_bus = priv->mdio_bus;
281 int smi_addr = priv->smi_addr;
284 /* In single-chip mode, the device can be addressed directly */
286 return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
290 /* Wait for the bus to become free */
291 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
295 /* Set the data to write */
296 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
301 /* Issue the write command */
302 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
303 smi_cmd_write(dev, reg));
307 /* Wait for the write command to complete */
308 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
315 static int mv88e61xx_phy_wait(struct phy_device *phydev)
321 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
322 GLOBAL2_REG_PHY_CMD);
323 if (val >= 0 && (val & SMI_BUSY) == 0)
332 static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
335 struct phy_device *phydev;
338 phydev = (struct phy_device *)smi_wrapper->priv;
340 /* Issue command to read */
341 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
343 smi_cmd_read(dev, reg));
345 /* Wait for data to be read */
346 res = mv88e61xx_phy_wait(phydev);
350 /* Read retrieved data */
351 return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
352 GLOBAL2_REG_PHY_DATA);
355 static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
356 int devad, int reg, u16 data)
358 struct phy_device *phydev;
361 phydev = (struct phy_device *)smi_wrapper->priv;
363 /* Set the data to write */
364 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
365 GLOBAL2_REG_PHY_DATA, data);
368 /* Issue the write command */
369 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
371 smi_cmd_write(dev, reg));
375 /* Wait for command to complete */
376 return mv88e61xx_phy_wait(phydev);
379 /* Wrapper function to make calls to phy_read_indirect simpler */
380 static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
382 return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
383 MDIO_DEVAD_NONE, reg);
386 /* Wrapper function to make calls to phy_read_indirect simpler */
387 static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
390 return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
391 MDIO_DEVAD_NONE, reg, val);
394 static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
396 return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg);
399 static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
402 return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val);
405 static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
407 return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
410 static int mv88e61xx_get_switch_id(struct phy_device *phydev)
414 res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
420 static bool mv88e61xx_6352_family(struct phy_device *phydev)
422 struct mv88e61xx_phy_priv *priv = phydev->priv;
425 case PORT_SWITCH_ID_6172:
426 case PORT_SWITCH_ID_6176:
427 case PORT_SWITCH_ID_6240:
428 case PORT_SWITCH_ID_6352:
434 static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
438 res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
441 return res & PORT_REG_STATUS_CMODE_MASK;
444 static int mv88e61xx_parse_status(struct phy_device *phydev)
447 unsigned int mii_reg;
449 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
451 if ((mii_reg & PHY_REG_STATUS1_LINK) &&
452 !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
455 puts("Waiting for PHY realtime link");
456 while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
457 /* Timeout reached ? */
458 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
459 puts(" TIMEOUT !\n");
464 if ((i++ % 1000) == 0)
467 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
471 udelay(500000); /* another 500 ms (results in faster booting) */
473 if (mii_reg & PHY_REG_STATUS1_LINK)
479 if (mii_reg & PHY_REG_STATUS1_DUPLEX)
480 phydev->duplex = DUPLEX_FULL;
482 phydev->duplex = DUPLEX_HALF;
484 speed = mii_reg & PHY_REG_STATUS1_SPEED;
487 case PHY_REG_STATUS1_GBIT:
488 phydev->speed = SPEED_1000;
490 case PHY_REG_STATUS1_100:
491 phydev->speed = SPEED_100;
494 phydev->speed = SPEED_10;
501 static int mv88e61xx_switch_reset(struct phy_device *phydev)
507 /* Disable all ports */
508 for (port = 0; port < PORT_COUNT; port++) {
509 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
512 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
513 PORT_REG_CTRL_PSTATE_WIDTH,
514 PORT_REG_CTRL_PSTATE_DISABLED);
515 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
520 /* Wait 2 ms for queues to drain */
524 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_CTRL);
527 val |= GLOBAL1_CTRL_SWRESET;
528 val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
533 /* Wait up to 1 second for switch reset complete */
534 for (time = 1000; time; time--) {
535 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1,
537 if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
547 static int mv88e61xx_serdes_init(struct phy_device *phydev)
551 val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
555 /* Power up serdes module */
556 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
559 val &= ~(BMCR_PDOWN);
560 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
567 static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
571 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
574 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
575 PORT_REG_CTRL_PSTATE_WIDTH,
576 PORT_REG_CTRL_PSTATE_FORWARD);
577 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
584 static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
589 /* Set VID to port number plus one */
590 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
593 val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
594 PORT_REG_VLAN_ID_DEF_VID_WIDTH,
596 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
601 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
604 val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
605 PORT_REG_VLAN_MAP_TABLE_WIDTH,
607 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
614 static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
620 val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
623 if (!(val & PORT_REG_STATUS_LINK)) {
624 /* Temporarily force link to read port configuration */
628 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
631 val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
632 PORT_REG_PHYS_CTRL_LINK_VALUE);
633 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
638 /* Wait for status register to reflect forced link */
640 val = mv88e61xx_port_read(phydev, port,
644 if (val & PORT_REG_STATUS_LINK)
654 if (val & PORT_REG_STATUS_DUPLEX)
655 phydev->duplex = DUPLEX_FULL;
657 phydev->duplex = DUPLEX_HALF;
659 val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
660 PORT_REG_STATUS_SPEED_WIDTH);
662 case PORT_REG_STATUS_SPEED_1000:
663 phydev->speed = SPEED_1000;
665 case PORT_REG_STATUS_SPEED_100:
666 phydev->speed = SPEED_100;
669 phydev->speed = SPEED_10;
677 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
680 val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
681 PORT_REG_PHYS_CTRL_LINK_VALUE);
682 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
691 static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
696 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_MON_CTRL);
699 val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
700 GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
701 CONFIG_MV88E61XX_CPU_PORT);
702 val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
703 GLOBAL1_MON_CTRL, val);
707 /* Allow CPU to route to any port */
708 val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
709 val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
713 /* Enable CPU port */
714 val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
718 val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
722 /* If CPU is connected to serdes, initialize serdes */
723 if (mv88e61xx_6352_family(phydev)) {
724 val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
727 if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
728 val == PORT_REG_STATUS_CMODE_1000BASE_X ||
729 val == PORT_REG_STATUS_CMODE_SGMII) {
730 val = mv88e61xx_serdes_init(phydev);
739 static int mv88e61xx_switch_init(struct phy_device *phydev)
747 res = mv88e61xx_switch_reset(phydev);
751 res = mv88e61xx_set_cpu_port(phydev);
760 static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
764 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
767 val &= ~(BMCR_PDOWN);
768 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
775 static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
780 * Enable energy-detect sensing on PHY, used to determine when a PHY
781 * port is physically connected
783 val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
786 val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT,
787 PHY_REG_CTRL1_ENERGY_DET_WIDTH,
788 PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT);
789 val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
796 static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
800 val = mv88e61xx_port_enable(phydev, phy);
804 val = mv88e61xx_port_set_vlan(phydev, phy,
805 1 << CONFIG_MV88E61XX_CPU_PORT);
812 static int mv88e61xx_probe(struct phy_device *phydev)
814 struct mii_dev *smi_wrapper;
815 struct mv88e61xx_phy_priv *priv;
818 res = mv88e61xx_hw_reset(phydev);
822 priv = malloc(sizeof(*priv));
826 memset(priv, 0, sizeof(*priv));
829 * This device requires indirect reads/writes to the PHY registers
830 * which the generic PHY code can't handle. Make a wrapper MII device
831 * to handle reads/writes
833 smi_wrapper = mdio_alloc();
840 * Store the mdio bus in the private data, as we are going to replace
841 * the bus with the wrapper bus
843 priv->mdio_bus = phydev->bus;
846 * Store the smi bus address in private data. This lets us use the
847 * phydev addr field for device address instead, as the genphy code
850 priv->smi_addr = phydev->addr;
853 * Store the phy_device in the wrapper mii device. This lets us get it
854 * back when genphy functions call phy_read/phy_write.
856 smi_wrapper->priv = phydev;
857 strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
858 smi_wrapper->read = mv88e61xx_phy_read_indirect;
859 smi_wrapper->write = mv88e61xx_phy_write_indirect;
861 /* Replace the bus with the wrapper device */
862 phydev->bus = smi_wrapper;
866 priv->id = mv88e61xx_get_switch_id(phydev);
871 static int mv88e61xx_phy_config(struct phy_device *phydev)
877 res = mv88e61xx_switch_init(phydev);
881 for (i = 0; i < PORT_COUNT; i++) {
882 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
885 res = mv88e61xx_phy_enable(phydev, i);
887 printf("Error enabling PHY %i\n", i);
890 res = mv88e61xx_phy_setup(phydev, i);
892 printf("Error setting up PHY %i\n", i);
895 res = mv88e61xx_phy_config_port(phydev, i);
897 printf("Error configuring PHY %i\n", i);
901 res = genphy_config_aneg(phydev);
903 printf("Error setting PHY %i autoneg\n", i);
906 res = phy_reset(phydev);
908 printf("Error resetting PHY %i\n", i);
912 /* Return success if any PHY succeeds */
920 static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
924 val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
929 * After reset, the energy detect signal remains high for a few seconds
930 * regardless of whether a cable is connected. This function will
931 * return false positives during this time.
933 return (val & PHY_REG_STATUS1_ENERGY) == 0;
936 static int mv88e61xx_phy_startup(struct phy_device *phydev)
941 int speed = phydev->speed;
942 int duplex = phydev->duplex;
944 for (i = 0; i < PORT_COUNT; i++) {
945 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
947 if (!mv88e61xx_phy_is_connected(phydev))
949 res = genphy_update_link(phydev);
952 res = mv88e61xx_parse_status(phydev);
955 link = (link || phydev->link);
960 /* Restore CPU interface speed and duplex after it was changed for
962 phydev->speed = speed;
963 phydev->duplex = duplex;
968 static struct phy_driver mv88e61xx_driver = {
969 .name = "Marvell MV88E61xx",
972 .features = PHY_GBIT_FEATURES,
973 .probe = mv88e61xx_probe,
974 .config = mv88e61xx_phy_config,
975 .startup = mv88e61xx_phy_startup,
976 .shutdown = &genphy_shutdown,
979 static struct phy_driver mv88e609x_driver = {
980 .name = "Marvell MV88E609x",
983 .features = PHY_GBIT_FEATURES,
984 .probe = mv88e61xx_probe,
985 .config = mv88e61xx_phy_config,
986 .startup = mv88e61xx_phy_startup,
987 .shutdown = &genphy_shutdown,
990 int phy_mv88e61xx_init(void)
992 phy_register(&mv88e61xx_driver);
993 phy_register(&mv88e609x_driver);
999 * Overload weak get_phy_id definition since we need non-standard functions
1000 * to read PHY registers
1002 int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
1004 struct phy_device temp_phy;
1005 struct mv88e61xx_phy_priv temp_priv;
1006 struct mii_dev temp_mii;
1010 * Buid temporary data structures that the chip reading code needs to
1013 temp_priv.mdio_bus = bus;
1014 temp_priv.smi_addr = smi_addr;
1015 temp_phy.priv = &temp_priv;
1016 temp_mii.priv = &temp_phy;
1018 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
1022 *phy_id = val << 16;
1024 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
1028 *phy_id |= (val & 0xffff);