1 // SPDX-License-Identifier: GPL-2.0+
4 * Elecsys Corporation <www.elecsyscorp.com>
5 * Kevin Smith <kevin.smith@elecsyscorp.com>
9 * Marvell Semiconductor <www.marvell.com>
10 * Prafulla Wadaskar <prafulla@marvell.com>
14 * PHY driver for mv88e61xx ethernet switches.
16 * This driver configures the mv88e61xx for basic use as a PHY. The switch
17 * supports a VLAN configuration that determines how traffic will be routed
18 * between the ports. This driver uses a simple configuration that routes
19 * traffic from each PHY port only to the CPU port, and from the CPU port to
22 * The configuration determines which PHY ports to activate using the
23 * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit
24 * 1 activates port 1, etc. Do not set the bit for the port the CPU is
25 * connected to unless it is connected over a PHY interface (not MII).
27 * This driver was written for and tested on the mv88e6176 with an SGMII
28 * connection. Other configurations should be supported, but some additions or
29 * changes may be required.
40 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
43 #define PORT_MASK ((1 << PORT_COUNT) - 1)
45 /* Device addresses */
46 #define DEVADDR_PHY(p) (p)
47 #define DEVADDR_PORT(p) (0x10 + (p))
48 #define DEVADDR_SERDES 0x0F
49 #define DEVADDR_GLOBAL_1 0x1B
50 #define DEVADDR_GLOBAL_2 0x1C
52 /* SMI indirection registers for multichip addressing mode */
53 #define SMI_CMD_REG 0x00
54 #define SMI_DATA_REG 0x01
56 /* Global registers */
57 #define GLOBAL1_STATUS 0x00
58 #define GLOBAL1_CTRL 0x04
59 #define GLOBAL1_MON_CTRL 0x1A
61 /* Global 2 registers */
62 #define GLOBAL2_REG_PHY_CMD 0x18
63 #define GLOBAL2_REG_PHY_DATA 0x19
66 #define PORT_REG_STATUS 0x00
67 #define PORT_REG_PHYS_CTRL 0x01
68 #define PORT_REG_SWITCH_ID 0x03
69 #define PORT_REG_CTRL 0x04
70 #define PORT_REG_VLAN_MAP 0x06
71 #define PORT_REG_VLAN_ID 0x07
74 #define PHY_REG_CTRL1 0x10
75 #define PHY_REG_STATUS1 0x11
76 #define PHY_REG_PAGE 0x16
78 /* Serdes registers */
79 #define SERDES_REG_CTRL_1 0x10
81 /* Phy page numbers */
82 #define PHY_PAGE_COPPER 0
83 #define PHY_PAGE_SERDES 1
86 #define GLOBAL1_CTRL_SWRESET BIT(15)
88 #define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
89 #define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
91 #define PORT_REG_STATUS_LINK BIT(11)
92 #define PORT_REG_STATUS_DUPLEX BIT(10)
94 #define PORT_REG_STATUS_SPEED_SHIFT 8
95 #define PORT_REG_STATUS_SPEED_WIDTH 2
96 #define PORT_REG_STATUS_SPEED_10 0
97 #define PORT_REG_STATUS_SPEED_100 1
98 #define PORT_REG_STATUS_SPEED_1000 2
100 #define PORT_REG_STATUS_CMODE_MASK 0xF
101 #define PORT_REG_STATUS_CMODE_100BASE_X 0x8
102 #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
103 #define PORT_REG_STATUS_CMODE_SGMII 0xa
105 #define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
106 #define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
107 #define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
108 #define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6)
109 #define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
110 #define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
111 #define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3)
112 #define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2)
113 #define PORT_REG_PHYS_CTRL_SPD1000 BIT(1)
114 #define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0))
116 #define PORT_REG_CTRL_PSTATE_SHIFT 0
117 #define PORT_REG_CTRL_PSTATE_WIDTH 2
119 #define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
120 #define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
122 #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0
123 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
125 #define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
127 #define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8
128 #define PHY_REG_CTRL1_ENERGY_DET_WIDTH 2
131 #define PORT_REG_CTRL_PSTATE_DISABLED 0
132 #define PORT_REG_CTRL_PSTATE_FORWARD 3
134 #define PHY_REG_CTRL1_ENERGY_DET_OFF 0
135 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2
136 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3
138 /* PHY Status Register */
139 #define PHY_REG_STATUS1_SPEED 0xc000
140 #define PHY_REG_STATUS1_GBIT 0x8000
141 #define PHY_REG_STATUS1_100 0x4000
142 #define PHY_REG_STATUS1_DUPLEX 0x2000
143 #define PHY_REG_STATUS1_SPDDONE 0x0800
144 #define PHY_REG_STATUS1_LINK 0x0400
145 #define PHY_REG_STATUS1_ENERGY 0x0010
148 * Macros for building commands for indirect addressing modes. These are valid
149 * for both the indirect multichip addressing mode and the PHY indirection
150 * required for the writes to any PHY register.
152 #define SMI_BUSY BIT(15)
153 #define SMI_CMD_CLAUSE_22 BIT(12)
154 #define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
155 #define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
157 #define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
158 SMI_CMD_CLAUSE_22_OP_READ)
159 #define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
160 SMI_CMD_CLAUSE_22_OP_WRITE)
162 #define SMI_CMD_ADDR_SHIFT 5
163 #define SMI_CMD_ADDR_WIDTH 5
164 #define SMI_CMD_REG_SHIFT 0
165 #define SMI_CMD_REG_WIDTH 5
167 /* Check for required macros */
168 #ifndef CONFIG_MV88E61XX_PHY_PORTS
169 #error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
172 #ifndef CONFIG_MV88E61XX_CPU_PORT
173 #error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
177 * These are ports without PHYs that may be wired directly
178 * to other serdes interfaces
180 #ifndef CONFIG_MV88E61XX_FIXED_PORTS
181 #define CONFIG_MV88E61XX_FIXED_PORTS 0
184 /* ID register values for different switch models */
185 #define PORT_SWITCH_ID_6096 0x0980
186 #define PORT_SWITCH_ID_6097 0x0990
187 #define PORT_SWITCH_ID_6172 0x1720
188 #define PORT_SWITCH_ID_6176 0x1760
189 #define PORT_SWITCH_ID_6240 0x2400
190 #define PORT_SWITCH_ID_6352 0x3520
192 struct mv88e61xx_phy_priv {
193 struct mii_dev *mdio_bus;
198 static inline int smi_cmd(int cmd, int addr, int reg)
200 cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
202 cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
206 static inline int smi_cmd_read(int addr, int reg)
208 return smi_cmd(SMI_CMD_READ, addr, reg);
211 static inline int smi_cmd_write(int addr, int reg)
213 return smi_cmd(SMI_CMD_WRITE, addr, reg);
216 __weak int mv88e61xx_hw_reset(struct phy_device *phydev)
221 /* Wait for the current SMI indirect command to complete */
222 static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
228 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
229 if (val >= 0 && (val & SMI_BUSY) == 0)
235 puts("SMI busy timeout\n");
240 * The mv88e61xx has three types of addresses: the smi bus address, the device
241 * address, and the register address. The smi bus address distinguishes it on
242 * the smi bus from other PHYs or switches. The device address determines
243 * which on-chip register set you are reading/writing (the various PHYs, their
244 * associated ports, or global configuration registers). The register address
245 * is the offset of the register you are reading/writing.
247 * When the mv88e61xx is hardware configured to have address zero, it behaves in
248 * single-chip addressing mode, where it responds to all SMI addresses, using
249 * the smi address as its device address. This obviously only works when this
250 * is the only chip on the SMI bus. This allows the driver to access device
251 * registers without using indirection. When the chip is configured to a
252 * non-zero address, it only responds to that SMI address and requires indirect
253 * writes to access the different device addresses.
255 static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
257 struct mv88e61xx_phy_priv *priv = phydev->priv;
258 struct mii_dev *mdio_bus = priv->mdio_bus;
259 int smi_addr = priv->smi_addr;
262 /* In single-chip mode, the device can be addressed directly */
264 return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
266 /* Wait for the bus to become free */
267 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
271 /* Issue the read command */
272 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
273 smi_cmd_read(dev, reg));
277 /* Wait for the read command to complete */
278 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
283 res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
287 return bitfield_extract(res, 0, 16);
290 /* See the comment above mv88e61xx_reg_read */
291 static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
294 struct mv88e61xx_phy_priv *priv = phydev->priv;
295 struct mii_dev *mdio_bus = priv->mdio_bus;
296 int smi_addr = priv->smi_addr;
299 /* In single-chip mode, the device can be addressed directly */
301 return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
305 /* Wait for the bus to become free */
306 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
310 /* Set the data to write */
311 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
316 /* Issue the write command */
317 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
318 smi_cmd_write(dev, reg));
322 /* Wait for the write command to complete */
323 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
330 static int mv88e61xx_phy_wait(struct phy_device *phydev)
336 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
337 GLOBAL2_REG_PHY_CMD);
338 if (val >= 0 && (val & SMI_BUSY) == 0)
347 static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
350 struct phy_device *phydev;
353 phydev = (struct phy_device *)smi_wrapper->priv;
355 /* Issue command to read */
356 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
358 smi_cmd_read(dev, reg));
360 /* Wait for data to be read */
361 res = mv88e61xx_phy_wait(phydev);
365 /* Read retrieved data */
366 return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
367 GLOBAL2_REG_PHY_DATA);
370 static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
371 int devad, int reg, u16 data)
373 struct phy_device *phydev;
376 phydev = (struct phy_device *)smi_wrapper->priv;
378 /* Set the data to write */
379 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
380 GLOBAL2_REG_PHY_DATA, data);
383 /* Issue the write command */
384 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
386 smi_cmd_write(dev, reg));
390 /* Wait for command to complete */
391 return mv88e61xx_phy_wait(phydev);
394 /* Wrapper function to make calls to phy_read_indirect simpler */
395 static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
397 return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
398 MDIO_DEVAD_NONE, reg);
401 /* Wrapper function to make calls to phy_read_indirect simpler */
402 static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
405 return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
406 MDIO_DEVAD_NONE, reg, val);
409 static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
411 return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg);
414 static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
417 return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val);
420 static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
422 return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
425 static int mv88e61xx_get_switch_id(struct phy_device *phydev)
429 res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
435 static bool mv88e61xx_6352_family(struct phy_device *phydev)
437 struct mv88e61xx_phy_priv *priv = phydev->priv;
440 case PORT_SWITCH_ID_6172:
441 case PORT_SWITCH_ID_6176:
442 case PORT_SWITCH_ID_6240:
443 case PORT_SWITCH_ID_6352:
449 static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
453 res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
456 return res & PORT_REG_STATUS_CMODE_MASK;
459 static int mv88e61xx_parse_status(struct phy_device *phydev)
462 unsigned int mii_reg;
464 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
466 if ((mii_reg & PHY_REG_STATUS1_LINK) &&
467 !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
470 puts("Waiting for PHY realtime link");
471 while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
472 /* Timeout reached ? */
473 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
474 puts(" TIMEOUT !\n");
479 if ((i++ % 1000) == 0)
482 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
486 udelay(500000); /* another 500 ms (results in faster booting) */
488 if (mii_reg & PHY_REG_STATUS1_LINK)
494 if (mii_reg & PHY_REG_STATUS1_DUPLEX)
495 phydev->duplex = DUPLEX_FULL;
497 phydev->duplex = DUPLEX_HALF;
499 speed = mii_reg & PHY_REG_STATUS1_SPEED;
502 case PHY_REG_STATUS1_GBIT:
503 phydev->speed = SPEED_1000;
505 case PHY_REG_STATUS1_100:
506 phydev->speed = SPEED_100;
509 phydev->speed = SPEED_10;
516 static int mv88e61xx_switch_reset(struct phy_device *phydev)
522 /* Disable all ports */
523 for (port = 0; port < PORT_COUNT; port++) {
524 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
527 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
528 PORT_REG_CTRL_PSTATE_WIDTH,
529 PORT_REG_CTRL_PSTATE_DISABLED);
530 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
535 /* Wait 2 ms for queues to drain */
539 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_CTRL);
542 val |= GLOBAL1_CTRL_SWRESET;
543 val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
548 /* Wait up to 1 second for switch reset complete */
549 for (time = 1000; time; time--) {
550 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1,
552 if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
562 static int mv88e61xx_serdes_init(struct phy_device *phydev)
566 val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
570 /* Power up serdes module */
571 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
574 val &= ~(BMCR_PDOWN);
575 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
582 static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
586 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
589 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
590 PORT_REG_CTRL_PSTATE_WIDTH,
591 PORT_REG_CTRL_PSTATE_FORWARD);
592 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
599 static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
604 /* Set VID to port number plus one */
605 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
608 val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
609 PORT_REG_VLAN_ID_DEF_VID_WIDTH,
611 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
616 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
619 val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
620 PORT_REG_VLAN_MAP_TABLE_WIDTH,
622 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
629 static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
635 val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
638 if (!(val & PORT_REG_STATUS_LINK)) {
639 /* Temporarily force link to read port configuration */
643 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
646 val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
647 PORT_REG_PHYS_CTRL_LINK_VALUE);
648 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
653 /* Wait for status register to reflect forced link */
655 val = mv88e61xx_port_read(phydev, port,
661 if (val & PORT_REG_STATUS_LINK)
671 if (val & PORT_REG_STATUS_DUPLEX)
672 phydev->duplex = DUPLEX_FULL;
674 phydev->duplex = DUPLEX_HALF;
676 val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
677 PORT_REG_STATUS_SPEED_WIDTH);
679 case PORT_REG_STATUS_SPEED_1000:
680 phydev->speed = SPEED_1000;
682 case PORT_REG_STATUS_SPEED_100:
683 phydev->speed = SPEED_100;
686 phydev->speed = SPEED_10;
694 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
697 val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
698 PORT_REG_PHYS_CTRL_LINK_VALUE);
699 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
708 static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
712 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
716 val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK |
717 PORT_REG_PHYS_CTRL_FC_VALUE);
718 val |= PORT_REG_PHYS_CTRL_PCS_AN_EN |
719 PORT_REG_PHYS_CTRL_PCS_AN_RST |
720 PORT_REG_PHYS_CTRL_FC_FORCE |
721 PORT_REG_PHYS_CTRL_DUPLEX_VALUE |
722 PORT_REG_PHYS_CTRL_DUPLEX_FORCE |
723 PORT_REG_PHYS_CTRL_SPD1000;
725 if (port == CONFIG_MV88E61XX_CPU_PORT)
726 val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
727 PORT_REG_PHYS_CTRL_LINK_FORCE;
729 return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
733 static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
738 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_MON_CTRL);
741 val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
742 GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
743 CONFIG_MV88E61XX_CPU_PORT);
744 val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
745 GLOBAL1_MON_CTRL, val);
749 /* Allow CPU to route to any port */
750 val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
751 val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
755 /* Enable CPU port */
756 val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
760 val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
764 /* If CPU is connected to serdes, initialize serdes */
765 if (mv88e61xx_6352_family(phydev)) {
766 val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
769 if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
770 val == PORT_REG_STATUS_CMODE_1000BASE_X ||
771 val == PORT_REG_STATUS_CMODE_SGMII) {
772 val = mv88e61xx_serdes_init(phydev);
777 val = mv88e61xx_fixed_port_setup(phydev,
778 CONFIG_MV88E61XX_CPU_PORT);
786 static int mv88e61xx_switch_init(struct phy_device *phydev)
794 res = mv88e61xx_switch_reset(phydev);
798 res = mv88e61xx_set_cpu_port(phydev);
807 static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
811 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
814 val &= ~(BMCR_PDOWN);
815 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
822 static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
827 * Enable energy-detect sensing on PHY, used to determine when a PHY
828 * port is physically connected
830 val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
833 val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT,
834 PHY_REG_CTRL1_ENERGY_DET_WIDTH,
835 PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT);
836 val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
843 static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
847 val = mv88e61xx_port_enable(phydev, phy);
851 val = mv88e61xx_port_set_vlan(phydev, phy,
852 1 << CONFIG_MV88E61XX_CPU_PORT);
859 static int mv88e61xx_probe(struct phy_device *phydev)
861 struct mii_dev *smi_wrapper;
862 struct mv88e61xx_phy_priv *priv;
865 res = mv88e61xx_hw_reset(phydev);
869 priv = malloc(sizeof(*priv));
873 memset(priv, 0, sizeof(*priv));
876 * This device requires indirect reads/writes to the PHY registers
877 * which the generic PHY code can't handle. Make a wrapper MII device
878 * to handle reads/writes
880 smi_wrapper = mdio_alloc();
887 * Store the mdio bus in the private data, as we are going to replace
888 * the bus with the wrapper bus
890 priv->mdio_bus = phydev->bus;
893 * Store the smi bus address in private data. This lets us use the
894 * phydev addr field for device address instead, as the genphy code
897 priv->smi_addr = phydev->addr;
900 * Store the phy_device in the wrapper mii device. This lets us get it
901 * back when genphy functions call phy_read/phy_write.
903 smi_wrapper->priv = phydev;
904 strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
905 smi_wrapper->read = mv88e61xx_phy_read_indirect;
906 smi_wrapper->write = mv88e61xx_phy_write_indirect;
908 /* Replace the bus with the wrapper device */
909 phydev->bus = smi_wrapper;
913 priv->id = mv88e61xx_get_switch_id(phydev);
918 static int mv88e61xx_phy_config(struct phy_device *phydev)
924 res = mv88e61xx_switch_init(phydev);
928 for (i = 0; i < PORT_COUNT; i++) {
929 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
932 res = mv88e61xx_phy_enable(phydev, i);
934 printf("Error enabling PHY %i\n", i);
937 res = mv88e61xx_phy_setup(phydev, i);
939 printf("Error setting up PHY %i\n", i);
942 res = mv88e61xx_phy_config_port(phydev, i);
944 printf("Error configuring PHY %i\n", i);
948 res = phy_reset(phydev);
950 printf("Error resetting PHY %i\n", i);
953 res = genphy_config_aneg(phydev);
955 printf("Error setting PHY %i autoneg\n", i);
959 /* Return success if any PHY succeeds */
961 } else if ((1 << i) & CONFIG_MV88E61XX_FIXED_PORTS) {
962 res = mv88e61xx_fixed_port_setup(phydev, i);
964 printf("Error configuring port %i\n", i);
973 static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
977 val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
982 * After reset, the energy detect signal remains high for a few seconds
983 * regardless of whether a cable is connected. This function will
984 * return false positives during this time.
986 return (val & PHY_REG_STATUS1_ENERGY) == 0;
989 static int mv88e61xx_phy_startup(struct phy_device *phydev)
994 int speed = phydev->speed;
995 int duplex = phydev->duplex;
997 for (i = 0; i < PORT_COUNT; i++) {
998 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
1000 if (!mv88e61xx_phy_is_connected(phydev))
1002 res = genphy_update_link(phydev);
1005 res = mv88e61xx_parse_status(phydev);
1008 link = (link || phydev->link);
1011 phydev->link = link;
1013 /* Restore CPU interface speed and duplex after it was changed for
1015 phydev->speed = speed;
1016 phydev->duplex = duplex;
1021 static struct phy_driver mv88e61xx_driver = {
1022 .name = "Marvell MV88E61xx",
1025 .features = PHY_GBIT_FEATURES,
1026 .probe = mv88e61xx_probe,
1027 .config = mv88e61xx_phy_config,
1028 .startup = mv88e61xx_phy_startup,
1029 .shutdown = &genphy_shutdown,
1032 static struct phy_driver mv88e609x_driver = {
1033 .name = "Marvell MV88E609x",
1036 .features = PHY_GBIT_FEATURES,
1037 .probe = mv88e61xx_probe,
1038 .config = mv88e61xx_phy_config,
1039 .startup = mv88e61xx_phy_startup,
1040 .shutdown = &genphy_shutdown,
1043 int phy_mv88e61xx_init(void)
1045 phy_register(&mv88e61xx_driver);
1046 phy_register(&mv88e609x_driver);
1052 * Overload weak get_phy_id definition since we need non-standard functions
1053 * to read PHY registers
1055 int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
1057 struct phy_device temp_phy;
1058 struct mv88e61xx_phy_priv temp_priv;
1059 struct mii_dev temp_mii;
1063 * Buid temporary data structures that the chip reading code needs to
1066 temp_priv.mdio_bus = bus;
1067 temp_priv.smi_addr = smi_addr;
1068 temp_phy.priv = &temp_priv;
1069 temp_mii.priv = &temp_phy;
1071 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
1075 *phy_id = val << 16;
1077 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
1081 *phy_id |= (val & 0xffff);