3 * Elecsys Corporation <www.elecsyscorp.com>
4 * Kevin Smith <kevin.smith@elecsyscorp.com>
8 * Marvell Semiconductor <www.marvell.com>
9 * Prafulla Wadaskar <prafulla@marvell.com>
11 * SPDX-License-Identifier: GPL-2.0+
15 * PHY driver for mv88e61xx ethernet switches.
17 * This driver configures the mv88e61xx for basic use as a PHY. The switch
18 * supports a VLAN configuration that determines how traffic will be routed
19 * between the ports. This driver uses a simple configuration that routes
20 * traffic from each PHY port only to the CPU port, and from the CPU port to
23 * The configuration determines which PHY ports to activate using the
24 * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit
25 * 1 activates port 1, etc. Do not set the bit for the port the CPU is
26 * connected to unless it is connected over a PHY interface (not MII).
28 * This driver was written for and tested on the mv88e6176 with an SGMII
29 * connection. Other configurations should be supported, but some additions or
30 * changes may be required.
41 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
44 #define PORT_MASK ((1 << PORT_COUNT) - 1)
46 /* Device addresses */
47 #define DEVADDR_PHY(p) (p)
48 #define DEVADDR_PORT(p) (0x10 + (p))
49 #define DEVADDR_SERDES 0x0F
50 #define DEVADDR_GLOBAL_1 0x1B
51 #define DEVADDR_GLOBAL_2 0x1C
53 /* SMI indirection registers for multichip addressing mode */
54 #define SMI_CMD_REG 0x00
55 #define SMI_DATA_REG 0x01
57 /* Global registers */
58 #define GLOBAL1_STATUS 0x00
59 #define GLOBAL1_CTRL 0x04
60 #define GLOBAL1_MON_CTRL 0x1A
62 /* Global 2 registers */
63 #define GLOBAL2_REG_PHY_CMD 0x18
64 #define GLOBAL2_REG_PHY_DATA 0x19
67 #define PORT_REG_STATUS 0x00
68 #define PORT_REG_PHYS_CTRL 0x01
69 #define PORT_REG_SWITCH_ID 0x03
70 #define PORT_REG_CTRL 0x04
71 #define PORT_REG_VLAN_MAP 0x06
72 #define PORT_REG_VLAN_ID 0x07
75 #define PHY_REG_CTRL1 0x10
76 #define PHY_REG_STATUS1 0x11
77 #define PHY_REG_PAGE 0x16
79 /* Serdes registers */
80 #define SERDES_REG_CTRL_1 0x10
82 /* Phy page numbers */
83 #define PHY_PAGE_COPPER 0
84 #define PHY_PAGE_SERDES 1
87 #define GLOBAL1_CTRL_SWRESET BIT(15)
89 #define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
90 #define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
92 #define PORT_REG_STATUS_LINK BIT(11)
93 #define PORT_REG_STATUS_DUPLEX BIT(10)
95 #define PORT_REG_STATUS_SPEED_SHIFT 8
96 #define PORT_REG_STATUS_SPEED_WIDTH 2
97 #define PORT_REG_STATUS_SPEED_10 0
98 #define PORT_REG_STATUS_SPEED_100 1
99 #define PORT_REG_STATUS_SPEED_1000 2
101 #define PORT_REG_STATUS_CMODE_MASK 0xF
102 #define PORT_REG_STATUS_CMODE_100BASE_X 0x8
103 #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
104 #define PORT_REG_STATUS_CMODE_SGMII 0xa
106 #define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
107 #define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
108 #define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
109 #define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6)
110 #define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
111 #define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
112 #define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3)
113 #define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2)
114 #define PORT_REG_PHYS_CTRL_SPD1000 BIT(1)
115 #define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0))
117 #define PORT_REG_CTRL_PSTATE_SHIFT 0
118 #define PORT_REG_CTRL_PSTATE_WIDTH 2
120 #define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
121 #define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
123 #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0
124 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
126 #define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
128 #define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8
129 #define PHY_REG_CTRL1_ENERGY_DET_WIDTH 2
132 #define PORT_REG_CTRL_PSTATE_DISABLED 0
133 #define PORT_REG_CTRL_PSTATE_FORWARD 3
135 #define PHY_REG_CTRL1_ENERGY_DET_OFF 0
136 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2
137 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3
139 /* PHY Status Register */
140 #define PHY_REG_STATUS1_SPEED 0xc000
141 #define PHY_REG_STATUS1_GBIT 0x8000
142 #define PHY_REG_STATUS1_100 0x4000
143 #define PHY_REG_STATUS1_DUPLEX 0x2000
144 #define PHY_REG_STATUS1_SPDDONE 0x0800
145 #define PHY_REG_STATUS1_LINK 0x0400
146 #define PHY_REG_STATUS1_ENERGY 0x0010
149 * Macros for building commands for indirect addressing modes. These are valid
150 * for both the indirect multichip addressing mode and the PHY indirection
151 * required for the writes to any PHY register.
153 #define SMI_BUSY BIT(15)
154 #define SMI_CMD_CLAUSE_22 BIT(12)
155 #define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
156 #define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
158 #define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
159 SMI_CMD_CLAUSE_22_OP_READ)
160 #define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
161 SMI_CMD_CLAUSE_22_OP_WRITE)
163 #define SMI_CMD_ADDR_SHIFT 5
164 #define SMI_CMD_ADDR_WIDTH 5
165 #define SMI_CMD_REG_SHIFT 0
166 #define SMI_CMD_REG_WIDTH 5
168 /* Check for required macros */
169 #ifndef CONFIG_MV88E61XX_PHY_PORTS
170 #error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
173 #ifndef CONFIG_MV88E61XX_CPU_PORT
174 #error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
178 * These are ports without PHYs that may be wired directly
179 * to other serdes interfaces
181 #ifndef CONFIG_MV88E61XX_FIXED_PORTS
182 #define CONFIG_MV88E61XX_FIXED_PORTS 0
185 /* ID register values for different switch models */
186 #define PORT_SWITCH_ID_6096 0x0980
187 #define PORT_SWITCH_ID_6097 0x0990
188 #define PORT_SWITCH_ID_6172 0x1720
189 #define PORT_SWITCH_ID_6176 0x1760
190 #define PORT_SWITCH_ID_6240 0x2400
191 #define PORT_SWITCH_ID_6352 0x3520
193 struct mv88e61xx_phy_priv {
194 struct mii_dev *mdio_bus;
199 static inline int smi_cmd(int cmd, int addr, int reg)
201 cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
203 cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
207 static inline int smi_cmd_read(int addr, int reg)
209 return smi_cmd(SMI_CMD_READ, addr, reg);
212 static inline int smi_cmd_write(int addr, int reg)
214 return smi_cmd(SMI_CMD_WRITE, addr, reg);
217 __weak int mv88e61xx_hw_reset(struct phy_device *phydev)
222 /* Wait for the current SMI indirect command to complete */
223 static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
229 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
230 if (val >= 0 && (val & SMI_BUSY) == 0)
236 puts("SMI busy timeout\n");
241 * The mv88e61xx has three types of addresses: the smi bus address, the device
242 * address, and the register address. The smi bus address distinguishes it on
243 * the smi bus from other PHYs or switches. The device address determines
244 * which on-chip register set you are reading/writing (the various PHYs, their
245 * associated ports, or global configuration registers). The register address
246 * is the offset of the register you are reading/writing.
248 * When the mv88e61xx is hardware configured to have address zero, it behaves in
249 * single-chip addressing mode, where it responds to all SMI addresses, using
250 * the smi address as its device address. This obviously only works when this
251 * is the only chip on the SMI bus. This allows the driver to access device
252 * registers without using indirection. When the chip is configured to a
253 * non-zero address, it only responds to that SMI address and requires indirect
254 * writes to access the different device addresses.
256 static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
258 struct mv88e61xx_phy_priv *priv = phydev->priv;
259 struct mii_dev *mdio_bus = priv->mdio_bus;
260 int smi_addr = priv->smi_addr;
263 /* In single-chip mode, the device can be addressed directly */
265 return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
267 /* Wait for the bus to become free */
268 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
272 /* Issue the read command */
273 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
274 smi_cmd_read(dev, reg));
278 /* Wait for the read command to complete */
279 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
284 res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
288 return bitfield_extract(res, 0, 16);
291 /* See the comment above mv88e61xx_reg_read */
292 static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
295 struct mv88e61xx_phy_priv *priv = phydev->priv;
296 struct mii_dev *mdio_bus = priv->mdio_bus;
297 int smi_addr = priv->smi_addr;
300 /* In single-chip mode, the device can be addressed directly */
302 return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
306 /* Wait for the bus to become free */
307 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
311 /* Set the data to write */
312 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
317 /* Issue the write command */
318 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
319 smi_cmd_write(dev, reg));
323 /* Wait for the write command to complete */
324 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
331 static int mv88e61xx_phy_wait(struct phy_device *phydev)
337 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
338 GLOBAL2_REG_PHY_CMD);
339 if (val >= 0 && (val & SMI_BUSY) == 0)
348 static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
351 struct phy_device *phydev;
354 phydev = (struct phy_device *)smi_wrapper->priv;
356 /* Issue command to read */
357 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
359 smi_cmd_read(dev, reg));
361 /* Wait for data to be read */
362 res = mv88e61xx_phy_wait(phydev);
366 /* Read retrieved data */
367 return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
368 GLOBAL2_REG_PHY_DATA);
371 static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
372 int devad, int reg, u16 data)
374 struct phy_device *phydev;
377 phydev = (struct phy_device *)smi_wrapper->priv;
379 /* Set the data to write */
380 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
381 GLOBAL2_REG_PHY_DATA, data);
384 /* Issue the write command */
385 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
387 smi_cmd_write(dev, reg));
391 /* Wait for command to complete */
392 return mv88e61xx_phy_wait(phydev);
395 /* Wrapper function to make calls to phy_read_indirect simpler */
396 static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
398 return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
399 MDIO_DEVAD_NONE, reg);
402 /* Wrapper function to make calls to phy_read_indirect simpler */
403 static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
406 return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
407 MDIO_DEVAD_NONE, reg, val);
410 static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
412 return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg);
415 static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
418 return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val);
421 static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
423 return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
426 static int mv88e61xx_get_switch_id(struct phy_device *phydev)
430 res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
436 static bool mv88e61xx_6352_family(struct phy_device *phydev)
438 struct mv88e61xx_phy_priv *priv = phydev->priv;
441 case PORT_SWITCH_ID_6172:
442 case PORT_SWITCH_ID_6176:
443 case PORT_SWITCH_ID_6240:
444 case PORT_SWITCH_ID_6352:
450 static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
454 res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
457 return res & PORT_REG_STATUS_CMODE_MASK;
460 static int mv88e61xx_parse_status(struct phy_device *phydev)
463 unsigned int mii_reg;
465 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
467 if ((mii_reg & PHY_REG_STATUS1_LINK) &&
468 !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
471 puts("Waiting for PHY realtime link");
472 while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
473 /* Timeout reached ? */
474 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
475 puts(" TIMEOUT !\n");
480 if ((i++ % 1000) == 0)
483 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
487 udelay(500000); /* another 500 ms (results in faster booting) */
489 if (mii_reg & PHY_REG_STATUS1_LINK)
495 if (mii_reg & PHY_REG_STATUS1_DUPLEX)
496 phydev->duplex = DUPLEX_FULL;
498 phydev->duplex = DUPLEX_HALF;
500 speed = mii_reg & PHY_REG_STATUS1_SPEED;
503 case PHY_REG_STATUS1_GBIT:
504 phydev->speed = SPEED_1000;
506 case PHY_REG_STATUS1_100:
507 phydev->speed = SPEED_100;
510 phydev->speed = SPEED_10;
517 static int mv88e61xx_switch_reset(struct phy_device *phydev)
523 /* Disable all ports */
524 for (port = 0; port < PORT_COUNT; port++) {
525 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
528 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
529 PORT_REG_CTRL_PSTATE_WIDTH,
530 PORT_REG_CTRL_PSTATE_DISABLED);
531 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
536 /* Wait 2 ms for queues to drain */
540 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_CTRL);
543 val |= GLOBAL1_CTRL_SWRESET;
544 val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
549 /* Wait up to 1 second for switch reset complete */
550 for (time = 1000; time; time--) {
551 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1,
553 if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
563 static int mv88e61xx_serdes_init(struct phy_device *phydev)
567 val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
571 /* Power up serdes module */
572 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
575 val &= ~(BMCR_PDOWN);
576 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
583 static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
587 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
590 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
591 PORT_REG_CTRL_PSTATE_WIDTH,
592 PORT_REG_CTRL_PSTATE_FORWARD);
593 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
600 static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
605 /* Set VID to port number plus one */
606 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
609 val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
610 PORT_REG_VLAN_ID_DEF_VID_WIDTH,
612 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
617 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
620 val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
621 PORT_REG_VLAN_MAP_TABLE_WIDTH,
623 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
630 static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
636 val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
639 if (!(val & PORT_REG_STATUS_LINK)) {
640 /* Temporarily force link to read port configuration */
644 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
647 val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
648 PORT_REG_PHYS_CTRL_LINK_VALUE);
649 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
654 /* Wait for status register to reflect forced link */
656 val = mv88e61xx_port_read(phydev, port,
660 if (val & PORT_REG_STATUS_LINK)
670 if (val & PORT_REG_STATUS_DUPLEX)
671 phydev->duplex = DUPLEX_FULL;
673 phydev->duplex = DUPLEX_HALF;
675 val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
676 PORT_REG_STATUS_SPEED_WIDTH);
678 case PORT_REG_STATUS_SPEED_1000:
679 phydev->speed = SPEED_1000;
681 case PORT_REG_STATUS_SPEED_100:
682 phydev->speed = SPEED_100;
685 phydev->speed = SPEED_10;
693 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
696 val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
697 PORT_REG_PHYS_CTRL_LINK_VALUE);
698 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
707 static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
712 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_MON_CTRL);
715 val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
716 GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
717 CONFIG_MV88E61XX_CPU_PORT);
718 val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
719 GLOBAL1_MON_CTRL, val);
723 /* Allow CPU to route to any port */
724 val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
725 val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
729 /* Enable CPU port */
730 val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
734 val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
738 /* If CPU is connected to serdes, initialize serdes */
739 if (mv88e61xx_6352_family(phydev)) {
740 val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
743 if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
744 val == PORT_REG_STATUS_CMODE_1000BASE_X ||
745 val == PORT_REG_STATUS_CMODE_SGMII) {
746 val = mv88e61xx_serdes_init(phydev);
755 static int mv88e61xx_switch_init(struct phy_device *phydev)
763 res = mv88e61xx_switch_reset(phydev);
767 res = mv88e61xx_set_cpu_port(phydev);
776 static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
780 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
783 val &= ~(BMCR_PDOWN);
784 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
791 static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
796 * Enable energy-detect sensing on PHY, used to determine when a PHY
797 * port is physically connected
799 val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
802 val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT,
803 PHY_REG_CTRL1_ENERGY_DET_WIDTH,
804 PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT);
805 val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
812 static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
816 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
820 val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK |
821 PORT_REG_PHYS_CTRL_FC_VALUE);
822 val |= PORT_REG_PHYS_CTRL_PCS_AN_EN |
823 PORT_REG_PHYS_CTRL_PCS_AN_RST |
824 PORT_REG_PHYS_CTRL_FC_FORCE |
825 PORT_REG_PHYS_CTRL_DUPLEX_VALUE |
826 PORT_REG_PHYS_CTRL_DUPLEX_FORCE |
827 PORT_REG_PHYS_CTRL_SPD1000;
829 return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
833 static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
837 val = mv88e61xx_port_enable(phydev, phy);
841 val = mv88e61xx_port_set_vlan(phydev, phy,
842 1 << CONFIG_MV88E61XX_CPU_PORT);
849 static int mv88e61xx_probe(struct phy_device *phydev)
851 struct mii_dev *smi_wrapper;
852 struct mv88e61xx_phy_priv *priv;
855 res = mv88e61xx_hw_reset(phydev);
859 priv = malloc(sizeof(*priv));
863 memset(priv, 0, sizeof(*priv));
866 * This device requires indirect reads/writes to the PHY registers
867 * which the generic PHY code can't handle. Make a wrapper MII device
868 * to handle reads/writes
870 smi_wrapper = mdio_alloc();
877 * Store the mdio bus in the private data, as we are going to replace
878 * the bus with the wrapper bus
880 priv->mdio_bus = phydev->bus;
883 * Store the smi bus address in private data. This lets us use the
884 * phydev addr field for device address instead, as the genphy code
887 priv->smi_addr = phydev->addr;
890 * Store the phy_device in the wrapper mii device. This lets us get it
891 * back when genphy functions call phy_read/phy_write.
893 smi_wrapper->priv = phydev;
894 strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
895 smi_wrapper->read = mv88e61xx_phy_read_indirect;
896 smi_wrapper->write = mv88e61xx_phy_write_indirect;
898 /* Replace the bus with the wrapper device */
899 phydev->bus = smi_wrapper;
903 priv->id = mv88e61xx_get_switch_id(phydev);
908 static int mv88e61xx_phy_config(struct phy_device *phydev)
914 res = mv88e61xx_switch_init(phydev);
918 for (i = 0; i < PORT_COUNT; i++) {
919 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
922 res = mv88e61xx_phy_enable(phydev, i);
924 printf("Error enabling PHY %i\n", i);
927 res = mv88e61xx_phy_setup(phydev, i);
929 printf("Error setting up PHY %i\n", i);
932 res = mv88e61xx_phy_config_port(phydev, i);
934 printf("Error configuring PHY %i\n", i);
938 res = genphy_config_aneg(phydev);
940 printf("Error setting PHY %i autoneg\n", i);
943 res = phy_reset(phydev);
945 printf("Error resetting PHY %i\n", i);
949 /* Return success if any PHY succeeds */
951 } else if ((1 << i) & CONFIG_MV88E61XX_FIXED_PORTS) {
952 res = mv88e61xx_fixed_port_setup(phydev, i);
954 printf("Error configuring port %i\n", i);
963 static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
967 val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
972 * After reset, the energy detect signal remains high for a few seconds
973 * regardless of whether a cable is connected. This function will
974 * return false positives during this time.
976 return (val & PHY_REG_STATUS1_ENERGY) == 0;
979 static int mv88e61xx_phy_startup(struct phy_device *phydev)
984 int speed = phydev->speed;
985 int duplex = phydev->duplex;
987 for (i = 0; i < PORT_COUNT; i++) {
988 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
990 if (!mv88e61xx_phy_is_connected(phydev))
992 res = genphy_update_link(phydev);
995 res = mv88e61xx_parse_status(phydev);
998 link = (link || phydev->link);
1001 phydev->link = link;
1003 /* Restore CPU interface speed and duplex after it was changed for
1005 phydev->speed = speed;
1006 phydev->duplex = duplex;
1011 static struct phy_driver mv88e61xx_driver = {
1012 .name = "Marvell MV88E61xx",
1015 .features = PHY_GBIT_FEATURES,
1016 .probe = mv88e61xx_probe,
1017 .config = mv88e61xx_phy_config,
1018 .startup = mv88e61xx_phy_startup,
1019 .shutdown = &genphy_shutdown,
1022 static struct phy_driver mv88e609x_driver = {
1023 .name = "Marvell MV88E609x",
1026 .features = PHY_GBIT_FEATURES,
1027 .probe = mv88e61xx_probe,
1028 .config = mv88e61xx_phy_config,
1029 .startup = mv88e61xx_phy_startup,
1030 .shutdown = &genphy_shutdown,
1033 int phy_mv88e61xx_init(void)
1035 phy_register(&mv88e61xx_driver);
1036 phy_register(&mv88e609x_driver);
1042 * Overload weak get_phy_id definition since we need non-standard functions
1043 * to read PHY registers
1045 int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
1047 struct phy_device temp_phy;
1048 struct mv88e61xx_phy_priv temp_priv;
1049 struct mii_dev temp_mii;
1053 * Buid temporary data structures that the chip reading code needs to
1056 temp_priv.mdio_bus = bus;
1057 temp_priv.smi_addr = smi_addr;
1058 temp_phy.priv = &temp_priv;
1059 temp_mii.priv = &temp_phy;
1061 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
1065 *phy_id = val << 16;
1067 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
1071 *phy_id |= (val & 0xffff);