1 // SPDX-License-Identifier: GPL-2.0+
4 * Elecsys Corporation <www.elecsyscorp.com>
5 * Kevin Smith <kevin.smith@elecsyscorp.com>
9 * Marvell Semiconductor <www.marvell.com>
10 * Prafulla Wadaskar <prafulla@marvell.com>
14 * PHY driver for mv88e61xx ethernet switches.
16 * This driver configures the mv88e61xx for basic use as a PHY. The switch
17 * supports a VLAN configuration that determines how traffic will be routed
18 * between the ports. This driver uses a simple configuration that routes
19 * traffic from each PHY port only to the CPU port, and from the CPU port to
22 * The configuration determines which PHY ports to activate using the
23 * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit
24 * 1 activates port 1, etc. Do not set the bit for the port the CPU is
25 * connected to unless it is connected over a PHY interface (not MII).
27 * This driver was written for and tested on the mv88e6176 with an SGMII
28 * connection. Other configurations should be supported, but some additions or
29 * changes may be required.
34 #include <linux/delay.h>
42 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
44 #define PORT_MASK(port_count) ((1 << (port_count)) - 1)
46 /* Device addresses */
47 #define DEVADDR_PHY(p) (p)
48 #define DEVADDR_SERDES 0x0F
50 /* SMI indirection registers for multichip addressing mode */
51 #define SMI_CMD_REG 0x00
52 #define SMI_DATA_REG 0x01
54 /* Global registers */
55 #define GLOBAL1_STATUS 0x00
56 #define GLOBAL1_CTRL 0x04
57 #define GLOBAL1_MON_CTRL 0x1A
59 /* Global 2 registers */
60 #define GLOBAL2_REG_PHY_CMD 0x18
61 #define GLOBAL2_REG_PHY_DATA 0x19
64 #define PORT_REG_STATUS 0x00
65 #define PORT_REG_PHYS_CTRL 0x01
66 #define PORT_REG_SWITCH_ID 0x03
67 #define PORT_REG_CTRL 0x04
68 #define PORT_REG_VLAN_MAP 0x06
69 #define PORT_REG_VLAN_ID 0x07
72 #define PHY_REG_CTRL1 0x10
73 #define PHY_REG_STATUS1 0x11
74 #define PHY_REG_PAGE 0x16
76 /* Serdes registers */
77 #define SERDES_REG_CTRL_1 0x10
79 /* Phy page numbers */
80 #define PHY_PAGE_COPPER 0
81 #define PHY_PAGE_SERDES 1
84 #define GLOBAL1_CTRL_SWRESET BIT(15)
86 #define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
87 #define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
89 #define PORT_REG_STATUS_SPEED_SHIFT 8
90 #define PORT_REG_STATUS_SPEED_10 0
91 #define PORT_REG_STATUS_SPEED_100 1
92 #define PORT_REG_STATUS_SPEED_1000 2
94 #define PORT_REG_STATUS_CMODE_MASK 0xF
95 #define PORT_REG_STATUS_CMODE_100BASE_X 0x8
96 #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
97 #define PORT_REG_STATUS_CMODE_SGMII 0xa
99 #define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
100 #define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
101 #define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
102 #define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6)
103 #define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
104 #define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
105 #define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3)
106 #define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2)
107 #define PORT_REG_PHYS_CTRL_SPD1000 BIT(1)
108 #define PORT_REG_PHYS_CTRL_SPD100 BIT(0)
109 #define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0))
111 #define PORT_REG_CTRL_PSTATE_SHIFT 0
112 #define PORT_REG_CTRL_PSTATE_WIDTH 2
114 #define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
115 #define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
117 #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0
118 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
120 #define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
123 #define PORT_REG_CTRL_PSTATE_DISABLED 0
124 #define PORT_REG_CTRL_PSTATE_FORWARD 3
126 #define PHY_REG_CTRL1_ENERGY_DET_OFF 0
127 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_PULSE 1
128 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2
129 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3
131 /* PHY Status Register */
132 #define PHY_REG_STATUS1_SPEED 0xc000
133 #define PHY_REG_STATUS1_GBIT 0x8000
134 #define PHY_REG_STATUS1_100 0x4000
135 #define PHY_REG_STATUS1_DUPLEX 0x2000
136 #define PHY_REG_STATUS1_SPDDONE 0x0800
137 #define PHY_REG_STATUS1_LINK 0x0400
138 #define PHY_REG_STATUS1_ENERGY 0x0010
141 * Macros for building commands for indirect addressing modes. These are valid
142 * for both the indirect multichip addressing mode and the PHY indirection
143 * required for the writes to any PHY register.
145 #define SMI_BUSY BIT(15)
146 #define SMI_CMD_CLAUSE_22 BIT(12)
147 #define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
148 #define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
150 #define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
151 SMI_CMD_CLAUSE_22_OP_READ)
152 #define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
153 SMI_CMD_CLAUSE_22_OP_WRITE)
155 #define SMI_CMD_ADDR_SHIFT 5
156 #define SMI_CMD_ADDR_WIDTH 5
157 #define SMI_CMD_REG_SHIFT 0
158 #define SMI_CMD_REG_WIDTH 5
160 /* Check for required macros */
161 #ifndef CONFIG_MV88E61XX_PHY_PORTS
162 #error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
165 #ifndef CONFIG_MV88E61XX_CPU_PORT
166 #error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
170 * These are ports without PHYs that may be wired directly
171 * to other serdes interfaces
173 #ifndef CONFIG_MV88E61XX_FIXED_PORTS
174 #define CONFIG_MV88E61XX_FIXED_PORTS 0
177 /* ID register values for different switch models */
178 #define PORT_SWITCH_ID_6020 0x0200
179 #define PORT_SWITCH_ID_6070 0x0700
180 #define PORT_SWITCH_ID_6071 0x0710
181 #define PORT_SWITCH_ID_6096 0x0980
182 #define PORT_SWITCH_ID_6097 0x0990
183 #define PORT_SWITCH_ID_6172 0x1720
184 #define PORT_SWITCH_ID_6176 0x1760
185 #define PORT_SWITCH_ID_6220 0x2200
186 #define PORT_SWITCH_ID_6240 0x2400
187 #define PORT_SWITCH_ID_6250 0x2500
188 #define PORT_SWITCH_ID_6352 0x3520
190 struct mv88e61xx_phy_priv {
191 struct mii_dev *mdio_bus;
194 int port_count; /* Number of switch ports */
195 int port_reg_base; /* Base of the switch port registers */
196 u16 port_stat_link_mask;/* Bitmask for port link status bits */
197 u16 port_stat_dup_mask; /* Bitmask for port duplex status bits */
198 u8 port_stat_speed_width;/* Width of speed status bitfield */
199 u8 global1; /* Offset of Switch Global 1 registers */
200 u8 global2; /* Offset of Switch Global 2 registers */
201 u8 phy_ctrl1_en_det_shift; /* 'EDet' bit field offset */
202 u8 phy_ctrl1_en_det_width; /* Width of 'EDet' bit field */
203 u8 phy_ctrl1_en_det_ctrl; /* 'EDet' control value */
206 static inline int smi_cmd(int cmd, int addr, int reg)
208 cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
210 cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
214 static inline int smi_cmd_read(int addr, int reg)
216 return smi_cmd(SMI_CMD_READ, addr, reg);
219 static inline int smi_cmd_write(int addr, int reg)
221 return smi_cmd(SMI_CMD_WRITE, addr, reg);
224 __weak int mv88e61xx_hw_reset(struct phy_device *phydev)
229 /* Wait for the current SMI indirect command to complete */
230 static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
236 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
237 if (val >= 0 && (val & SMI_BUSY) == 0)
243 puts("SMI busy timeout\n");
248 * The mv88e61xx has three types of addresses: the smi bus address, the device
249 * address, and the register address. The smi bus address distinguishes it on
250 * the smi bus from other PHYs or switches. The device address determines
251 * which on-chip register set you are reading/writing (the various PHYs, their
252 * associated ports, or global configuration registers). The register address
253 * is the offset of the register you are reading/writing.
255 * When the mv88e61xx is hardware configured to have address zero, it behaves in
256 * single-chip addressing mode, where it responds to all SMI addresses, using
257 * the smi address as its device address. This obviously only works when this
258 * is the only chip on the SMI bus. This allows the driver to access device
259 * registers without using indirection. When the chip is configured to a
260 * non-zero address, it only responds to that SMI address and requires indirect
261 * writes to access the different device addresses.
263 static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
265 struct mv88e61xx_phy_priv *priv = phydev->priv;
266 struct mii_dev *mdio_bus = priv->mdio_bus;
267 int smi_addr = priv->smi_addr;
270 /* In single-chip mode, the device can be addressed directly */
272 return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
274 /* Wait for the bus to become free */
275 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
279 /* Issue the read command */
280 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
281 smi_cmd_read(dev, reg));
285 /* Wait for the read command to complete */
286 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
291 res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
295 return bitfield_extract(res, 0, 16);
298 /* See the comment above mv88e61xx_reg_read */
299 static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
302 struct mv88e61xx_phy_priv *priv = phydev->priv;
303 struct mii_dev *mdio_bus = priv->mdio_bus;
304 int smi_addr = priv->smi_addr;
307 /* In single-chip mode, the device can be addressed directly */
309 return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
313 /* Wait for the bus to become free */
314 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
318 /* Set the data to write */
319 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
324 /* Issue the write command */
325 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
326 smi_cmd_write(dev, reg));
330 /* Wait for the write command to complete */
331 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
338 static int mv88e61xx_phy_wait(struct phy_device *phydev)
340 struct mv88e61xx_phy_priv *priv = phydev->priv;
345 val = mv88e61xx_reg_read(phydev, priv->global2,
346 GLOBAL2_REG_PHY_CMD);
347 if (val >= 0 && (val & SMI_BUSY) == 0)
356 static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
359 struct mv88e61xx_phy_priv *priv;
360 struct phy_device *phydev;
363 phydev = (struct phy_device *)smi_wrapper->priv;
366 /* Issue command to read */
367 res = mv88e61xx_reg_write(phydev, priv->global2,
369 smi_cmd_read(dev, reg));
371 /* Wait for data to be read */
372 res = mv88e61xx_phy_wait(phydev);
376 /* Read retrieved data */
377 return mv88e61xx_reg_read(phydev, priv->global2,
378 GLOBAL2_REG_PHY_DATA);
381 static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
382 int devad, int reg, u16 data)
384 struct mv88e61xx_phy_priv *priv;
385 struct phy_device *phydev;
388 phydev = (struct phy_device *)smi_wrapper->priv;
391 /* Set the data to write */
392 res = mv88e61xx_reg_write(phydev, priv->global2,
393 GLOBAL2_REG_PHY_DATA, data);
396 /* Issue the write command */
397 res = mv88e61xx_reg_write(phydev, priv->global2,
399 smi_cmd_write(dev, reg));
403 /* Wait for command to complete */
404 return mv88e61xx_phy_wait(phydev);
407 /* Wrapper function to make calls to phy_read_indirect simpler */
408 static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
410 return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
411 MDIO_DEVAD_NONE, reg);
414 /* Wrapper function to make calls to phy_read_indirect simpler */
415 static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
418 return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
419 MDIO_DEVAD_NONE, reg, val);
422 static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
424 struct mv88e61xx_phy_priv *priv = phydev->priv;
426 return mv88e61xx_reg_read(phydev, priv->port_reg_base + port, reg);
429 static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
432 struct mv88e61xx_phy_priv *priv = phydev->priv;
434 return mv88e61xx_reg_write(phydev, priv->port_reg_base + port,
438 static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
440 return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
443 static int mv88e61xx_get_switch_id(struct phy_device *phydev)
447 res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
453 static bool mv88e61xx_6352_family(struct phy_device *phydev)
455 struct mv88e61xx_phy_priv *priv = phydev->priv;
458 case PORT_SWITCH_ID_6172:
459 case PORT_SWITCH_ID_6176:
460 case PORT_SWITCH_ID_6240:
461 case PORT_SWITCH_ID_6352:
467 static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
471 res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
474 return res & PORT_REG_STATUS_CMODE_MASK;
477 static int mv88e61xx_parse_status(struct phy_device *phydev)
480 unsigned int mii_reg;
482 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
484 if ((mii_reg & PHY_REG_STATUS1_LINK) &&
485 !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
488 puts("Waiting for PHY realtime link");
489 while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
490 /* Timeout reached ? */
491 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
492 puts(" TIMEOUT !\n");
497 if ((i++ % 1000) == 0)
500 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
504 udelay(500000); /* another 500 ms (results in faster booting) */
506 if (mii_reg & PHY_REG_STATUS1_LINK)
512 if (mii_reg & PHY_REG_STATUS1_DUPLEX)
513 phydev->duplex = DUPLEX_FULL;
515 phydev->duplex = DUPLEX_HALF;
517 speed = mii_reg & PHY_REG_STATUS1_SPEED;
520 case PHY_REG_STATUS1_GBIT:
521 phydev->speed = SPEED_1000;
523 case PHY_REG_STATUS1_100:
524 phydev->speed = SPEED_100;
527 phydev->speed = SPEED_10;
534 static int mv88e61xx_switch_reset(struct phy_device *phydev)
536 struct mv88e61xx_phy_priv *priv = phydev->priv;
541 /* Disable all ports */
542 for (port = 0; port < priv->port_count; port++) {
543 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
546 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
547 PORT_REG_CTRL_PSTATE_WIDTH,
548 PORT_REG_CTRL_PSTATE_DISABLED);
549 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
554 /* Wait 2 ms for queues to drain */
558 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_CTRL);
561 val |= GLOBAL1_CTRL_SWRESET;
562 val = mv88e61xx_reg_write(phydev, priv->global1,
567 /* Wait up to 1 second for switch reset complete */
568 for (time = 1000; time; time--) {
569 val = mv88e61xx_reg_read(phydev, priv->global1,
571 if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
581 static int mv88e61xx_serdes_init(struct phy_device *phydev)
585 val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
589 /* Power up serdes module */
590 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
593 val &= ~(BMCR_PDOWN);
594 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
601 static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
605 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
608 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
609 PORT_REG_CTRL_PSTATE_WIDTH,
610 PORT_REG_CTRL_PSTATE_FORWARD);
611 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
618 static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
623 /* Set VID to port number plus one */
624 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
627 val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
628 PORT_REG_VLAN_ID_DEF_VID_WIDTH,
630 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
635 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
638 val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
639 PORT_REG_VLAN_MAP_TABLE_WIDTH,
641 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
648 static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
650 struct mv88e61xx_phy_priv *priv = phydev->priv;
655 val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
658 if (!(val & priv->port_stat_link_mask)) {
659 /* Temporarily force link to read port configuration */
663 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
666 val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
667 PORT_REG_PHYS_CTRL_LINK_VALUE);
668 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
673 /* Wait for status register to reflect forced link */
675 val = mv88e61xx_port_read(phydev, port,
681 if (val & priv->port_stat_link_mask)
691 if (val & priv->port_stat_dup_mask)
692 phydev->duplex = DUPLEX_FULL;
694 phydev->duplex = DUPLEX_HALF;
696 val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
697 priv->port_stat_speed_width);
699 case PORT_REG_STATUS_SPEED_1000:
700 phydev->speed = SPEED_1000;
702 case PORT_REG_STATUS_SPEED_100:
703 phydev->speed = SPEED_100;
706 phydev->speed = SPEED_10;
714 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
717 val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
718 PORT_REG_PHYS_CTRL_LINK_VALUE);
719 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
728 static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
730 struct mv88e61xx_phy_priv *priv = phydev->priv;
733 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
737 val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK |
738 PORT_REG_PHYS_CTRL_FC_VALUE |
739 PORT_REG_PHYS_CTRL_FC_FORCE);
740 val |= PORT_REG_PHYS_CTRL_FC_FORCE |
741 PORT_REG_PHYS_CTRL_DUPLEX_VALUE |
742 PORT_REG_PHYS_CTRL_DUPLEX_FORCE;
744 if (priv->id == PORT_SWITCH_ID_6071) {
745 val |= PORT_REG_PHYS_CTRL_SPD100;
747 val |= PORT_REG_PHYS_CTRL_PCS_AN_EN |
748 PORT_REG_PHYS_CTRL_PCS_AN_RST |
749 PORT_REG_PHYS_CTRL_SPD1000;
752 if (port == CONFIG_MV88E61XX_CPU_PORT)
753 val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
754 PORT_REG_PHYS_CTRL_LINK_FORCE;
756 return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
760 static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
762 struct mv88e61xx_phy_priv *priv = phydev->priv;
766 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_MON_CTRL);
769 val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
770 GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
771 CONFIG_MV88E61XX_CPU_PORT);
772 val = mv88e61xx_reg_write(phydev, priv->global1,
773 GLOBAL1_MON_CTRL, val);
777 /* Allow CPU to route to any port */
778 val = PORT_MASK(priv->port_count) & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
779 val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
783 /* Enable CPU port */
784 val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
788 val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
792 /* If CPU is connected to serdes, initialize serdes */
793 if (mv88e61xx_6352_family(phydev)) {
794 val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
797 if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
798 val == PORT_REG_STATUS_CMODE_1000BASE_X ||
799 val == PORT_REG_STATUS_CMODE_SGMII) {
800 val = mv88e61xx_serdes_init(phydev);
805 val = mv88e61xx_fixed_port_setup(phydev,
806 CONFIG_MV88E61XX_CPU_PORT);
814 static int mv88e61xx_switch_init(struct phy_device *phydev)
822 res = mv88e61xx_switch_reset(phydev);
826 res = mv88e61xx_set_cpu_port(phydev);
835 static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
839 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
842 val &= ~(BMCR_PDOWN);
843 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
850 static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
852 struct mv88e61xx_phy_priv *priv = phydev->priv;
856 * Enable energy-detect sensing on PHY, used to determine when a PHY
857 * port is physically connected
859 val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
862 val = bitfield_replace(val, priv->phy_ctrl1_en_det_shift,
863 priv->phy_ctrl1_en_det_width,
864 priv->phy_ctrl1_en_det_ctrl);
865 val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
872 static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
876 val = mv88e61xx_port_enable(phydev, phy);
880 val = mv88e61xx_port_set_vlan(phydev, phy,
881 1 << CONFIG_MV88E61XX_CPU_PORT);
889 * This function is used to pre-configure the required register
890 * offsets, so that the indirect register access to the PHY registers
891 * is possible. This is necessary to be able to read the PHY ID
892 * while driver probing or in get_phy_id(). The globalN register
893 * offsets must be initialized correctly for a detected switch,
894 * otherwise detection of the PHY ID won't work!
896 static int mv88e61xx_priv_reg_offs_pre_init(struct phy_device *phydev)
898 struct mv88e61xx_phy_priv *priv = phydev->priv;
901 * Initial 'port_reg_base' value must be an offset of existing
902 * port register, then reading the ID should succeed. First, try
903 * to read via port registers with device address 0x10 (88E6096
904 * and compatible switches).
906 priv->port_reg_base = 0x10;
907 priv->id = mv88e61xx_get_switch_id(phydev);
908 if (priv->id != 0xfff0) {
909 priv->global1 = 0x1B;
910 priv->global2 = 0x1C;
915 * Now try via port registers with device address 0x08
916 * (88E6020 and compatible switches).
918 priv->port_reg_base = 0x08;
919 priv->id = mv88e61xx_get_switch_id(phydev);
920 if (priv->id != 0xfff0) {
921 priv->global1 = 0x0F;
922 priv->global2 = 0x07;
926 debug("%s Unknown ID 0x%x\n", __func__, priv->id);
930 static int mv88e61xx_probe(struct phy_device *phydev)
932 struct mii_dev *smi_wrapper;
933 struct mv88e61xx_phy_priv *priv;
936 res = mv88e61xx_hw_reset(phydev);
940 priv = malloc(sizeof(*priv));
944 memset(priv, 0, sizeof(*priv));
947 * This device requires indirect reads/writes to the PHY registers
948 * which the generic PHY code can't handle. Make a wrapper MII device
949 * to handle reads/writes
951 smi_wrapper = mdio_alloc();
958 * Store the mdio bus in the private data, as we are going to replace
959 * the bus with the wrapper bus
961 priv->mdio_bus = phydev->bus;
964 * Store the smi bus address in private data. This lets us use the
965 * phydev addr field for device address instead, as the genphy code
968 priv->smi_addr = phydev->addr;
971 * Store the phy_device in the wrapper mii device. This lets us get it
972 * back when genphy functions call phy_read/phy_write.
974 smi_wrapper->priv = phydev;
975 strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
976 smi_wrapper->read = mv88e61xx_phy_read_indirect;
977 smi_wrapper->write = mv88e61xx_phy_write_indirect;
979 /* Replace the bus with the wrapper device */
980 phydev->bus = smi_wrapper;
984 res = mv88e61xx_priv_reg_offs_pre_init(phydev);
988 debug("%s ID 0x%x\n", __func__, priv->id);
991 case PORT_SWITCH_ID_6096:
992 case PORT_SWITCH_ID_6097:
993 case PORT_SWITCH_ID_6172:
994 case PORT_SWITCH_ID_6176:
995 case PORT_SWITCH_ID_6240:
996 case PORT_SWITCH_ID_6352:
997 priv->port_count = 11;
998 priv->port_stat_link_mask = BIT(11);
999 priv->port_stat_dup_mask = BIT(10);
1000 priv->port_stat_speed_width = 2;
1001 priv->phy_ctrl1_en_det_shift = 8;
1002 priv->phy_ctrl1_en_det_width = 2;
1003 priv->phy_ctrl1_en_det_ctrl =
1004 PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT;
1006 case PORT_SWITCH_ID_6020:
1007 case PORT_SWITCH_ID_6070:
1008 case PORT_SWITCH_ID_6071:
1009 case PORT_SWITCH_ID_6220:
1010 case PORT_SWITCH_ID_6250:
1011 priv->port_count = 7;
1012 priv->port_stat_link_mask = BIT(12);
1013 priv->port_stat_dup_mask = BIT(9);
1014 priv->port_stat_speed_width = 1;
1015 priv->phy_ctrl1_en_det_shift = 14;
1016 priv->phy_ctrl1_en_det_width = 1;
1017 priv->phy_ctrl1_en_det_ctrl =
1018 PHY_REG_CTRL1_ENERGY_DET_SENSE_PULSE;
1025 res = mdio_register(smi_wrapper);
1027 printf("Failed to register SMI bus\n");
1032 static int mv88e61xx_phy_config(struct phy_device *phydev)
1034 struct mv88e61xx_phy_priv *priv = phydev->priv;
1039 res = mv88e61xx_switch_init(phydev);
1043 for (i = 0; i < priv->port_count; i++) {
1044 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
1047 res = mv88e61xx_phy_enable(phydev, i);
1049 printf("Error enabling PHY %i\n", i);
1052 res = mv88e61xx_phy_setup(phydev, i);
1054 printf("Error setting up PHY %i\n", i);
1057 res = mv88e61xx_phy_config_port(phydev, i);
1059 printf("Error configuring PHY %i\n", i);
1063 res = phy_reset(phydev);
1065 printf("Error resetting PHY %i\n", i);
1068 res = genphy_config_aneg(phydev);
1070 printf("Error setting PHY %i autoneg\n", i);
1074 /* Return success if any PHY succeeds */
1076 } else if ((1 << i) & CONFIG_MV88E61XX_FIXED_PORTS) {
1077 res = mv88e61xx_fixed_port_setup(phydev, i);
1079 printf("Error configuring port %i\n", i);
1088 static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
1092 val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
1097 * After reset, the energy detect signal remains high for a few seconds
1098 * regardless of whether a cable is connected. This function will
1099 * return false positives during this time.
1101 return (val & PHY_REG_STATUS1_ENERGY) == 0;
1104 static int mv88e61xx_phy_startup(struct phy_device *phydev)
1106 struct mv88e61xx_phy_priv *priv = phydev->priv;
1110 int speed = phydev->speed;
1111 int duplex = phydev->duplex;
1113 for (i = 0; i < priv->port_count; i++) {
1114 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
1116 if (!mv88e61xx_phy_is_connected(phydev))
1118 res = genphy_update_link(phydev);
1121 res = mv88e61xx_parse_status(phydev);
1124 link = (link || phydev->link);
1127 phydev->link = link;
1129 /* Restore CPU interface speed and duplex after it was changed for
1131 phydev->speed = speed;
1132 phydev->duplex = duplex;
1137 static struct phy_driver mv88e61xx_driver = {
1138 .name = "Marvell MV88E61xx",
1141 .features = PHY_GBIT_FEATURES,
1142 .probe = mv88e61xx_probe,
1143 .config = mv88e61xx_phy_config,
1144 .startup = mv88e61xx_phy_startup,
1145 .shutdown = &genphy_shutdown,
1148 static struct phy_driver mv88e609x_driver = {
1149 .name = "Marvell MV88E609x",
1152 .features = PHY_GBIT_FEATURES,
1153 .probe = mv88e61xx_probe,
1154 .config = mv88e61xx_phy_config,
1155 .startup = mv88e61xx_phy_startup,
1156 .shutdown = &genphy_shutdown,
1159 static struct phy_driver mv88e6071_driver = {
1160 .name = "Marvell MV88E6071",
1163 .features = PHY_BASIC_FEATURES | SUPPORTED_MII,
1164 .probe = mv88e61xx_probe,
1165 .config = mv88e61xx_phy_config,
1166 .startup = mv88e61xx_phy_startup,
1167 .shutdown = &genphy_shutdown,
1170 int phy_mv88e61xx_init(void)
1172 phy_register(&mv88e61xx_driver);
1173 phy_register(&mv88e609x_driver);
1174 phy_register(&mv88e6071_driver);
1180 * Overload weak get_phy_id definition since we need non-standard functions
1181 * to read PHY registers
1183 int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
1185 struct phy_device temp_phy;
1186 struct mv88e61xx_phy_priv temp_priv;
1187 struct mii_dev temp_mii;
1191 * Buid temporary data structures that the chip reading code needs to
1194 temp_priv.mdio_bus = bus;
1195 temp_priv.smi_addr = smi_addr;
1196 temp_phy.priv = &temp_priv;
1197 temp_mii.priv = &temp_phy;
1200 * get_phy_id() can be called by framework before mv88e61xx driver
1201 * probing, in this case the global register offsets are not
1202 * initialized yet. Do this initialization here before indirect
1203 * PHY register access.
1205 val = mv88e61xx_priv_reg_offs_pre_init(&temp_phy);
1209 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
1213 *phy_id = val << 16;
1215 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
1219 *phy_id |= (val & 0xffff);