1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009 Industrie Dial Face S.p.A.
4 * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
7 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
11 * This provides a bit-banged interface to the ethernet MII management
17 #include <ppc_asm.tmpl>
20 #define BB_MII_RELOCATE(v,off) (v += (v?off:0))
22 DECLARE_GLOBAL_DATA_PTR;
24 #ifndef CONFIG_BITBANGMII_MULTI
27 * If CONFIG_BITBANGMII_MULTI is not defined we use a
28 * compatibility layer with the previous miiphybb implementation
29 * based on macros usage.
32 static int bb_mii_init_wrap(struct bb_miiphy_bus *bus)
40 static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus)
49 static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus)
58 static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v)
67 static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v)
76 static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v)
85 static int bb_delay_wrap(struct bb_miiphy_bus *bus)
91 struct bb_miiphy_bus bb_miiphy_buses[] = {
93 .name = BB_MII_DEVNAME,
94 .init = bb_mii_init_wrap,
95 .mdio_active = bb_mdio_active_wrap,
96 .mdio_tristate = bb_mdio_tristate_wrap,
97 .set_mdio = bb_set_mdio_wrap,
98 .get_mdio = bb_get_mdio_wrap,
99 .set_mdc = bb_set_mdc_wrap,
100 .delay = bb_delay_wrap,
104 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
105 sizeof(bb_miiphy_buses[0]);
108 void bb_miiphy_init(void)
112 for (i = 0; i < bb_miiphy_buses_num; i++) {
113 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
114 /* Relocate the hook pointers*/
115 BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off);
116 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off);
117 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off);
118 BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off);
119 BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off);
120 BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off);
121 BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off);
123 if (bb_miiphy_buses[i].init != NULL) {
124 bb_miiphy_buses[i].init(&bb_miiphy_buses[i]);
129 static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
131 #ifdef CONFIG_BITBANGMII_MULTI
134 /* Search the correct bus */
135 for (i = 0; i < bb_miiphy_buses_num; i++) {
136 if (!strcmp(bb_miiphy_buses[i].name, devname)) {
137 return &bb_miiphy_buses[i];
142 /* We have just one bitbanging bus */
143 return &bb_miiphy_buses[0];
147 /*****************************************************************************
149 * Utility to send the preamble, address, and register (common to read
152 static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
153 unsigned char addr, unsigned char reg)
158 * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
159 * The IEEE spec says this is a PHY optional requirement. The AMD
160 * 79C874 requires one after power up and one after a MII communications
161 * error. This means that we are doing more preambles than we need,
162 * but it is safer and will be much more robust.
165 bus->mdio_active(bus);
166 bus->set_mdio(bus, 1);
167 for (j = 0; j < 32; j++) {
168 bus->set_mdc(bus, 0);
170 bus->set_mdc(bus, 1);
174 /* send the start bit (01) and the read opcode (10) or write (10) */
175 bus->set_mdc(bus, 0);
176 bus->set_mdio(bus, 0);
178 bus->set_mdc(bus, 1);
180 bus->set_mdc(bus, 0);
181 bus->set_mdio(bus, 1);
183 bus->set_mdc(bus, 1);
185 bus->set_mdc(bus, 0);
186 bus->set_mdio(bus, read);
188 bus->set_mdc(bus, 1);
190 bus->set_mdc(bus, 0);
191 bus->set_mdio(bus, !read);
193 bus->set_mdc(bus, 1);
196 /* send the PHY address */
197 for (j = 0; j < 5; j++) {
198 bus->set_mdc(bus, 0);
199 if ((addr & 0x10) == 0) {
200 bus->set_mdio(bus, 0);
202 bus->set_mdio(bus, 1);
205 bus->set_mdc(bus, 1);
210 /* send the register address */
211 for (j = 0; j < 5; j++) {
212 bus->set_mdc(bus, 0);
213 if ((reg & 0x10) == 0) {
214 bus->set_mdio(bus, 0);
216 bus->set_mdio(bus, 1);
219 bus->set_mdc(bus, 1);
225 /*****************************************************************************
227 * Read a MII PHY register.
232 int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg)
234 unsigned short rdreg; /* register working value */
237 struct bb_miiphy_bus *bus;
239 bus = bb_miiphy_getbus(miidev->name);
244 miiphy_pre (bus, 1, addr, reg);
246 /* tri-state our MDIO I/O pin so we can read */
247 bus->set_mdc(bus, 0);
248 bus->mdio_tristate(bus);
250 bus->set_mdc(bus, 1);
253 /* check the turnaround bit: the PHY should be driving it to zero */
254 bus->get_mdio(bus, &v);
256 /* puts ("PHY didn't drive TA low\n"); */
257 for (j = 0; j < 32; j++) {
258 bus->set_mdc(bus, 0);
260 bus->set_mdc(bus, 1);
263 /* There is no PHY, return */
267 bus->set_mdc(bus, 0);
270 /* read 16 bits of register data, MSB first */
272 for (j = 0; j < 16; j++) {
273 bus->set_mdc(bus, 1);
276 bus->get_mdio(bus, &v);
278 bus->set_mdc(bus, 0);
282 bus->set_mdc(bus, 1);
284 bus->set_mdc(bus, 0);
286 bus->set_mdc(bus, 1);
290 printf("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, rdreg);
297 /*****************************************************************************
299 * Write a MII PHY register.
304 int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg,
307 struct bb_miiphy_bus *bus;
310 bus = bb_miiphy_getbus(miidev->name);
316 miiphy_pre (bus, 0, addr, reg);
318 /* send the turnaround (10) */
319 bus->set_mdc(bus, 0);
320 bus->set_mdio(bus, 1);
322 bus->set_mdc(bus, 1);
324 bus->set_mdc(bus, 0);
325 bus->set_mdio(bus, 0);
327 bus->set_mdc(bus, 1);
330 /* write 16 bits of register data, MSB first */
331 for (j = 0; j < 16; j++) {
332 bus->set_mdc(bus, 0);
333 if ((value & 0x00008000) == 0) {
334 bus->set_mdio(bus, 0);
336 bus->set_mdio(bus, 1);
339 bus->set_mdc(bus, 1);
345 * Tri-state the MDIO line.
347 bus->mdio_tristate(bus);
348 bus->set_mdc(bus, 0);
350 bus->set_mdc(bus, 1);