1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * (C) 2012 NetModule AG, David Andrey, added KSZ9031
8 * (C) Copyright 2017 Adaptrum, Inc.
9 * Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
18 * KSZ9021 - KSZ9031 common
21 #define MII_KSZ90xx_PHY_CTL 0x1f
22 #define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
23 #define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
24 #define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
25 #define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
27 /* KSZ9021 PHY Registers */
28 #define MII_KSZ9021_EXTENDED_CTRL 0x0b
29 #define MII_KSZ9021_EXTENDED_DATAW 0x0c
30 #define MII_KSZ9021_EXTENDED_DATAR 0x0d
32 #define CTRL1000_PREFER_MASTER (1 << 10)
33 #define CTRL1000_CONFIG_MASTER (1 << 11)
34 #define CTRL1000_MANUAL_CONFIG (1 << 12)
36 #define KSZ9021_PS_TO_REG 120
38 /* KSZ9031 PHY Registers */
39 #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
40 #define MII_KSZ9031_MMD_REG_DATA 0x0e
42 #define KSZ9031_PS_TO_REG 60
44 static int ksz90xx_startup(struct phy_device *phydev)
49 ret = genphy_update_link(phydev);
53 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
55 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
56 phydev->duplex = DUPLEX_FULL;
58 phydev->duplex = DUPLEX_HALF;
60 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
61 phydev->speed = SPEED_1000;
62 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
63 phydev->speed = SPEED_100;
64 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
65 phydev->speed = SPEED_10;
69 /* Common OF config bits for KSZ9021 and KSZ9031 */
71 struct ksz90x1_reg_field {
73 const u8 size; /* Size of the bitfield, in bits */
74 const u8 off; /* Offset from bit 0 */
75 const u8 dflt; /* Default value */
78 struct ksz90x1_ofcfg {
81 const struct ksz90x1_reg_field *grp;
85 static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
86 { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
87 { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
90 static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
91 { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
92 { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
95 static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
96 { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
97 { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
100 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
101 { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
104 static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
105 { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
108 static int ksz90x1_of_config_group(struct phy_device *phydev,
109 struct ksz90x1_ofcfg *ofcfg,
112 struct udevice *dev = phydev->dev;
113 struct phy_driver *drv = phydev->drv;
115 int i, changed = 0, offset, max;
119 if (!drv || !drv->writeext)
122 /* Look for a PHY node under the Ethernet node */
123 node = dev_read_subnode(dev, "ethernet-phy");
124 if (!ofnode_valid(node)) {
125 /* No node found, look in the Ethernet node */
126 node = dev_ofnode(dev);
129 for (i = 0; i < ofcfg->grpsz; i++) {
130 val[i] = ofnode_read_u32_default(node, ofcfg->grp[i].name, ~0);
131 offset = ofcfg->grp[i].off;
133 /* Default register value for KSZ9021 */
134 regval |= ofcfg->grp[i].dflt << offset;
136 changed = 1; /* Value was changed in OF */
137 /* Calculate the register value and fix corner cases */
138 max = (1 << ofcfg->grp[i].size) - 1;
139 if (val[i] > ps_to_regval * max) {
140 regval |= max << offset;
142 regval |= (val[i] / ps_to_regval) << offset;
150 return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
153 static int ksz9021_of_config(struct phy_device *phydev)
155 struct ksz90x1_ofcfg ofcfg[] = {
156 { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
157 { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
158 { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
162 for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
163 ret = ksz90x1_of_config_group(phydev, &ofcfg[i],
172 static int ksz9031_of_config(struct phy_device *phydev)
174 struct ksz90x1_ofcfg ofcfg[] = {
175 { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
176 { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
177 { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
178 { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
182 for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
183 ret = ksz90x1_of_config_group(phydev, &ofcfg[i],
192 static int ksz9031_center_flp_timing(struct phy_device *phydev)
194 struct phy_driver *drv = phydev->drv;
197 if (!drv || !drv->writeext)
200 ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
204 ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
208 #else /* !CONFIG_DM_ETH */
209 static int ksz9021_of_config(struct phy_device *phydev)
214 static int ksz9031_of_config(struct phy_device *phydev)
219 static int ksz9031_center_flp_timing(struct phy_device *phydev)
228 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
230 /* extended registers */
231 phy_write(phydev, MDIO_DEVAD_NONE,
232 MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
233 return phy_write(phydev, MDIO_DEVAD_NONE,
234 MII_KSZ9021_EXTENDED_DATAW, val);
237 int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
239 /* extended registers */
240 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
241 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
245 static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
248 return ksz9021_phy_extended_read(phydev, regnum);
251 static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
252 int devaddr, int regnum, u16 val)
254 return ksz9021_phy_extended_write(phydev, regnum, val);
257 static int ksz9021_config(struct phy_device *phydev)
259 unsigned ctrl1000 = 0;
260 const unsigned master = CTRL1000_PREFER_MASTER |
261 CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
262 unsigned features = phydev->drv->features;
265 ret = ksz9021_of_config(phydev);
269 if (env_get("disable_giga"))
270 features &= ~(SUPPORTED_1000baseT_Half |
271 SUPPORTED_1000baseT_Full);
272 /* force master mode for 1000BaseT due to chip errata */
273 if (features & SUPPORTED_1000baseT_Half)
274 ctrl1000 |= ADVERTISE_1000HALF | master;
275 if (features & SUPPORTED_1000baseT_Full)
276 ctrl1000 |= ADVERTISE_1000FULL | master;
277 phydev->advertising = features;
278 phydev->supported = features;
279 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
280 genphy_config_aneg(phydev);
281 genphy_restart_aneg(phydev);
285 static struct phy_driver ksz9021_driver = {
286 .name = "Micrel ksz9021",
289 .features = PHY_GBIT_FEATURES,
290 .config = &ksz9021_config,
291 .startup = &ksz90xx_startup,
292 .shutdown = &genphy_shutdown,
293 .writeext = &ksz9021_phy_extwrite,
294 .readext = &ksz9021_phy_extread,
300 int ksz9031_phy_extended_write(struct phy_device *phydev,
301 int devaddr, int regnum, u16 mode, u16 val)
303 /*select register addr for mmd*/
304 phy_write(phydev, MDIO_DEVAD_NONE,
305 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
306 /*select register for mmd*/
307 phy_write(phydev, MDIO_DEVAD_NONE,
308 MII_KSZ9031_MMD_REG_DATA, regnum);
310 phy_write(phydev, MDIO_DEVAD_NONE,
311 MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
313 return phy_write(phydev, MDIO_DEVAD_NONE,
314 MII_KSZ9031_MMD_REG_DATA, val);
317 int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
318 int regnum, u16 mode)
320 phy_write(phydev, MDIO_DEVAD_NONE,
321 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
322 phy_write(phydev, MDIO_DEVAD_NONE,
323 MII_KSZ9031_MMD_REG_DATA, regnum);
324 phy_write(phydev, MDIO_DEVAD_NONE,
325 MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
326 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
329 static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
332 return ksz9031_phy_extended_read(phydev, devaddr, regnum,
333 MII_KSZ9031_MOD_DATA_NO_POST_INC);
336 static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
337 int devaddr, int regnum, u16 val)
339 return ksz9031_phy_extended_write(phydev, devaddr, regnum,
340 MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
343 static int ksz9031_config(struct phy_device *phydev)
347 ret = ksz9031_of_config(phydev);
350 ret = ksz9031_center_flp_timing(phydev);
354 /* add an option to disable the gigabit feature of this PHY */
355 if (env_get("disable_giga")) {
359 /* disable speed 1000 in features supported by the PHY */
360 features = phydev->drv->features;
361 features &= ~(SUPPORTED_1000baseT_Half |
362 SUPPORTED_1000baseT_Full);
363 phydev->advertising = phydev->supported = features;
365 /* disable speed 1000 in Basic Control Register */
366 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
368 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
370 /* disable speed 1000 in 1000Base-T Control Register */
371 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
374 genphy_config_aneg(phydev);
375 genphy_restart_aneg(phydev);
380 return genphy_config(phydev);
383 static struct phy_driver ksz9031_driver = {
384 .name = "Micrel ksz9031",
387 .features = PHY_GBIT_FEATURES,
388 .config = &ksz9031_config,
389 .startup = &ksz90xx_startup,
390 .shutdown = &genphy_shutdown,
391 .writeext = &ksz9031_phy_extwrite,
392 .readext = &ksz9031_phy_extread,
395 int phy_micrel_ksz90x1_init(void)
397 phy_register(&ksz9021_driver);
398 phy_register(&ksz9031_driver);