1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * (C) 2012 NetModule AG, David Andrey, added KSZ9031
8 * (C) Copyright 2017 Adaptrum, Inc.
9 * Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
19 * KSZ9021 - KSZ9031 common
22 #define MII_KSZ90xx_PHY_CTL 0x1f
23 #define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
24 #define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
25 #define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
26 #define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
28 /* KSZ9021 PHY Registers */
29 #define MII_KSZ9021_EXTENDED_CTRL 0x0b
30 #define MII_KSZ9021_EXTENDED_DATAW 0x0c
31 #define MII_KSZ9021_EXTENDED_DATAR 0x0d
33 #define CTRL1000_PREFER_MASTER (1 << 10)
34 #define CTRL1000_CONFIG_MASTER (1 << 11)
35 #define CTRL1000_MANUAL_CONFIG (1 << 12)
37 #define KSZ9021_PS_TO_REG 120
39 /* KSZ9031 PHY Registers */
40 #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
41 #define MII_KSZ9031_MMD_REG_DATA 0x0e
43 #define KSZ9031_PS_TO_REG 60
45 static int ksz90xx_startup(struct phy_device *phydev)
50 ret = genphy_update_link(phydev);
54 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
56 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
57 phydev->duplex = DUPLEX_FULL;
59 phydev->duplex = DUPLEX_HALF;
61 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
62 phydev->speed = SPEED_1000;
63 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
64 phydev->speed = SPEED_100;
65 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
66 phydev->speed = SPEED_10;
70 /* Common OF config bits for KSZ9021 and KSZ9031 */
72 struct ksz90x1_reg_field {
74 const u8 size; /* Size of the bitfield, in bits */
75 const u8 off; /* Offset from bit 0 */
76 const u8 dflt; /* Default value */
79 struct ksz90x1_ofcfg {
82 const struct ksz90x1_reg_field *grp;
86 static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
87 { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
88 { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
91 static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
92 { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
93 { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
96 static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
97 { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
98 { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
101 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
102 { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
105 static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
106 { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
109 static int ksz90x1_of_config_group(struct phy_device *phydev,
110 struct ksz90x1_ofcfg *ofcfg,
113 struct udevice *dev = phydev->dev;
114 struct phy_driver *drv = phydev->drv;
116 int i, changed = 0, offset, max;
120 if (!drv || !drv->writeext)
123 /* Look for a PHY node under the Ethernet node */
124 node = dev_read_subnode(dev, "ethernet-phy");
125 if (!ofnode_valid(node)) {
126 /* No node found, look in the Ethernet node */
127 node = dev_ofnode(dev);
130 for (i = 0; i < ofcfg->grpsz; i++) {
131 val[i] = ofnode_read_u32_default(node, ofcfg->grp[i].name, ~0);
132 offset = ofcfg->grp[i].off;
134 /* Default register value for KSZ9021 */
135 regval |= ofcfg->grp[i].dflt << offset;
137 changed = 1; /* Value was changed in OF */
138 /* Calculate the register value and fix corner cases */
139 max = (1 << ofcfg->grp[i].size) - 1;
140 if (val[i] > ps_to_regval * max) {
141 regval |= max << offset;
143 regval |= (val[i] / ps_to_regval) << offset;
151 return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
154 static int ksz9021_of_config(struct phy_device *phydev)
156 struct ksz90x1_ofcfg ofcfg[] = {
157 { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
158 { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
159 { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
163 for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
164 ret = ksz90x1_of_config_group(phydev, &ofcfg[i],
173 static int ksz9031_of_config(struct phy_device *phydev)
175 struct ksz90x1_ofcfg ofcfg[] = {
176 { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
177 { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
178 { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
179 { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
183 for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
184 ret = ksz90x1_of_config_group(phydev, &ofcfg[i],
193 static int ksz9031_center_flp_timing(struct phy_device *phydev)
195 struct phy_driver *drv = phydev->drv;
198 if (!drv || !drv->writeext)
201 ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
205 ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
209 #else /* !CONFIG_DM_ETH */
210 static int ksz9021_of_config(struct phy_device *phydev)
215 static int ksz9031_of_config(struct phy_device *phydev)
220 static int ksz9031_center_flp_timing(struct phy_device *phydev)
229 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
231 /* extended registers */
232 phy_write(phydev, MDIO_DEVAD_NONE,
233 MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
234 return phy_write(phydev, MDIO_DEVAD_NONE,
235 MII_KSZ9021_EXTENDED_DATAW, val);
238 int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
240 /* extended registers */
241 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
242 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
246 static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
249 return ksz9021_phy_extended_read(phydev, regnum);
252 static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
253 int devaddr, int regnum, u16 val)
255 return ksz9021_phy_extended_write(phydev, regnum, val);
258 static int ksz9021_config(struct phy_device *phydev)
260 unsigned ctrl1000 = 0;
261 const unsigned master = CTRL1000_PREFER_MASTER |
262 CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
263 unsigned features = phydev->drv->features;
266 ret = ksz9021_of_config(phydev);
270 if (env_get("disable_giga"))
271 features &= ~(SUPPORTED_1000baseT_Half |
272 SUPPORTED_1000baseT_Full);
273 /* force master mode for 1000BaseT due to chip errata */
274 if (features & SUPPORTED_1000baseT_Half)
275 ctrl1000 |= ADVERTISE_1000HALF | master;
276 if (features & SUPPORTED_1000baseT_Full)
277 ctrl1000 |= ADVERTISE_1000FULL | master;
278 phydev->advertising = features;
279 phydev->supported = features;
280 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
281 genphy_config_aneg(phydev);
282 genphy_restart_aneg(phydev);
286 static struct phy_driver ksz9021_driver = {
287 .name = "Micrel ksz9021",
290 .features = PHY_GBIT_FEATURES,
291 .config = &ksz9021_config,
292 .startup = &ksz90xx_startup,
293 .shutdown = &genphy_shutdown,
294 .writeext = &ksz9021_phy_extwrite,
295 .readext = &ksz9021_phy_extread,
301 int ksz9031_phy_extended_write(struct phy_device *phydev,
302 int devaddr, int regnum, u16 mode, u16 val)
304 /*select register addr for mmd*/
305 phy_write(phydev, MDIO_DEVAD_NONE,
306 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
307 /*select register for mmd*/
308 phy_write(phydev, MDIO_DEVAD_NONE,
309 MII_KSZ9031_MMD_REG_DATA, regnum);
311 phy_write(phydev, MDIO_DEVAD_NONE,
312 MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
314 return phy_write(phydev, MDIO_DEVAD_NONE,
315 MII_KSZ9031_MMD_REG_DATA, val);
318 int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
319 int regnum, u16 mode)
321 phy_write(phydev, MDIO_DEVAD_NONE,
322 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
323 phy_write(phydev, MDIO_DEVAD_NONE,
324 MII_KSZ9031_MMD_REG_DATA, regnum);
325 phy_write(phydev, MDIO_DEVAD_NONE,
326 MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
327 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
330 static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
333 return ksz9031_phy_extended_read(phydev, devaddr, regnum,
334 MII_KSZ9031_MOD_DATA_NO_POST_INC);
337 static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
338 int devaddr, int regnum, u16 val)
340 return ksz9031_phy_extended_write(phydev, devaddr, regnum,
341 MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
344 static int ksz9031_config(struct phy_device *phydev)
348 ret = ksz9031_of_config(phydev);
351 ret = ksz9031_center_flp_timing(phydev);
355 /* add an option to disable the gigabit feature of this PHY */
356 if (env_get("disable_giga")) {
360 /* disable speed 1000 in features supported by the PHY */
361 features = phydev->drv->features;
362 features &= ~(SUPPORTED_1000baseT_Half |
363 SUPPORTED_1000baseT_Full);
364 phydev->advertising = phydev->supported = features;
366 /* disable speed 1000 in Basic Control Register */
367 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
369 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
371 /* disable speed 1000 in 1000Base-T Control Register */
372 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
375 genphy_config_aneg(phydev);
376 genphy_restart_aneg(phydev);
381 return genphy_config(phydev);
384 static struct phy_driver ksz9031_driver = {
385 .name = "Micrel ksz9031",
388 .features = PHY_GBIT_FEATURES,
389 .config = &ksz9031_config,
390 .startup = &ksz90xx_startup,
391 .shutdown = &genphy_shutdown,
392 .writeext = &ksz9031_phy_extwrite,
393 .readext = &ksz9031_phy_extread,
396 int phy_micrel_ksz90x1_init(void)
398 phy_register(&ksz9021_driver);
399 phy_register(&ksz9031_driver);