4 * SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * (C) 2012 NetModule AG, David Andrey, added KSZ9031
18 DECLARE_GLOBAL_DATA_PTR;
20 static struct phy_driver KSZ804_driver = {
21 .name = "Micrel KSZ804",
24 .features = PHY_BASIC_FEATURES,
25 .config = &genphy_config,
26 .startup = &genphy_startup,
27 .shutdown = &genphy_shutdown,
30 #define MII_KSZPHY_OMSO 0x16
31 #define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
33 static int ksz_genconfig_bcastoff(struct phy_device *phydev)
37 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO);
41 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO,
42 ret | KSZPHY_OMSO_B_CAST_OFF);
46 return genphy_config(phydev);
49 static struct phy_driver KSZ8031_driver = {
50 .name = "Micrel KSZ8021/KSZ8031",
53 .features = PHY_BASIC_FEATURES,
54 .config = &ksz_genconfig_bcastoff,
55 .startup = &genphy_startup,
56 .shutdown = &genphy_shutdown,
62 #define MII_KSZ8051_PHY_OMSO 0x16
63 #define MII_KSZ8051_PHY_OMSO_NAND_TREE_ON (1 << 5)
65 static int ksz8051_config(struct phy_device *phydev)
69 /* Disable NAND-tree */
70 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO);
71 val &= ~MII_KSZ8051_PHY_OMSO_NAND_TREE_ON;
72 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val);
74 return genphy_config(phydev);
77 static struct phy_driver KSZ8051_driver = {
78 .name = "Micrel KSZ8051",
81 .features = PHY_BASIC_FEATURES,
82 .config = &ksz8051_config,
83 .startup = &genphy_startup,
84 .shutdown = &genphy_shutdown,
87 static struct phy_driver KSZ8081_driver = {
88 .name = "Micrel KSZ8081",
91 .features = PHY_BASIC_FEATURES,
92 .config = &ksz_genconfig_bcastoff,
93 .startup = &genphy_startup,
94 .shutdown = &genphy_shutdown,
101 static unsigned short smireg_to_phy(unsigned short reg)
103 return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5);
106 static unsigned short smireg_to_reg(unsigned short reg)
111 static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val)
113 phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE,
114 smireg_to_reg(smireg), val);
118 static int ksz8895_read_smireg(struct phy_device *phydev, int smireg)
120 return phydev->bus->read(phydev->bus, smireg_to_phy(smireg),
121 MDIO_DEVAD_NONE, smireg_to_reg(smireg));
125 int ksz8895_config(struct phy_device *phydev)
127 /* we are connected directly to the switch without
128 * dedicated PHY. SCONF1 == 001 */
130 phydev->duplex = DUPLEX_FULL;
131 phydev->speed = SPEED_100;
133 /* Force the switch to start */
134 ksz8895_write_smireg(phydev, 1, 1);
139 static int ksz8895_startup(struct phy_device *phydev)
144 static struct phy_driver ksz8895_driver = {
145 .name = "Micrel KSZ8895/KSZ8864",
148 .features = PHY_BASIC_FEATURES,
149 .config = &ksz8895_config,
150 .startup = &ksz8895_startup,
151 .shutdown = &genphy_shutdown,
154 #ifndef CONFIG_PHY_MICREL_KSZ9021
156 * I can't believe Micrel used the exact same part number
157 * for the KSZ9021. Shame Micrel, Shame!
159 static struct phy_driver KS8721_driver = {
160 .name = "Micrel KS8721BL",
163 .features = PHY_BASIC_FEATURES,
164 .config = &genphy_config,
165 .startup = &genphy_startup,
166 .shutdown = &genphy_shutdown,
172 * KSZ9021 - KSZ9031 common
175 #define MII_KSZ90xx_PHY_CTL 0x1f
176 #define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
177 #define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
178 #define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
179 #define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
181 static int ksz90xx_startup(struct phy_device *phydev)
184 genphy_update_link(phydev);
185 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
187 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
188 phydev->duplex = DUPLEX_FULL;
190 phydev->duplex = DUPLEX_HALF;
192 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
193 phydev->speed = SPEED_1000;
194 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
195 phydev->speed = SPEED_100;
196 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
197 phydev->speed = SPEED_10;
201 /* Common OF config bits for KSZ9021 and KSZ9031 */
202 #if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031)
204 struct ksz90x1_reg_field {
206 const u8 size; /* Size of the bitfield, in bits */
207 const u8 off; /* Offset from bit 0 */
208 const u8 dflt; /* Default value */
211 struct ksz90x1_ofcfg {
214 const struct ksz90x1_reg_field *grp;
218 static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
219 { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
220 { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
223 static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
224 { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
225 { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
228 static int ksz90x1_of_config_group(struct phy_device *phydev,
229 struct ksz90x1_ofcfg *ofcfg)
231 struct udevice *dev = phydev->dev;
232 struct phy_driver *drv = phydev->drv;
233 const int ps_to_regval = 60;
235 int i, changed = 0, offset, max;
238 if (!drv || !drv->writeext)
241 for (i = 0; i < ofcfg->grpsz; i++) {
242 val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
243 ofcfg->grp[i].name, -1);
244 offset = ofcfg->grp[i].off;
246 /* Default register value for KSZ9021 */
247 regval |= ofcfg->grp[i].dflt << offset;
249 changed = 1; /* Value was changed in OF */
250 /* Calculate the register value and fix corner cases */
251 if (val[i] > ps_to_regval * 0xf) {
252 max = (1 << ofcfg->grp[i].size) - 1;
253 regval |= max << offset;
255 regval |= (val[i] / ps_to_regval) << offset;
263 return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
268 #ifdef CONFIG_PHY_MICREL_KSZ9021
274 #define MII_KSZ9021_EXTENDED_CTRL 0x0b
275 #define MII_KSZ9021_EXTENDED_DATAW 0x0c
276 #define MII_KSZ9021_EXTENDED_DATAR 0x0d
278 #define CTRL1000_PREFER_MASTER (1 << 10)
279 #define CTRL1000_CONFIG_MASTER (1 << 11)
280 #define CTRL1000_MANUAL_CONFIG (1 << 12)
283 static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
284 { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
285 { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
288 static int ksz9021_of_config(struct phy_device *phydev)
290 struct ksz90x1_ofcfg ofcfg[] = {
291 { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
292 { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
293 { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
297 for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
298 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
305 static int ksz9021_of_config(struct phy_device *phydev)
311 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
313 /* extended registers */
314 phy_write(phydev, MDIO_DEVAD_NONE,
315 MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
316 return phy_write(phydev, MDIO_DEVAD_NONE,
317 MII_KSZ9021_EXTENDED_DATAW, val);
320 int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
322 /* extended registers */
323 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
324 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
328 static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
331 return ksz9021_phy_extended_read(phydev, regnum);
334 static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
335 int devaddr, int regnum, u16 val)
337 return ksz9021_phy_extended_write(phydev, regnum, val);
341 static int ksz9021_config(struct phy_device *phydev)
343 unsigned ctrl1000 = 0;
344 const unsigned master = CTRL1000_PREFER_MASTER |
345 CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
346 unsigned features = phydev->drv->features;
349 ret = ksz9021_of_config(phydev);
353 if (getenv("disable_giga"))
354 features &= ~(SUPPORTED_1000baseT_Half |
355 SUPPORTED_1000baseT_Full);
356 /* force master mode for 1000BaseT due to chip errata */
357 if (features & SUPPORTED_1000baseT_Half)
358 ctrl1000 |= ADVERTISE_1000HALF | master;
359 if (features & SUPPORTED_1000baseT_Full)
360 ctrl1000 |= ADVERTISE_1000FULL | master;
361 phydev->advertising = phydev->supported = features;
362 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
363 genphy_config_aneg(phydev);
364 genphy_restart_aneg(phydev);
368 static struct phy_driver ksz9021_driver = {
369 .name = "Micrel ksz9021",
372 .features = PHY_GBIT_FEATURES,
373 .config = &ksz9021_config,
374 .startup = &ksz90xx_startup,
375 .shutdown = &genphy_shutdown,
376 .writeext = &ksz9021_phy_extwrite,
377 .readext = &ksz9021_phy_extread,
385 #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
386 #define MII_KSZ9031_MMD_REG_DATA 0x0e
389 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
390 { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } };
391 static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
392 { { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } };
394 static int ksz9031_of_config(struct phy_device *phydev)
396 struct ksz90x1_ofcfg ofcfg[] = {
397 { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
398 { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
399 { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
400 { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
404 for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
405 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
412 static int ksz9031_of_config(struct phy_device *phydev)
418 /* Accessors to extended registers*/
419 int ksz9031_phy_extended_write(struct phy_device *phydev,
420 int devaddr, int regnum, u16 mode, u16 val)
422 /*select register addr for mmd*/
423 phy_write(phydev, MDIO_DEVAD_NONE,
424 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
425 /*select register for mmd*/
426 phy_write(phydev, MDIO_DEVAD_NONE,
427 MII_KSZ9031_MMD_REG_DATA, regnum);
429 phy_write(phydev, MDIO_DEVAD_NONE,
430 MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
432 return phy_write(phydev, MDIO_DEVAD_NONE,
433 MII_KSZ9031_MMD_REG_DATA, val);
436 int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
437 int regnum, u16 mode)
439 phy_write(phydev, MDIO_DEVAD_NONE,
440 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
441 phy_write(phydev, MDIO_DEVAD_NONE,
442 MII_KSZ9031_MMD_REG_DATA, regnum);
443 phy_write(phydev, MDIO_DEVAD_NONE,
444 MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
445 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
448 static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
451 return ksz9031_phy_extended_read(phydev, devaddr, regnum,
452 MII_KSZ9031_MOD_DATA_NO_POST_INC);
455 static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
456 int devaddr, int regnum, u16 val)
458 return ksz9031_phy_extended_write(phydev, devaddr, regnum,
459 MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
462 static int ksz9031_config(struct phy_device *phydev)
465 ret = ksz9031_of_config(phydev);
468 return genphy_config(phydev);
471 static struct phy_driver ksz9031_driver = {
472 .name = "Micrel ksz9031",
475 .features = PHY_GBIT_FEATURES,
476 .config = &ksz9031_config,
477 .startup = &ksz90xx_startup,
478 .shutdown = &genphy_shutdown,
479 .writeext = &ksz9031_phy_extwrite,
480 .readext = &ksz9031_phy_extread,
483 int phy_micrel_init(void)
485 phy_register(&KSZ804_driver);
486 phy_register(&KSZ8031_driver);
487 phy_register(&KSZ8051_driver);
488 phy_register(&KSZ8081_driver);
489 #ifdef CONFIG_PHY_MICREL_KSZ9021
490 phy_register(&ksz9021_driver);
492 phy_register(&KS8721_driver);
494 phy_register(&ksz9031_driver);
495 phy_register(&ksz8895_driver);