2 * Meson GXL Internal PHY Driver
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 * Copyright (C) 2016 BayLibre, SAS. All rights reserved.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/bitops.h>
16 /* This function is provided to cope with the possible failures of this phy
17 * during aneg process. When aneg fails, the PHY reports that aneg is done
18 * but the value found in MII_LPA is wrong:
19 * - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
20 * the link partner (LP) supports aneg but the LP never acked our base
21 * code word, it is likely that we never sent it to begin with.
22 * - Late failures: MII_LPA is filled with a value which seems to make sense
23 * but it actually is not what the LP is advertising. It seems that we
24 * can detect this using a magic bit in the WOL bank (reg 12 - bit 12).
25 * If this particular bit is not set when aneg is reported being done,
26 * it means MII_LPA is likely to be wrong.
28 * In both case, forcing a restart of the aneg process solve the problem.
29 * When this failure happens, the first retry is usually successful but,
30 * in some cases, it may take up to 6 retries to get a decent result
32 int meson_gxl_startup(struct phy_device *phydev)
34 unsigned int retries = 10;
35 int ret, wol, lpa, exp;
38 ret = genphy_update_link(phydev);
42 if (phydev->autoneg == AUTONEG_ENABLE) {
43 /* Need to access WOL bank, make sure the access is open */
44 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
47 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
50 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
53 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
57 /* Request LPI_STATUS WOL register */
58 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x8D80);
62 /* Read LPI_STATUS value */
63 wol = phy_read(phydev, MDIO_DEVAD_NONE, 0x15);
67 lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
71 exp = phy_read(phydev, MDIO_DEVAD_NONE, MII_EXPANSION);
75 if (!(wol & BIT(12)) ||
76 ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
78 /* Looks like aneg failed after all */
80 printf("%s LPA corruption max attempts\n",
85 printf("%s LPA corruption - aneg restart\n",
88 ret = genphy_restart_aneg(phydev);
98 return genphy_parse_link(phydev);
101 static int meson_gxl_phy_config(struct phy_device *phydev)
103 /* Enable Analog and DSP register Bank access by */
104 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
105 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
106 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
107 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
109 /* Write Analog register 23 */
110 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
111 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
113 /* Enable fractional PLL */
114 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
115 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
117 /* Program fraction FR_PLL_DIV1 */
118 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
119 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
121 /* Program fraction FR_PLL_DIV1 */
122 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
123 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
125 return genphy_config(phydev);
128 static struct phy_driver meson_gxl_phy_driver = {
129 .name = "Meson GXL Internal PHY",
132 .features = PHY_BASIC_FEATURES,
133 .config = &meson_gxl_phy_config,
134 .startup = &meson_gxl_startup,
135 .shutdown = &genphy_shutdown,
138 int phy_meson_gxl_init(void)
140 phy_register(&meson_gxl_phy_driver);