4 * SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2010-2011 Freescale Semiconductor, Inc.
13 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
15 /* 88E1011 PHY Status Register */
16 #define MIIM_88E1xxx_PHY_STATUS 0x11
17 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
18 #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
19 #define MIIM_88E1xxx_PHYSTAT_100 0x4000
20 #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
21 #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
22 #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
24 #define MIIM_88E1xxx_PHY_SCR 0x10
25 #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
27 /* 88E1111 PHY LED Control Register */
28 #define MIIM_88E1111_PHY_LED_CONTROL 24
29 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
30 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
32 /* 88E1111 Extended PHY Specific Control Register */
33 #define MIIM_88E1111_PHY_EXT_CR 0x14
34 #define MIIM_88E1111_RX_DELAY 0x80
35 #define MIIM_88E1111_TX_DELAY 0x2
37 /* 88E1111 Extended PHY Specific Status Register */
38 #define MIIM_88E1111_PHY_EXT_SR 0x1b
39 #define MIIM_88E1111_HWCFG_MODE_MASK 0xf
40 #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
41 #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
42 #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
43 #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
44 #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
45 #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
47 #define MIIM_88E1111_COPPER 0
48 #define MIIM_88E1111_FIBER 1
50 /* 88E1118 PHY defines */
51 #define MIIM_88E1118_PHY_PAGE 22
52 #define MIIM_88E1118_PHY_LED_PAGE 3
54 /* 88E1121 PHY LED Control Register */
55 #define MIIM_88E1121_PHY_LED_CTRL 16
56 #define MIIM_88E1121_PHY_LED_PAGE 3
57 #define MIIM_88E1121_PHY_LED_DEF 0x0030
59 /* 88E1121 PHY IRQ Enable/Status Register */
60 #define MIIM_88E1121_PHY_IRQ_EN 18
61 #define MIIM_88E1121_PHY_IRQ_STATUS 19
63 #define MIIM_88E1121_PHY_PAGE 22
65 /* 88E1145 Extended PHY Specific Control Register */
66 #define MIIM_88E1145_PHY_EXT_CR 20
67 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
68 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
70 #define MIIM_88E1145_PHY_LED_CONTROL 24
71 #define MIIM_88E1145_PHY_LED_DIRECT 0x4100
73 #define MIIM_88E1145_PHY_PAGE 29
74 #define MIIM_88E1145_PHY_CAL_OV 30
76 #define MIIM_88E1149_PHY_PAGE 29
78 /* 88E1310 PHY defines */
79 #define MIIM_88E1310_PHY_LED_CTRL 16
80 #define MIIM_88E1310_PHY_IRQ_EN 18
81 #define MIIM_88E1310_PHY_RGMII_CTRL 21
82 #define MIIM_88E1310_PHY_PAGE 22
84 /* Marvell 88E1011S */
85 static int m88e1011s_config(struct phy_device *phydev)
87 /* Reset and configure the PHY */
88 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
90 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
91 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
92 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
93 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
94 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
96 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
98 genphy_config_aneg(phydev);
103 /* Parse the 88E1011's status register for speed and duplex
106 static int m88e1xxx_parse_status(struct phy_device *phydev)
109 unsigned int mii_reg;
111 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
113 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
114 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
117 puts("Waiting for PHY realtime link");
118 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
119 /* Timeout reached ? */
120 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
121 puts(" TIMEOUT !\n");
126 if ((i++ % 1000) == 0)
129 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
130 MIIM_88E1xxx_PHY_STATUS);
133 udelay(500000); /* another 500 ms (results in faster booting) */
135 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
141 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
142 phydev->duplex = DUPLEX_FULL;
144 phydev->duplex = DUPLEX_HALF;
146 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
149 case MIIM_88E1xxx_PHYSTAT_GBIT:
150 phydev->speed = SPEED_1000;
152 case MIIM_88E1xxx_PHYSTAT_100:
153 phydev->speed = SPEED_100;
156 phydev->speed = SPEED_10;
163 static int m88e1011s_startup(struct phy_device *phydev)
167 ret = genphy_update_link(phydev);
171 return m88e1xxx_parse_status(phydev);
174 /* Marvell 88E1111S */
175 static int m88e1111s_config(struct phy_device *phydev)
179 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
180 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
181 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
182 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
183 reg = phy_read(phydev,
184 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
185 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
186 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
187 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
188 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
189 reg &= ~MIIM_88E1111_TX_DELAY;
190 reg |= MIIM_88E1111_RX_DELAY;
191 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
192 reg &= ~MIIM_88E1111_RX_DELAY;
193 reg |= MIIM_88E1111_TX_DELAY;
197 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
199 reg = phy_read(phydev,
200 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
202 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
204 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
205 reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
207 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
210 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
213 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
214 reg = phy_read(phydev,
215 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
217 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
218 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
219 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
221 phy_write(phydev, MDIO_DEVAD_NONE,
222 MIIM_88E1111_PHY_EXT_SR, reg);
225 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
226 reg = phy_read(phydev,
227 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
228 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
230 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
232 reg = phy_read(phydev, MDIO_DEVAD_NONE,
233 MIIM_88E1111_PHY_EXT_SR);
234 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
235 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
236 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
237 phy_write(phydev, MDIO_DEVAD_NONE,
238 MIIM_88E1111_PHY_EXT_SR, reg);
243 reg = phy_read(phydev, MDIO_DEVAD_NONE,
244 MIIM_88E1111_PHY_EXT_SR);
245 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
246 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
247 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
248 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
249 phy_write(phydev, MDIO_DEVAD_NONE,
250 MIIM_88E1111_PHY_EXT_SR, reg);
256 genphy_config_aneg(phydev);
257 genphy_restart_aneg(phydev);
263 * m88e1518_phy_writebits - write bits to a register
265 void m88e1518_phy_writebits(struct phy_device *phydev,
266 u8 reg_num, u16 offset, u16 len, u16 data)
270 if ((len + offset) >= 16)
271 mask = 0 - (1 << offset);
273 mask = (1 << (len + offset)) - (1 << offset);
275 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
278 reg |= data << offset;
280 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
283 static int m88e1518_config(struct phy_device *phydev)
286 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
287 * /88E1514 Rev A0, Errata Section 3.1
290 /* EEE initialization */
291 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff);
292 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
293 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
294 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
295 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
296 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
297 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
298 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
299 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
300 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
302 /* SGMII-to-Copper mode initialization */
303 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
305 phy_write(phydev, MDIO_DEVAD_NONE, 22, 18);
307 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
308 m88e1518_phy_writebits(phydev, 20, 0, 3, 1);
310 /* PHY reset is necessary after changing MODE[2:0] */
311 m88e1518_phy_writebits(phydev, 20, 15, 1, 1);
313 /* Reset page selection */
314 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
319 return m88e1111s_config(phydev);
322 /* Marvell 88E1510 */
323 static int m88e1510_config(struct phy_device *phydev)
326 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
328 /* Enable INTn output on LED[2] */
329 m88e1518_phy_writebits(phydev, 18, 7, 1, 1);
332 m88e1518_phy_writebits(phydev, 16, 0, 4, 3); /* LED[0]:0011 (ACT) */
333 m88e1518_phy_writebits(phydev, 16, 4, 4, 6); /* LED[1]:0110 (LINK) */
335 /* Reset page selection */
336 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
338 return m88e1518_config(phydev);
341 /* Marvell 88E1118 */
342 static int m88e1118_config(struct phy_device *phydev)
344 /* Change Page Number */
345 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
346 /* Delay RGMII TX and RX */
347 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
348 /* Change Page Number */
349 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
350 /* Adjust LED control */
351 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
352 /* Change Page Number */
353 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
355 return genphy_config_aneg(phydev);
358 static int m88e1118_startup(struct phy_device *phydev)
362 /* Change Page Number */
363 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
365 ret = genphy_update_link(phydev);
369 return m88e1xxx_parse_status(phydev);
372 /* Marvell 88E1121R */
373 static int m88e1121_config(struct phy_device *phydev)
377 /* Configure the PHY */
378 genphy_config_aneg(phydev);
380 /* Switch the page to access the led register */
381 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
382 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
383 MIIM_88E1121_PHY_LED_PAGE);
385 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
386 MIIM_88E1121_PHY_LED_DEF);
387 /* Restore the page pointer */
388 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
390 /* Disable IRQs and de-assert interrupt */
391 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
392 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
397 /* Marvell 88E1145 */
398 static int m88e1145_config(struct phy_device *phydev)
403 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
404 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
405 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
406 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
408 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
409 MIIM_88E1xxx_PHY_MDI_X_AUTO);
411 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
412 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
413 reg |= MIIM_M88E1145_RGMII_RX_DELAY |
414 MIIM_M88E1145_RGMII_TX_DELAY;
415 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
417 genphy_config_aneg(phydev);
424 static int m88e1145_startup(struct phy_device *phydev)
428 ret = genphy_update_link(phydev);
432 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
433 MIIM_88E1145_PHY_LED_DIRECT);
434 return m88e1xxx_parse_status(phydev);
437 /* Marvell 88E1149S */
438 static int m88e1149_config(struct phy_device *phydev)
440 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
441 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
442 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
443 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
444 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
446 genphy_config_aneg(phydev);
453 /* Marvell 88E1310 */
454 static int m88e1310_config(struct phy_device *phydev)
458 /* LED link and activity */
459 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
460 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
461 reg = (reg & ~0xf) | 0x1;
462 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
464 /* Set LED2/INT to INT mode, low active */
465 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
466 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
467 reg = (reg & 0x77ff) | 0x0880;
468 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
470 /* Set RGMII delay */
471 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
472 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
474 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
476 /* Ensure to return to page 0 */
477 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
479 genphy_config_aneg(phydev);
485 static struct phy_driver M88E1011S_driver = {
486 .name = "Marvell 88E1011S",
489 .features = PHY_GBIT_FEATURES,
490 .config = &m88e1011s_config,
491 .startup = &m88e1011s_startup,
492 .shutdown = &genphy_shutdown,
495 static struct phy_driver M88E1111S_driver = {
496 .name = "Marvell 88E1111S",
499 .features = PHY_GBIT_FEATURES,
500 .config = &m88e1111s_config,
501 .startup = &m88e1011s_startup,
502 .shutdown = &genphy_shutdown,
505 static struct phy_driver M88E1118_driver = {
506 .name = "Marvell 88E1118",
509 .features = PHY_GBIT_FEATURES,
510 .config = &m88e1118_config,
511 .startup = &m88e1118_startup,
512 .shutdown = &genphy_shutdown,
515 static struct phy_driver M88E1118R_driver = {
516 .name = "Marvell 88E1118R",
519 .features = PHY_GBIT_FEATURES,
520 .config = &m88e1118_config,
521 .startup = &m88e1118_startup,
522 .shutdown = &genphy_shutdown,
525 static struct phy_driver M88E1121R_driver = {
526 .name = "Marvell 88E1121R",
529 .features = PHY_GBIT_FEATURES,
530 .config = &m88e1121_config,
531 .startup = &genphy_startup,
532 .shutdown = &genphy_shutdown,
535 static struct phy_driver M88E1145_driver = {
536 .name = "Marvell 88E1145",
539 .features = PHY_GBIT_FEATURES,
540 .config = &m88e1145_config,
541 .startup = &m88e1145_startup,
542 .shutdown = &genphy_shutdown,
545 static struct phy_driver M88E1149S_driver = {
546 .name = "Marvell 88E1149S",
549 .features = PHY_GBIT_FEATURES,
550 .config = &m88e1149_config,
551 .startup = &m88e1011s_startup,
552 .shutdown = &genphy_shutdown,
555 static struct phy_driver M88E1510_driver = {
556 .name = "Marvell 88E1510",
559 .features = PHY_GBIT_FEATURES,
560 .config = &m88e1510_config,
561 .startup = &m88e1011s_startup,
562 .shutdown = &genphy_shutdown,
565 static struct phy_driver M88E1518_driver = {
566 .name = "Marvell 88E1518",
569 .features = PHY_GBIT_FEATURES,
570 .config = &m88e1518_config,
571 .startup = &m88e1011s_startup,
572 .shutdown = &genphy_shutdown,
575 static struct phy_driver M88E1310_driver = {
576 .name = "Marvell 88E1310",
579 .features = PHY_GBIT_FEATURES,
580 .config = &m88e1310_config,
581 .startup = &m88e1011s_startup,
582 .shutdown = &genphy_shutdown,
585 int phy_marvell_init(void)
587 phy_register(&M88E1310_driver);
588 phy_register(&M88E1149S_driver);
589 phy_register(&M88E1145_driver);
590 phy_register(&M88E1121R_driver);
591 phy_register(&M88E1118_driver);
592 phy_register(&M88E1118R_driver);
593 phy_register(&M88E1111S_driver);
594 phy_register(&M88E1011S_driver);
595 phy_register(&M88E1510_driver);
596 phy_register(&M88E1518_driver);