4 * SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2010-2011 Freescale Semiconductor, Inc.
14 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
16 /* 88E1011 PHY Status Register */
17 #define MIIM_88E1xxx_PHY_STATUS 0x11
18 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
19 #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
20 #define MIIM_88E1xxx_PHYSTAT_100 0x4000
21 #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
22 #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
23 #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
25 #define MIIM_88E1xxx_PHY_SCR 0x10
26 #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
28 /* 88E1111 PHY LED Control Register */
29 #define MIIM_88E1111_PHY_LED_CONTROL 24
30 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
31 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
33 /* 88E1111 Extended PHY Specific Control Register */
34 #define MIIM_88E1111_PHY_EXT_CR 0x14
35 #define MIIM_88E1111_RX_DELAY 0x80
36 #define MIIM_88E1111_TX_DELAY 0x2
38 /* 88E1111 Extended PHY Specific Status Register */
39 #define MIIM_88E1111_PHY_EXT_SR 0x1b
40 #define MIIM_88E1111_HWCFG_MODE_MASK 0xf
41 #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
42 #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
43 #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
44 #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
45 #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
46 #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
48 #define MIIM_88E1111_COPPER 0
49 #define MIIM_88E1111_FIBER 1
51 /* 88E1118 PHY defines */
52 #define MIIM_88E1118_PHY_PAGE 22
53 #define MIIM_88E1118_PHY_LED_PAGE 3
55 /* 88E1121 PHY LED Control Register */
56 #define MIIM_88E1121_PHY_LED_CTRL 16
57 #define MIIM_88E1121_PHY_LED_PAGE 3
58 #define MIIM_88E1121_PHY_LED_DEF 0x0030
60 /* 88E1121 PHY IRQ Enable/Status Register */
61 #define MIIM_88E1121_PHY_IRQ_EN 18
62 #define MIIM_88E1121_PHY_IRQ_STATUS 19
64 #define MIIM_88E1121_PHY_PAGE 22
66 /* 88E1145 Extended PHY Specific Control Register */
67 #define MIIM_88E1145_PHY_EXT_CR 20
68 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
69 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
71 #define MIIM_88E1145_PHY_LED_CONTROL 24
72 #define MIIM_88E1145_PHY_LED_DIRECT 0x4100
74 #define MIIM_88E1145_PHY_PAGE 29
75 #define MIIM_88E1145_PHY_CAL_OV 30
77 #define MIIM_88E1149_PHY_PAGE 29
79 /* 88E1310 PHY defines */
80 #define MIIM_88E1310_PHY_LED_CTRL 16
81 #define MIIM_88E1310_PHY_IRQ_EN 18
82 #define MIIM_88E1310_PHY_RGMII_CTRL 21
83 #define MIIM_88E1310_PHY_PAGE 22
85 /* Marvell 88E1011S */
86 static int m88e1011s_config(struct phy_device *phydev)
88 /* Reset and configure the PHY */
89 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
91 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
92 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
93 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
94 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
95 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
97 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
99 genphy_config_aneg(phydev);
104 /* Parse the 88E1011's status register for speed and duplex
107 static int m88e1xxx_parse_status(struct phy_device *phydev)
110 unsigned int mii_reg;
112 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
114 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
115 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
118 puts("Waiting for PHY realtime link");
119 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
120 /* Timeout reached ? */
121 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
122 puts(" TIMEOUT !\n");
127 if ((i++ % 1000) == 0)
130 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
131 MIIM_88E1xxx_PHY_STATUS);
134 udelay(500000); /* another 500 ms (results in faster booting) */
136 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
142 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
143 phydev->duplex = DUPLEX_FULL;
145 phydev->duplex = DUPLEX_HALF;
147 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
150 case MIIM_88E1xxx_PHYSTAT_GBIT:
151 phydev->speed = SPEED_1000;
153 case MIIM_88E1xxx_PHYSTAT_100:
154 phydev->speed = SPEED_100;
157 phydev->speed = SPEED_10;
164 static int m88e1011s_startup(struct phy_device *phydev)
168 ret = genphy_update_link(phydev);
172 return m88e1xxx_parse_status(phydev);
175 /* Marvell 88E1111S */
176 static int m88e1111s_config(struct phy_device *phydev)
180 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
181 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
182 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
183 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
184 reg = phy_read(phydev,
185 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
186 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
187 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
188 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
189 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
190 reg &= ~MIIM_88E1111_TX_DELAY;
191 reg |= MIIM_88E1111_RX_DELAY;
192 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
193 reg &= ~MIIM_88E1111_RX_DELAY;
194 reg |= MIIM_88E1111_TX_DELAY;
198 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
200 reg = phy_read(phydev,
201 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
203 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
205 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
206 reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
208 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
211 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
214 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
215 reg = phy_read(phydev,
216 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
218 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
219 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
220 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
222 phy_write(phydev, MDIO_DEVAD_NONE,
223 MIIM_88E1111_PHY_EXT_SR, reg);
226 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
227 reg = phy_read(phydev,
228 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
229 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
231 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
233 reg = phy_read(phydev, MDIO_DEVAD_NONE,
234 MIIM_88E1111_PHY_EXT_SR);
235 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
236 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
237 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
238 phy_write(phydev, MDIO_DEVAD_NONE,
239 MIIM_88E1111_PHY_EXT_SR, reg);
244 reg = phy_read(phydev, MDIO_DEVAD_NONE,
245 MIIM_88E1111_PHY_EXT_SR);
246 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
247 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
248 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
249 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
250 phy_write(phydev, MDIO_DEVAD_NONE,
251 MIIM_88E1111_PHY_EXT_SR, reg);
257 genphy_config_aneg(phydev);
258 genphy_restart_aneg(phydev);
264 * m88e1518_phy_writebits - write bits to a register
266 void m88e1518_phy_writebits(struct phy_device *phydev,
267 u8 reg_num, u16 offset, u16 len, u16 data)
271 if ((len + offset) >= 16)
272 mask = 0 - (1 << offset);
274 mask = (1 << (len + offset)) - (1 << offset);
276 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
279 reg |= data << offset;
281 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
284 static int m88e1518_config(struct phy_device *phydev)
287 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
288 * /88E1514 Rev A0, Errata Section 3.1
291 /* EEE initialization */
292 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff);
293 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
294 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
295 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
296 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
297 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
298 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
299 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
300 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
301 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
303 /* SGMII-to-Copper mode initialization */
304 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
306 phy_write(phydev, MDIO_DEVAD_NONE, 22, 18);
308 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
309 m88e1518_phy_writebits(phydev, 20, 0, 3, 1);
311 /* PHY reset is necessary after changing MODE[2:0] */
312 m88e1518_phy_writebits(phydev, 20, 15, 1, 1);
314 /* Reset page selection */
315 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
320 return m88e1111s_config(phydev);
323 /* Marvell 88E1510 */
324 static int m88e1510_config(struct phy_device *phydev)
327 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
329 /* Enable INTn output on LED[2] */
330 m88e1518_phy_writebits(phydev, 18, 7, 1, 1);
333 m88e1518_phy_writebits(phydev, 16, 0, 4, 3); /* LED[0]:0011 (ACT) */
334 m88e1518_phy_writebits(phydev, 16, 4, 4, 6); /* LED[1]:0110 (LINK) */
336 /* Reset page selection */
337 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
339 return m88e1518_config(phydev);
342 /* Marvell 88E1118 */
343 static int m88e1118_config(struct phy_device *phydev)
345 /* Change Page Number */
346 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
347 /* Delay RGMII TX and RX */
348 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
349 /* Change Page Number */
350 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
351 /* Adjust LED control */
352 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
353 /* Change Page Number */
354 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
356 return genphy_config_aneg(phydev);
359 static int m88e1118_startup(struct phy_device *phydev)
363 /* Change Page Number */
364 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
366 ret = genphy_update_link(phydev);
370 return m88e1xxx_parse_status(phydev);
373 /* Marvell 88E1121R */
374 static int m88e1121_config(struct phy_device *phydev)
378 /* Configure the PHY */
379 genphy_config_aneg(phydev);
381 /* Switch the page to access the led register */
382 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
383 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
384 MIIM_88E1121_PHY_LED_PAGE);
386 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
387 MIIM_88E1121_PHY_LED_DEF);
388 /* Restore the page pointer */
389 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
391 /* Disable IRQs and de-assert interrupt */
392 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
393 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
398 /* Marvell 88E1145 */
399 static int m88e1145_config(struct phy_device *phydev)
404 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
405 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
406 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
407 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
409 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
410 MIIM_88E1xxx_PHY_MDI_X_AUTO);
412 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
413 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
414 reg |= MIIM_M88E1145_RGMII_RX_DELAY |
415 MIIM_M88E1145_RGMII_TX_DELAY;
416 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
418 genphy_config_aneg(phydev);
425 static int m88e1145_startup(struct phy_device *phydev)
429 ret = genphy_update_link(phydev);
433 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
434 MIIM_88E1145_PHY_LED_DIRECT);
435 return m88e1xxx_parse_status(phydev);
438 /* Marvell 88E1149S */
439 static int m88e1149_config(struct phy_device *phydev)
441 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
442 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
443 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
444 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
445 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
447 genphy_config_aneg(phydev);
454 /* Marvell 88E1310 */
455 static int m88e1310_config(struct phy_device *phydev)
459 /* LED link and activity */
460 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
461 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
462 reg = (reg & ~0xf) | 0x1;
463 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
465 /* Set LED2/INT to INT mode, low active */
466 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
467 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
468 reg = (reg & 0x77ff) | 0x0880;
469 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
471 /* Set RGMII delay */
472 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
473 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
475 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
477 /* Ensure to return to page 0 */
478 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
480 return genphy_config_aneg(phydev);
483 static int m88e1680_config(struct phy_device *phydev)
486 * As per Marvell Release Notes - Alaska V 88E1680 Rev A2
492 /* Matrix LED mode (not neede if single LED mode is used */
493 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004);
494 reg = phy_read(phydev, MDIO_DEVAD_NONE, 27);
496 phy_write(phydev, MDIO_DEVAD_NONE, 27, reg);
498 /* QSGMII TX amplitude change */
499 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd);
500 phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53);
501 phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d);
502 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
504 /* EEE initialization */
505 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
506 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030);
507 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c);
508 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc);
509 phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c);
510 phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c);
511 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
512 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
514 res = genphy_config_aneg(phydev);
519 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
521 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
526 static struct phy_driver M88E1011S_driver = {
527 .name = "Marvell 88E1011S",
530 .features = PHY_GBIT_FEATURES,
531 .config = &m88e1011s_config,
532 .startup = &m88e1011s_startup,
533 .shutdown = &genphy_shutdown,
536 static struct phy_driver M88E1111S_driver = {
537 .name = "Marvell 88E1111S",
540 .features = PHY_GBIT_FEATURES,
541 .config = &m88e1111s_config,
542 .startup = &m88e1011s_startup,
543 .shutdown = &genphy_shutdown,
546 static struct phy_driver M88E1118_driver = {
547 .name = "Marvell 88E1118",
550 .features = PHY_GBIT_FEATURES,
551 .config = &m88e1118_config,
552 .startup = &m88e1118_startup,
553 .shutdown = &genphy_shutdown,
556 static struct phy_driver M88E1118R_driver = {
557 .name = "Marvell 88E1118R",
560 .features = PHY_GBIT_FEATURES,
561 .config = &m88e1118_config,
562 .startup = &m88e1118_startup,
563 .shutdown = &genphy_shutdown,
566 static struct phy_driver M88E1121R_driver = {
567 .name = "Marvell 88E1121R",
570 .features = PHY_GBIT_FEATURES,
571 .config = &m88e1121_config,
572 .startup = &genphy_startup,
573 .shutdown = &genphy_shutdown,
576 static struct phy_driver M88E1145_driver = {
577 .name = "Marvell 88E1145",
580 .features = PHY_GBIT_FEATURES,
581 .config = &m88e1145_config,
582 .startup = &m88e1145_startup,
583 .shutdown = &genphy_shutdown,
586 static struct phy_driver M88E1149S_driver = {
587 .name = "Marvell 88E1149S",
590 .features = PHY_GBIT_FEATURES,
591 .config = &m88e1149_config,
592 .startup = &m88e1011s_startup,
593 .shutdown = &genphy_shutdown,
596 static struct phy_driver M88E1510_driver = {
597 .name = "Marvell 88E1510",
600 .features = PHY_GBIT_FEATURES,
601 .config = &m88e1510_config,
602 .startup = &m88e1011s_startup,
603 .shutdown = &genphy_shutdown,
606 static struct phy_driver M88E1518_driver = {
607 .name = "Marvell 88E1518",
610 .features = PHY_GBIT_FEATURES,
611 .config = &m88e1518_config,
612 .startup = &m88e1011s_startup,
613 .shutdown = &genphy_shutdown,
616 static struct phy_driver M88E1310_driver = {
617 .name = "Marvell 88E1310",
620 .features = PHY_GBIT_FEATURES,
621 .config = &m88e1310_config,
622 .startup = &m88e1011s_startup,
623 .shutdown = &genphy_shutdown,
626 static struct phy_driver M88E1680_driver = {
627 .name = "Marvell 88E1680",
630 .features = PHY_GBIT_FEATURES,
631 .config = &m88e1680_config,
632 .startup = &genphy_startup,
633 .shutdown = &genphy_shutdown,
636 int phy_marvell_init(void)
638 phy_register(&M88E1310_driver);
639 phy_register(&M88E1149S_driver);
640 phy_register(&M88E1145_driver);
641 phy_register(&M88E1121R_driver);
642 phy_register(&M88E1118_driver);
643 phy_register(&M88E1118R_driver);
644 phy_register(&M88E1111S_driver);
645 phy_register(&M88E1011S_driver);
646 phy_register(&M88E1510_driver);
647 phy_register(&M88E1518_driver);
648 phy_register(&M88E1680_driver);