4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * Copyright 2010-2011 Freescale Semiconductor, Inc.
27 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
29 /* 88E1011 PHY Status Register */
30 #define MIIM_88E1xxx_PHY_STATUS 0x11
31 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
32 #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
33 #define MIIM_88E1xxx_PHYSTAT_100 0x4000
34 #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
35 #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
36 #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
38 #define MIIM_88E1xxx_PHY_SCR 0x10
39 #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
41 /* 88E1111 PHY LED Control Register */
42 #define MIIM_88E1111_PHY_LED_CONTROL 24
43 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
44 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
46 /* 88E1111 Extended PHY Specific Control Register */
47 #define MIIM_88E1111_PHY_EXT_CR 0x14
48 #define MIIM_88E1111_RX_DELAY 0x80
49 #define MIIM_88E1111_TX_DELAY 0x2
51 /* 88E1111 Extended PHY Specific Status Register */
52 #define MIIM_88E1111_PHY_EXT_SR 0x1b
53 #define MIIM_88E1111_HWCFG_MODE_MASK 0xf
54 #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
55 #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
56 #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
57 #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
58 #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
59 #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
61 #define MIIM_88E1111_COPPER 0
62 #define MIIM_88E1111_FIBER 1
64 /* 88E1118 PHY defines */
65 #define MIIM_88E1118_PHY_PAGE 22
66 #define MIIM_88E1118_PHY_LED_PAGE 3
68 /* 88E1121 PHY LED Control Register */
69 #define MIIM_88E1121_PHY_LED_CTRL 16
70 #define MIIM_88E1121_PHY_LED_PAGE 3
71 #define MIIM_88E1121_PHY_LED_DEF 0x0030
73 /* 88E1121 PHY IRQ Enable/Status Register */
74 #define MIIM_88E1121_PHY_IRQ_EN 18
75 #define MIIM_88E1121_PHY_IRQ_STATUS 19
77 #define MIIM_88E1121_PHY_PAGE 22
79 /* 88E1145 Extended PHY Specific Control Register */
80 #define MIIM_88E1145_PHY_EXT_CR 20
81 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
82 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
84 #define MIIM_88E1145_PHY_LED_CONTROL 24
85 #define MIIM_88E1145_PHY_LED_DIRECT 0x4100
87 #define MIIM_88E1145_PHY_PAGE 29
88 #define MIIM_88E1145_PHY_CAL_OV 30
90 #define MIIM_88E1149_PHY_PAGE 29
92 /* 88E1310 PHY defines */
93 #define MIIM_88E1310_PHY_LED_CTRL 16
94 #define MIIM_88E1310_PHY_IRQ_EN 18
95 #define MIIM_88E1310_PHY_RGMII_CTRL 21
96 #define MIIM_88E1310_PHY_PAGE 22
98 /* Marvell 88E1011S */
99 static int m88e1011s_config(struct phy_device *phydev)
101 /* Reset and configure the PHY */
102 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
104 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
105 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
106 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
107 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
108 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
110 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
112 genphy_config_aneg(phydev);
117 /* Parse the 88E1011's status register for speed and duplex
120 static uint m88e1xxx_parse_status(struct phy_device *phydev)
123 unsigned int mii_reg;
125 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
127 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
128 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
131 puts("Waiting for PHY realtime link");
132 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
133 /* Timeout reached ? */
134 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
135 puts(" TIMEOUT !\n");
140 if ((i++ % 1000) == 0)
143 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
144 MIIM_88E1xxx_PHY_STATUS);
147 udelay(500000); /* another 500 ms (results in faster booting) */
149 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
155 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
156 phydev->duplex = DUPLEX_FULL;
158 phydev->duplex = DUPLEX_HALF;
160 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
163 case MIIM_88E1xxx_PHYSTAT_GBIT:
164 phydev->speed = SPEED_1000;
166 case MIIM_88E1xxx_PHYSTAT_100:
167 phydev->speed = SPEED_100;
170 phydev->speed = SPEED_10;
177 static int m88e1011s_startup(struct phy_device *phydev)
179 genphy_update_link(phydev);
180 m88e1xxx_parse_status(phydev);
185 /* Marvell 88E1111S */
186 static int m88e1111s_config(struct phy_device *phydev)
191 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
192 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
193 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
194 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
195 reg = phy_read(phydev,
196 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
197 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
198 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
199 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
200 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
201 reg &= ~MIIM_88E1111_TX_DELAY;
202 reg |= MIIM_88E1111_RX_DELAY;
203 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
204 reg &= ~MIIM_88E1111_RX_DELAY;
205 reg |= MIIM_88E1111_TX_DELAY;
209 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
211 reg = phy_read(phydev,
212 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
214 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
216 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
217 reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
219 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
222 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
225 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
226 reg = phy_read(phydev,
227 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
229 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
230 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
231 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
233 phy_write(phydev, MDIO_DEVAD_NONE,
234 MIIM_88E1111_PHY_EXT_SR, reg);
237 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
238 reg = phy_read(phydev,
239 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
240 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
242 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
244 reg = phy_read(phydev, MDIO_DEVAD_NONE,
245 MIIM_88E1111_PHY_EXT_SR);
246 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
247 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
248 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
249 phy_write(phydev, MDIO_DEVAD_NONE,
250 MIIM_88E1111_PHY_EXT_SR, reg);
254 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
256 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
257 while ((reg & BMCR_RESET) && --timeout) {
259 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
262 printf("%s: phy soft reset timeout\n", __func__);
264 reg = phy_read(phydev, MDIO_DEVAD_NONE,
265 MIIM_88E1111_PHY_EXT_SR);
266 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
267 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
268 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
269 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
270 phy_write(phydev, MDIO_DEVAD_NONE,
271 MIIM_88E1111_PHY_EXT_SR, reg);
276 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
278 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
279 while ((reg & BMCR_RESET) && --timeout) {
281 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
284 printf("%s: phy soft reset timeout\n", __func__);
286 genphy_config_aneg(phydev);
293 /* Marvell 88E1118 */
294 static int m88e1118_config(struct phy_device *phydev)
296 /* Change Page Number */
297 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
298 /* Delay RGMII TX and RX */
299 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
300 /* Change Page Number */
301 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
302 /* Adjust LED control */
303 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
304 /* Change Page Number */
305 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
307 genphy_config_aneg(phydev);
314 static int m88e1118_startup(struct phy_device *phydev)
316 /* Change Page Number */
317 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
319 genphy_update_link(phydev);
320 m88e1xxx_parse_status(phydev);
325 /* Marvell 88E1121R */
326 static int m88e1121_config(struct phy_device *phydev)
330 /* Configure the PHY */
331 genphy_config_aneg(phydev);
333 /* Switch the page to access the led register */
334 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
335 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
336 MIIM_88E1121_PHY_LED_PAGE);
338 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
339 MIIM_88E1121_PHY_LED_DEF);
340 /* Restore the page pointer */
341 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
343 /* Disable IRQs and de-assert interrupt */
344 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
345 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
350 /* Marvell 88E1145 */
351 static int m88e1145_config(struct phy_device *phydev)
356 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
357 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
358 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
359 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
361 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
362 MIIM_88E1xxx_PHY_MDI_X_AUTO);
364 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
365 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
366 reg |= MIIM_M88E1145_RGMII_RX_DELAY |
367 MIIM_M88E1145_RGMII_TX_DELAY;
368 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
370 genphy_config_aneg(phydev);
377 static int m88e1145_startup(struct phy_device *phydev)
379 genphy_update_link(phydev);
380 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
381 MIIM_88E1145_PHY_LED_DIRECT);
382 m88e1xxx_parse_status(phydev);
387 /* Marvell 88E1149S */
388 static int m88e1149_config(struct phy_device *phydev)
390 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
391 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
392 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
393 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
394 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
396 genphy_config_aneg(phydev);
403 /* Marvell 88E1310 */
404 static int m88e1310_config(struct phy_device *phydev)
408 /* LED link and activity */
409 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
410 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
411 reg = (reg & ~0xf) | 0x1;
412 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
414 /* Set LED2/INT to INT mode, low active */
415 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
416 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
417 reg = (reg & 0x77ff) | 0x0880;
418 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
420 /* Set RGMII delay */
421 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
422 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
424 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
426 /* Ensure to return to page 0 */
427 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
429 genphy_config_aneg(phydev);
435 static struct phy_driver M88E1011S_driver = {
436 .name = "Marvell 88E1011S",
439 .features = PHY_GBIT_FEATURES,
440 .config = &m88e1011s_config,
441 .startup = &m88e1011s_startup,
442 .shutdown = &genphy_shutdown,
445 static struct phy_driver M88E1111S_driver = {
446 .name = "Marvell 88E1111S",
449 .features = PHY_GBIT_FEATURES,
450 .config = &m88e1111s_config,
451 .startup = &m88e1011s_startup,
452 .shutdown = &genphy_shutdown,
455 static struct phy_driver M88E1118_driver = {
456 .name = "Marvell 88E1118",
459 .features = PHY_GBIT_FEATURES,
460 .config = &m88e1118_config,
461 .startup = &m88e1118_startup,
462 .shutdown = &genphy_shutdown,
465 static struct phy_driver M88E1118R_driver = {
466 .name = "Marvell 88E1118R",
469 .features = PHY_GBIT_FEATURES,
470 .config = &m88e1118_config,
471 .startup = &m88e1118_startup,
472 .shutdown = &genphy_shutdown,
475 static struct phy_driver M88E1121R_driver = {
476 .name = "Marvell 88E1121R",
479 .features = PHY_GBIT_FEATURES,
480 .config = &m88e1121_config,
481 .startup = &genphy_startup,
482 .shutdown = &genphy_shutdown,
485 static struct phy_driver M88E1145_driver = {
486 .name = "Marvell 88E1145",
489 .features = PHY_GBIT_FEATURES,
490 .config = &m88e1145_config,
491 .startup = &m88e1145_startup,
492 .shutdown = &genphy_shutdown,
495 static struct phy_driver M88E1149S_driver = {
496 .name = "Marvell 88E1149S",
499 .features = PHY_GBIT_FEATURES,
500 .config = &m88e1149_config,
501 .startup = &m88e1011s_startup,
502 .shutdown = &genphy_shutdown,
505 static struct phy_driver M88E1518_driver = {
506 .name = "Marvell 88E1518",
509 .features = PHY_GBIT_FEATURES,
510 .config = &m88e1111s_config,
511 .startup = &m88e1011s_startup,
512 .shutdown = &genphy_shutdown,
515 static struct phy_driver M88E1310_driver = {
516 .name = "Marvell 88E1310",
519 .features = PHY_GBIT_FEATURES,
520 .config = &m88e1310_config,
521 .startup = &m88e1011s_startup,
522 .shutdown = &genphy_shutdown,
525 int phy_marvell_init(void)
527 phy_register(&M88E1310_driver);
528 phy_register(&M88E1149S_driver);
529 phy_register(&M88E1145_driver);
530 phy_register(&M88E1121R_driver);
531 phy_register(&M88E1118_driver);
532 phy_register(&M88E1118R_driver);
533 phy_register(&M88E1111S_driver);
534 phy_register(&M88E1011S_driver);
535 phy_register(&M88E1518_driver);