drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * TI PHY drivers
   4  *
   5  */
   6 #include <common.h>
   7 #include <log.h>
   8 #include <phy.h>
   9 #include <dm/devres.h>
  10 #include <linux/compat.h>
  11 #include <malloc.h>
  12
  13 #include <dm.h>
  14 #include <dt-bindings/net/ti-dp83867.h>
  15
  16
  17 /* TI DP83867 */
  18 #define DP83867_DEVADDR         0x1f
  19
  20 #define MII_DP83867_PHYCTRL     0x10
  21 #define MII_DP83867_MICR        0x12
  22 #define MII_DP83867_CFG2        0x14
  23 #define MII_DP83867_BISCR       0x16
  24 #define DP83867_CTRL            0x1f
  25
  26 /* Extended Registers */
  27 #define DP83867_CFG4            0x0031
  28 #define DP83867_RGMIICTL        0x0032
  29 #define DP83867_STRAP_STS1      0x006E
  30 #define DP83867_STRAP_STS2      0x006f
  31 #define DP83867_RGMIIDCTL       0x0086
  32 #define DP83867_IO_MUX_CFG      0x0170
  33 #define DP83867_SGMIICTL        0x00D3
  34
  35 #define DP83867_SW_RESET        BIT(15)
  36 #define DP83867_SW_RESTART      BIT(14)
  37
  38 /* MICR Interrupt bits */
  39 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  40 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  41 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  42 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  43 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  44 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  45 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  46 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  47 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  48 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  49 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  50 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  51
  52 /* RGMIICTL bits */
  53 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  54 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  55
  56 /* STRAP_STS1 bits */
  57 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  58
  59 /* STRAP_STS2 bits */
  60 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK     GENMASK(6, 4)
  61 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT    4
  62 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK     GENMASK(2, 0)
  63 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT    0
  64 #define DP83867_STRAP_STS2_CLK_SKEW_NONE        BIT(2)
  65
  66 /* PHY CTRL bits */
  67 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  68 #define DP83867_PHYCR_FIFO_DEPTH_MASK           GENMASK(15, 14)
  69 #define DP83867_PHYCR_RESERVED_MASK     BIT(11)
  70 #define DP83867_PHYCR_FORCE_LINK_GOOD   BIT(10)
  71 #define DP83867_MDI_CROSSOVER           5
  72 #define DP83867_MDI_CROSSOVER_MDIX      2
  73 #define DP83867_PHYCTRL_SGMIIEN                 0x0800
  74 #define DP83867_PHYCTRL_RXFIFO_SHIFT    12
  75 #define DP83867_PHYCTRL_TXFIFO_SHIFT    14
  76
  77 /* RGMIIDCTL bits */
  78 #define DP83867_RGMII_TX_CLK_DELAY_MAX          0xf
  79 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  80 #define DP83867_RGMII_RX_CLK_DELAY_MAX          0xf
  81
  82 /* CFG2 bits */
  83 #define MII_DP83867_CFG2_SPEEDOPT_10EN          0x0040
  84 #define MII_DP83867_CFG2_SGMII_AUTONEGEN        0x0080
  85 #define MII_DP83867_CFG2_SPEEDOPT_ENH           0x0100
  86 #define MII_DP83867_CFG2_SPEEDOPT_CNT           0x0800
  87 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW        0x2000
  88 #define MII_DP83867_CFG2_MASK                   0x003F
  89
  90 /* User setting - can be taken from DTS */
  91 #define DEFAULT_FIFO_DEPTH      DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
  92
  93 /* IO_MUX_CFG bits */
  94 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  95
  96 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  97 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  98 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE        BIT(6)
  99 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
 100 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       \
 101                 GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
 102
 103 /* CFG4 bits */
 104 #define DP83867_CFG4_PORT_MIRROR_EN             BIT(0)
 105
 106 /* SGMIICTL bits */
 107 #define DP83867_SGMII_TYPE                      BIT(14)
 108
 109 enum {
 110         DP83867_PORT_MIRRORING_KEEP,
 111         DP83867_PORT_MIRRORING_EN,
 112         DP83867_PORT_MIRRORING_DIS,
 113 };
 114
 115 struct dp83867_private {
 116         u32 rx_id_delay;
 117         u32 tx_id_delay;
 118         int fifo_depth;
 119         int io_impedance;
 120         bool rxctrl_strap_quirk;
 121         int port_mirroring;
 122         bool set_clk_output;
 123         unsigned int clk_output_sel;
 124         bool sgmii_ref_clk_en;
 125 };
 126
 127 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 128 {
 129         struct dp83867_private *dp83867 =
 130                 (struct dp83867_private *)phydev->priv;
 131         u16 val;
 132
 133         val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
 134
 135         if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
 136                 val |= DP83867_CFG4_PORT_MIRROR_EN;
 137         else
 138                 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
 139
 140         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
 141
 142         return 0;
 143 }
 144
 145 #if defined(CONFIG_DM_ETH)
 146 /**
 147  * dp83867_data_init - Convenience function for setting PHY specific data
 148  *
 149  * @phydev: the phy_device struct
 150  */
 151 static int dp83867_of_init(struct phy_device *phydev)
 152 {
 153         struct dp83867_private *dp83867 = phydev->priv;
 154         ofnode node;
 155         int ret;
 156
 157         node = phy_get_ofnode(phydev);
 158         if (!ofnode_valid(node))
 159                 return -EINVAL;
 160
 161         /* Optional configuration */
 162         ret = ofnode_read_u32(node, "ti,clk-output-sel",
 163                               &dp83867->clk_output_sel);
 164         /* If not set, keep default */
 165         if (!ret) {
 166                 dp83867->set_clk_output = true;
 167                 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
 168                  * DP83867_CLK_O_SEL_OFF.
 169                  */
 170                 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
 171                     dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
 172                         pr_debug("ti,clk-output-sel value %u out of range\n",
 173                                  dp83867->clk_output_sel);
 174                         return -EINVAL;
 175                 }
 176         }
 177
 178         if (ofnode_read_bool(node, "ti,max-output-impedance"))
 179                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 180         else if (ofnode_read_bool(node, "ti,min-output-impedance"))
 181                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 182         else
 183                 dp83867->io_impedance = -EINVAL;
 184
 185         if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
 186                 dp83867->rxctrl_strap_quirk = true;
 187
 188         /* Existing behavior was to use default pin strapping delay in rgmii
 189          * mode, but rgmii should have meant no delay.  Warn existing users.
 190          */
 191         if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
 192                 u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 193                                        DP83867_STRAP_STS2);
 194                 u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
 195                              DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
 196                 u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
 197                              DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
 198
 199                 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
 200                     rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
 201                         pr_warn("PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
 202                                 "Should be 'rgmii-id' to use internal delays\n");
 203         }
 204
 205         /* RX delay *must* be specified if internal delay of RX is used. */
 206         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 207             phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 208                 ret = ofnode_read_u32(node, "ti,rx-internal-delay",
 209                                       &dp83867->rx_id_delay);
 210                 if (ret) {
 211                         pr_debug("ti,rx-internal-delay must be specified\n");
 212                         return ret;
 213                 }
 214                 if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
 215                         pr_debug("ti,rx-internal-delay value of %u out of range\n",
 216                                  dp83867->rx_id_delay);
 217                         return -EINVAL;
 218                 }
 219         }
 220
 221         /* TX delay *must* be specified if internal delay of RX is used. */
 222         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 223             phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
 224                 ret = ofnode_read_u32(node, "ti,tx-internal-delay",
 225                                       &dp83867->tx_id_delay);
 226                 if (ret) {
 227                         debug("ti,tx-internal-delay must be specified\n");
 228                         return ret;
 229                 }
 230                 if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
 231                         pr_debug("ti,tx-internal-delay value of %u out of range\n",
 232                                  dp83867->tx_id_delay);
 233                         return -EINVAL;
 234                 }
 235         }
 236
 237         dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
 238                                                       DEFAULT_FIFO_DEPTH);
 239         if (ofnode_read_bool(node, "enet-phy-lane-swap"))
 240                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
 241
 242         if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
 243                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
 244
 245         if (ofnode_read_bool(node, "ti,sgmii-ref-clock-output-enable"))
 246                 dp83867->sgmii_ref_clk_en = true;
 247
 248         return 0;
 249 }
 250 #else
 251 static int dp83867_of_init(struct phy_device *phydev)
 252 {
 253         struct dp83867_private *dp83867 = phydev->priv;
 254
 255         dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS;
 256         dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS;
 257         dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
 258         dp83867->io_impedance = -EINVAL;
 259
 260         return 0;
 261 }
 262 #endif
 263
 264 static int dp83867_config(struct phy_device *phydev)
 265 {
 266         struct dp83867_private *dp83867;
 267         unsigned int val, delay, cfg2;
 268         int ret, bs;
 269
 270         dp83867 = (struct dp83867_private *)phydev->priv;
 271
 272         ret = dp83867_of_init(phydev);
 273         if (ret)
 274                 return ret;
 275
 276         /* Restart the PHY.  */
 277         val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
 278         phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
 279                   val | DP83867_SW_RESTART);
 280
 281         /* Mode 1 or 2 workaround */
 282         if (dp83867->rxctrl_strap_quirk) {
 283                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 284                                    DP83867_CFG4);
 285                 val &= ~BIT(7);
 286                 phy_write_mmd(phydev, DP83867_DEVADDR,
 287                               DP83867_CFG4, val);
 288         }
 289
 290         if (phy_interface_is_rgmii(phydev)) {
 291                 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
 292                 if (val < 0)
 293                         goto err_out;
 294                 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 295                 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 296
 297                 /* Do not force link good */
 298                 val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
 299
 300                 /* The code below checks if "port mirroring" N/A MODE4 has been
 301                  * enabled during power on bootstrap.
 302                  *
 303                  * Such N/A mode enabled by mistake can put PHY IC in some
 304                  * internal testing mode and disable RGMII transmission.
 305                  *
 306                  * In this particular case one needs to check STRAP_STS1
 307                  * register's bit 11 (marked as RESERVED).
 308                  */
 309
 310                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 311                 if (bs & DP83867_STRAP_STS1_RESERVED)
 312                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 313
 314                 ret = phy_write(phydev, MDIO_DEVAD_NONE,
 315                                 MII_DP83867_PHYCTRL, val);
 316
 317                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 318                                    DP83867_RGMIICTL);
 319
 320                 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN |
 321                          DP83867_RGMII_RX_CLK_DELAY_EN);
 322                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 323                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
 324                                 DP83867_RGMII_RX_CLK_DELAY_EN);
 325
 326                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 327                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 328
 329                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 330                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 331
 332                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 333
 334                 delay = (dp83867->rx_id_delay |
 335                         (dp83867->tx_id_delay <<
 336                         DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 337
 338                 phy_write_mmd(phydev, DP83867_DEVADDR,
 339                               DP83867_RGMIIDCTL, delay);
 340         }
 341
 342         if (phy_interface_is_sgmii(phydev)) {
 343                 if (dp83867->sgmii_ref_clk_en)
 344                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL,
 345                                       DP83867_SGMII_TYPE);
 346
 347                 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 348                           (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
 349
 350                 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
 351                 cfg2 &= MII_DP83867_CFG2_MASK;
 352                 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
 353                          MII_DP83867_CFG2_SGMII_AUTONEGEN |
 354                          MII_DP83867_CFG2_SPEEDOPT_ENH |
 355                          MII_DP83867_CFG2_SPEEDOPT_CNT |
 356                          MII_DP83867_CFG2_SPEEDOPT_INTLOW);
 357                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
 358
 359                 phy_write_mmd(phydev, DP83867_DEVADDR,
 360                               DP83867_RGMIICTL, 0x0);
 361
 362                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 363                           DP83867_PHYCTRL_SGMIIEN |
 364                           (DP83867_MDI_CROSSOVER_MDIX <<
 365                           DP83867_MDI_CROSSOVER) |
 366                           (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
 367                           (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
 368                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
 369         }
 370
 371         if (dp83867->io_impedance >= 0) {
 372                 val = phy_read_mmd(phydev,
 373                                    DP83867_DEVADDR,
 374                                    DP83867_IO_MUX_CFG);
 375                 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 376                 val |= dp83867->io_impedance &
 377                        DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 378                 phy_write_mmd(phydev, DP83867_DEVADDR,
 379                               DP83867_IO_MUX_CFG, val);
 380         }
 381
 382         if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
 383                 dp83867_config_port_mirroring(phydev);
 384
 385         /* Clock output selection if muxing property is set */
 386         if (dp83867->set_clk_output) {
 387                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 388                                    DP83867_IO_MUX_CFG);
 389
 390                 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
 391                         val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 392                 } else {
 393                         val &= ~(DP83867_IO_MUX_CFG_CLK_O_SEL_MASK |
 394                                  DP83867_IO_MUX_CFG_CLK_O_DISABLE);
 395                         val |= dp83867->clk_output_sel <<
 396                                DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
 397                 }
 398                 phy_write_mmd(phydev, DP83867_DEVADDR,
 399                               DP83867_IO_MUX_CFG, val);
 400         }
 401
 402         genphy_config_aneg(phydev);
 403         return 0;
 404
 405 err_out:
 406         return ret;
 407 }
 408
 409 static int dp83867_probe(struct phy_device *phydev)
 410 {
 411         struct dp83867_private *dp83867;
 412
 413         dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
 414         if (!dp83867)
 415                 return -ENOMEM;
 416
 417         phydev->priv = dp83867;
 418         return 0;
 419 }
 420
 421 static struct phy_driver DP83867_driver = {
 422         .name = "TI DP83867",
 423         .uid = 0x2000a231,
 424         .mask = 0xfffffff0,
 425         .features = PHY_GBIT_FEATURES,
 426         .probe = dp83867_probe,
 427         .config = &dp83867_config,
 428         .startup = &genphy_startup,
 429         .shutdown = &genphy_shutdown,
 430 };
 431
 432 int phy_ti_init(void)
 433 {
 434         phy_register(&DP83867_driver);
 435         return 0;
 436 }