4 * SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2010-2011 Freescale Semiconductor, Inc.
13 /* Broadcom BCM54xx -- taken from linux sungem_phy */
14 #define MIIM_BCM54xx_AUXCNTL 0x18
15 #define MIIM_BCM54xx_AUXCNTL_ENCODE(val) (((val & 0x7) << 12)|(val & 0x7))
16 #define MIIM_BCM54xx_AUXSTATUS 0x19
17 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
18 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
20 #define MIIM_BCM54XX_SHD 0x1c
21 #define MIIM_BCM54XX_SHD_WRITE 0x8000
22 #define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
23 #define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
24 #define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \
25 (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \
26 MIIM_BCM54XX_SHD_DATA(data))
28 #define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
29 #define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
30 #define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
31 #define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
33 #define MIIM_BCM_AUXCNTL_SHDWSEL_MISC 0x0007
34 #define MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN 0x0800
36 #define MIIM_BCM_CHANNEL_WIDTH 0x2000
38 static void bcm_phy_write_misc(struct phy_device *phydev,
39 u16 reg, u16 chl, u16 value)
43 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL,
44 MIIM_BCM_AUXCNTL_SHDWSEL_MISC);
46 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL);
47 reg_val |= MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN;
48 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val);
50 reg_val = (chl * MIIM_BCM_CHANNEL_WIDTH) | reg;
51 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val);
53 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value);
56 /* Broadcom BCM5461S */
57 static int bcm5461_config(struct phy_device *phydev)
59 genphy_config_aneg(phydev);
66 static int bcm54xx_parse_status(struct phy_device *phydev)
70 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS);
72 switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
73 MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {
75 phydev->duplex = DUPLEX_HALF;
76 phydev->speed = SPEED_10;
79 phydev->duplex = DUPLEX_FULL;
80 phydev->speed = SPEED_10;
83 phydev->duplex = DUPLEX_HALF;
84 phydev->speed = SPEED_100;
87 phydev->duplex = DUPLEX_FULL;
88 phydev->speed = SPEED_100;
91 phydev->duplex = DUPLEX_HALF;
92 phydev->speed = SPEED_1000;
95 phydev->duplex = DUPLEX_FULL;
96 phydev->speed = SPEED_1000;
99 printf("Auto-neg error, defaulting to 10BT/HD\n");
100 phydev->duplex = DUPLEX_HALF;
101 phydev->speed = SPEED_10;
108 static int bcm54xx_startup(struct phy_device *phydev)
112 /* Read the Status (2x to make sure link is right) */
113 ret = genphy_update_link(phydev);
117 return bcm54xx_parse_status(phydev);
120 /* Broadcom BCM5482S */
122 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
123 * circumstances. eg a gigabit TSEC connected to a gigabit switch with
124 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't
125 * link. "Ethernet@Wirespeed" reduces advertised speed until link
128 static u32 bcm5482_read_wirespeed(struct phy_device *phydev, u32 reg)
130 return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010;
133 static int bcm5482_config(struct phy_device *phydev)
138 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
140 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
142 /* Setup read from auxilary control shadow register 7 */
143 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL,
144 MIIM_BCM54xx_AUXCNTL_ENCODE(7));
145 /* Read Misc Control register and or in Ethernet@Wirespeed */
146 reg = bcm5482_read_wirespeed(phydev, MIIM_BCM54xx_AUXCNTL);
147 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg);
149 /* Initial config/enable of secondary SerDes interface */
150 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD,
151 MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf));
152 /* Write intial value to secondary SerDes Contol */
153 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
154 MIIM_BCM54XX_EXP_SEL_SSD | 0);
155 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA,
157 /* Enable copper/fiber auto-detect */
158 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD,
159 MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201));
161 genphy_config_aneg(phydev);
166 static int bcm_cygnus_startup(struct phy_device *phydev)
170 /* Read the Status (2x to make sure link is right) */
171 ret = genphy_update_link(phydev);
175 return genphy_parse_link(phydev);
178 static void bcm_cygnus_afe(struct phy_device *phydev)
180 /* ensures smdspclk is enabled */
181 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, 0x0c30);
183 /* AFE_VDAC_ICTRL_0 bit 7:4 Iq=1100 for 1g 10bt, normal modes */
184 bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8);
186 /* AFE_HPF_TRIM_OTHERS bit11=1, short cascode for all modes*/
187 bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803);
189 /* AFE_TX_CONFIG_1 bit 7:4 Iq=1100 for test modes */
190 bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740);
192 /* AFE TEMPSEN_OTHERS rcal_HT, rcal_LT 10000 */
193 bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400);
195 /* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */
196 bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004);
198 /* Adjust bias current trim to overcome digital offSet */
199 phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x02);
201 /* make rcal=100, since rdb default is 000 */
202 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B1);
203 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010);
205 /* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */
206 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0);
207 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010);
209 /* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */
210 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0);
211 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0000);
214 static int bcm_cygnus_config(struct phy_device *phydev)
216 genphy_config_aneg(phydev);
218 /* AFE settings for PHY stability */
219 bcm_cygnus_afe(phydev);
220 /* Forcing aneg after applying the AFE settings */
221 genphy_restart_aneg(phydev);
227 * Find out if PHY is in copper or serdes mode by looking at Expansion Reg
228 * 0x42 - "Operating Mode Status Register"
230 static int bcm5482_is_serdes(struct phy_device *phydev)
235 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
236 MIIM_BCM54XX_EXP_SEL_ER | 0x42);
237 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA);
239 switch (val & 0x1f) {
240 case 0x0d: /* RGMII-to-100Base-FX */
241 case 0x0e: /* RGMII-to-SGMII */
242 case 0x0f: /* RGMII-to-SerDes */
243 case 0x12: /* SGMII-to-SerDes */
244 case 0x13: /* SGMII-to-100Base-FX */
245 case 0x16: /* SerDes-to-Serdes */
248 case 0x6: /* RGMII-to-Copper */
249 case 0x14: /* SGMII-to-Copper */
250 case 0x17: /* SerDes-to-Copper */
253 printf("ERROR, invalid PHY mode (0x%x\n)", val);
261 * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating
262 * Mode Status Register"
264 static u32 bcm5482_parse_serdes_sr(struct phy_device *phydev)
269 /* Wait 1s for link - Clause 37 autonegotiation happens very fast */
271 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
272 MIIM_BCM54XX_EXP_SEL_ER | 0x42);
273 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA);
283 udelay(1000); /* 1 ms */
287 switch ((val >> 13) & 0x3) {
295 phydev->speed = 1000;
299 phydev->duplex = (val & 0x1000) == 0x1000;
305 * Figure out if BCM5482 is in serdes or copper mode and determine link
306 * configuration accordingly
308 static int bcm5482_startup(struct phy_device *phydev)
312 if (bcm5482_is_serdes(phydev)) {
313 bcm5482_parse_serdes_sr(phydev);
314 phydev->port = PORT_FIBRE;
318 /* Wait for auto-negotiation to complete or fail */
319 ret = genphy_update_link(phydev);
323 /* Parse BCM54xx copper aux status register */
324 return bcm54xx_parse_status(phydev);
327 static struct phy_driver BCM5461S_driver = {
328 .name = "Broadcom BCM5461S",
331 .features = PHY_GBIT_FEATURES,
332 .config = &bcm5461_config,
333 .startup = &bcm54xx_startup,
334 .shutdown = &genphy_shutdown,
337 static struct phy_driver BCM5464S_driver = {
338 .name = "Broadcom BCM5464S",
341 .features = PHY_GBIT_FEATURES,
342 .config = &bcm5461_config,
343 .startup = &bcm54xx_startup,
344 .shutdown = &genphy_shutdown,
347 static struct phy_driver BCM5482S_driver = {
348 .name = "Broadcom BCM5482S",
351 .features = PHY_GBIT_FEATURES,
352 .config = &bcm5482_config,
353 .startup = &bcm5482_startup,
354 .shutdown = &genphy_shutdown,
357 static struct phy_driver BCM_CYGNUS_driver = {
358 .name = "Broadcom CYGNUS GPHY",
361 .features = PHY_GBIT_FEATURES,
362 .config = &bcm_cygnus_config,
363 .startup = &bcm_cygnus_startup,
364 .shutdown = &genphy_shutdown,
367 int phy_broadcom_init(void)
369 phy_register(&BCM5482S_driver);
370 phy_register(&BCM5464S_driver);
371 phy_register(&BCM5461S_driver);
372 phy_register(&BCM_CYGNUS_driver);