drivers/net/phy/aquantia.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Aquantia PHY drivers
   4  *
   5  * Copyright 2014 Freescale Semiconductor, Inc.
   6  * Copyright 2018 NXP
   7  */
   8 #include <config.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <net.h>
  12 #include <phy.h>
  13 #include <u-boot/crc.h>
  14 #include <malloc.h>
  15 #include <asm/byteorder.h>
  16 #include <fs.h>
  17
  18 #define AQUNTIA_10G_CTL         0x20
  19 #define AQUNTIA_VENDOR_P1       0xc400
  20
  21 #define AQUNTIA_SPEED_LSB_MASK  0x2000
  22 #define AQUNTIA_SPEED_MSB_MASK  0x40
  23
  24 #define AQUANTIA_SYSTEM_INTERFACE_SR     0xe812
  25 #define  AQUANTIA_SYSTEM_INTERFACE_SR_READY     BIT(0)
  26 #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
  27 #define AQUANTIA_FIRMWARE_ID             0x20
  28 #define AQUANTIA_RESERVED_STATUS         0xc885
  29 #define AQUANTIA_FIRMWARE_MAJOR_MASK     0xff00
  30 #define AQUANTIA_FIRMWARE_MINOR_MASK     0xff
  31 #define AQUANTIA_FIRMWARE_BUILD_MASK     0xf0
  32
  33 #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
  34 #define AQUANTIA_SI_IN_USE_MASK          0x0078
  35 #define AQUANTIA_SI_USXGMII              0x0018
  36
  37 /* registers in MDIO_MMD_VEND1 region */
  38 #define AQUANTIA_VND1_GLOBAL_SC                 0x000
  39 #define  AQUANTIA_VND1_GLOBAL_SC_LP             BIT(0xb)
  40
  41 #define GLOBAL_FIRMWARE_ID 0x20
  42 #define GLOBAL_FAULT 0xc850
  43 #define GLOBAL_RSTATUS_1 0xc885
  44
  45 #define GLOBAL_ALARM_1 0xcc00
  46 #define SYSTEM_READY_BIT 0x40
  47
  48 #define GLOBAL_STANDARD_CONTROL 0x0
  49 #define SOFT_RESET BIT(15)
  50 #define LOW_POWER BIT(11)
  51
  52 #define MAILBOX_CONTROL 0x0200
  53 #define MAILBOX_EXECUTE BIT(15)
  54 #define MAILBOX_WRITE BIT(14)
  55 #define MAILBOX_RESET_CRC BIT(12)
  56 #define MAILBOX_BUSY BIT(8)
  57
  58 #define MAILBOX_CRC 0x0201
  59
  60 #define MAILBOX_ADDR_MSW 0x0202
  61 #define MAILBOX_ADDR_LSW 0x0203
  62
  63 #define MAILBOX_DATA_MSW 0x0204
  64 #define MAILBOX_DATA_LSW 0x0205
  65
  66 #define UP_CONTROL 0xc001
  67 #define UP_RESET BIT(15)
  68 #define UP_RUN_STALL_OVERRIDE BIT(6)
  69 #define UP_RUN_STALL BIT(0)
  70
  71 #define AQUANTIA_PMA_RX_VENDOR_P1               0xe400
  72 #define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK      GENMASK(1, 0)
  73 /* MDI reversal configured through registers */
  74 #define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG      BIT(1)
  75 /* MDI reversal enabled */
  76 #define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV      BIT(0)
  77
  78 /*
  79  * global start rate, the protocol associated with this speed is used by default
  80  * on SI.
  81  */
  82 #define AQUANTIA_VND1_GSTART_RATE               0x31a
  83 #define  AQUANTIA_VND1_GSTART_RATE_OFF          0
  84 #define  AQUANTIA_VND1_GSTART_RATE_100M         1
  85 #define  AQUANTIA_VND1_GSTART_RATE_1G           2
  86 #define  AQUANTIA_VND1_GSTART_RATE_10G          3
  87 #define  AQUANTIA_VND1_GSTART_RATE_2_5G         4
  88 #define  AQUANTIA_VND1_GSTART_RATE_5G           5
  89
  90 /* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
  91 #define AQUANTIA_VND1_GSYSCFG_BASE              0x31b
  92 #define AQUANTIA_VND1_GSYSCFG_100M              0
  93 #define AQUANTIA_VND1_GSYSCFG_1G                1
  94 #define AQUANTIA_VND1_GSYSCFG_2_5G              2
  95 #define AQUANTIA_VND1_GSYSCFG_5G                3
  96 #define AQUANTIA_VND1_GSYSCFG_10G               4
  97
  98 #define AQUANTIA_VND1_SMBUS0                    0xc485
  99 #define AQUANTIA_VND1_SMBUS1                    0xc495
 100
 101 /* addresses of memory segments in the phy */
 102 #define DRAM_BASE_ADDR 0x3FFE0000
 103 #define IRAM_BASE_ADDR 0x40000000
 104
 105 /* firmware image format constants */
 106 #define VERSION_STRING_SIZE 0x40
 107 #define VERSION_STRING_OFFSET 0x0200
 108 #define HEADER_OFFSET 0x300
 109
 110 /* driver private data */
 111 #define AQUANTIA_NA             0
 112 #define AQUANTIA_GEN1           1
 113 #define AQUANTIA_GEN2           2
 114 #define AQUANTIA_GEN3           3
 115
 116 #pragma pack(1)
 117 struct fw_header {
 118         u8 padding[4];
 119         u8 iram_offset[3];
 120         u8 iram_size[3];
 121         u8 dram_offset[3];
 122         u8 dram_size[3];
 123 };
 124
 125 #pragma pack()
 126
 127 #if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW)
 128 static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
 129 {
 130         loff_t length, read;
 131         int ret;
 132         void *addr = NULL;
 133
 134         *fw_addr = NULL;
 135         *fw_length = 0;
 136         debug("Loading Acquantia microcode from %s %s\n",
 137               CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME);
 138         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
 139         if (ret < 0)
 140                 goto cleanup;
 141
 142         ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length);
 143         if (ret < 0)
 144                 goto cleanup;
 145
 146         addr = malloc(length);
 147         if (!addr) {
 148                 ret = -ENOMEM;
 149                 goto cleanup;
 150         }
 151
 152         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
 153         if (ret < 0)
 154                 goto cleanup;
 155
 156         ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,
 157                       &read);
 158         if (ret < 0)
 159                 goto cleanup;
 160
 161         *fw_addr = addr;
 162         *fw_length = length;
 163         debug("Found Acquantia microcode.\n");
 164
 165 cleanup:
 166         if (ret < 0) {
 167                 printf("loading firmware file %s %s failed with error %d\n",
 168                        CONFIG_PHY_AQUANTIA_FW_PART,
 169                        CONFIG_PHY_AQUANTIA_FW_NAME, ret);
 170                 free(addr);
 171         }
 172         return ret;
 173 }
 174
 175 /* load data into the phy's memory */
 176 static int aquantia_load_memory(struct phy_device *phydev, u32 addr,
 177                                 const u8 *data, size_t len)
 178 {
 179         size_t pos;
 180         u16 crc = 0, up_crc;
 181
 182         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC);
 183         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16);
 184         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);
 185
 186         for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {
 187                 u32 word = 0;
 188
 189                 memcpy(&word, &data[pos], min(sizeof(u32), len - pos));
 190
 191                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW,
 192                           (word >> 16));
 193                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW,
 194                           word & 0xffff);
 195
 196                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL,
 197                           MAILBOX_EXECUTE | MAILBOX_WRITE);
 198
 199                 /* keep a big endian CRC to match the phy processor */
 200                 word = cpu_to_be32(word);
 201                 crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word));
 202         }
 203
 204         up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC);
 205         if (crc != up_crc) {
 206                 printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",
 207                        phydev->dev->name, crc, up_crc);
 208                 return -EINVAL;
 209         }
 210         return 0;
 211 }
 212
 213 static u32 unpack_u24(const u8 *data)
 214 {
 215         return (data[2] << 16) + (data[1] << 8) + data[0];
 216 }
 217
 218 static int aquantia_upload_firmware(struct phy_device *phydev)
 219 {
 220         int ret;
 221         u8 *addr = NULL;
 222         size_t fw_length = 0;
 223         u16 calculated_crc, read_crc;
 224         char version[VERSION_STRING_SIZE];
 225         u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size;
 226         const struct fw_header *header;
 227
 228         ret = aquantia_read_fw(&addr, &fw_length);
 229         if (ret != 0)
 230                 return ret;
 231
 232         read_crc = (addr[fw_length - 2] << 8)  | addr[fw_length - 1];
 233         calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
 234         if (read_crc != calculated_crc) {
 235                 printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
 236                        phydev->dev->name, read_crc, calculated_crc);
 237                 ret = -EINVAL;
 238                 goto done;
 239         }
 240
 241         /* Find the DRAM and IRAM sections within the firmware file. */
 242         primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;
 243
 244         header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET];
 245
 246         iram_offset = primary_offset + unpack_u24(header->iram_offset);
 247         iram_size = unpack_u24(header->iram_size);
 248
 249         dram_offset = primary_offset + unpack_u24(header->dram_offset);
 250         dram_size = unpack_u24(header->dram_size);
 251
 252         debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n",
 253               primary_offset, iram_offset, iram_size, dram_offset, dram_size);
 254
 255         strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
 256                 VERSION_STRING_SIZE);
 257         printf("%s loading firmare version '%s'\n", phydev->dev->name, version);
 258
 259         /* stall the microcprocessor */
 260         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 261                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
 262
 263         debug("loading dram 0x%08x from offset=%d size=%d\n",
 264               DRAM_BASE_ADDR, dram_offset, dram_size);
 265         ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
 266                                    dram_size);
 267         if (ret != 0)
 268                 goto done;
 269
 270         debug("loading iram 0x%08x from offset=%d size=%d\n",
 271               IRAM_BASE_ADDR, iram_offset, iram_size);
 272         ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
 273                                    iram_size);
 274         if (ret != 0)
 275                 goto done;
 276
 277         /* make sure soft reset and low power mode are clear */
 278         phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);
 279
 280         /* Release the microprocessor. UP_RESET must be held for 100 usec. */
 281         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 282                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET);
 283
 284         udelay(100);
 285
 286         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE);
 287
 288         printf("%s firmare loading done.\n", phydev->dev->name);
 289 done:
 290         free(addr);
 291         return ret;
 292 }
 293 #else
 294 static int aquantia_upload_firmware(struct phy_device *phydev)
 295 {
 296         printf("ERROR %s firmware loading disabled.\n", phydev->dev->name);
 297         return -1;
 298 }
 299 #endif
 300
 301 struct {
 302         u16 syscfg;
 303         int cnt;
 304         u16 start_rate;
 305 } aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = {
 306         [PHY_INTERFACE_MODE_SGMII] =      {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
 307                                            AQUANTIA_VND1_GSTART_RATE_1G},
 308         [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
 309                                            AQUANTIA_VND1_GSTART_RATE_2_5G},
 310         [PHY_INTERFACE_MODE_XFI] =        {0x100, AQUANTIA_VND1_GSYSCFG_10G,
 311                                            AQUANTIA_VND1_GSTART_RATE_10G},
 312         [PHY_INTERFACE_MODE_USXGMII] =    {0x080, AQUANTIA_VND1_GSYSCFG_10G,
 313                                            AQUANTIA_VND1_GSTART_RATE_10G},
 314 };
 315
 316 static int aquantia_set_proto(struct phy_device *phydev,
 317                               phy_interface_t interface)
 318 {
 319         int i;
 320
 321         if (!aquantia_syscfg[interface].cnt)
 322                 return 0;
 323
 324         /* set the default rate to enable the SI link */
 325         phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
 326                   aquantia_syscfg[interface].start_rate);
 327
 328         /* set selected protocol for all relevant line side link speeds */
 329         for (i = 0; i <= aquantia_syscfg[interface].cnt; i++)
 330                 phy_write(phydev, MDIO_MMD_VEND1,
 331                           AQUANTIA_VND1_GSYSCFG_BASE + i,
 332                           aquantia_syscfg[interface].syscfg);
 333         return 0;
 334 }
 335
 336 static int aquantia_dts_config(struct phy_device *phydev)
 337 {
 338 #ifdef CONFIG_DM_ETH
 339         ofnode node = phydev->node;
 340         u32 prop;
 341         u16 reg;
 342
 343         /* this code only works on gen2 and gen3 PHYs */
 344         if (phydev->drv->data != AQUANTIA_GEN2 &&
 345             phydev->drv->data != AQUANTIA_GEN3)
 346                 return -ENOTSUPP;
 347
 348         if (!ofnode_valid(node))
 349                 return 0;
 350
 351         if (!ofnode_read_u32(node, "mdi-reversal", &prop)) {
 352                 debug("mdi-reversal = %d\n", (int)prop);
 353                 reg =  phy_read(phydev, MDIO_MMD_PMAPMD,
 354                                 AQUANTIA_PMA_RX_VENDOR_P1);
 355                 reg &= ~AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK;
 356                 reg |= AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG;
 357                 reg |= prop ? AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV : 0;
 358                 phy_write(phydev, MDIO_MMD_PMAPMD, AQUANTIA_PMA_RX_VENDOR_P1,
 359                           reg);
 360         }
 361         if (!ofnode_read_u32(node, "smb-addr", &prop)) {
 362                 debug("smb-addr = %x\n", (int)prop);
 363                 /*
 364                  * there are two addresses here, normally just one bus would
 365                  * be in use so we're setting both regs using the same DT
 366                  * property.
 367                  */
 368                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS0,
 369                           (u16)(prop << 1));
 370                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS1,
 371                           (u16)(prop << 1));
 372         }
 373
 374 #endif
 375         return 0;
 376 }
 377
 378 static bool aquantia_link_is_up(struct phy_device *phydev)
 379 {
 380         u16 reg, regmask;
 381         int devad, regnum;
 382
 383         /*
 384          * On Gen 2 and 3 we have a bit that indicates that both system and
 385          * line side are ready for data, use that if possible.
 386          */
 387         if (phydev->drv->data == AQUANTIA_GEN2 ||
 388             phydev->drv->data == AQUANTIA_GEN3) {
 389                 devad = MDIO_MMD_PHYXS;
 390                 regnum = AQUANTIA_SYSTEM_INTERFACE_SR;
 391                 regmask = AQUANTIA_SYSTEM_INTERFACE_SR_READY;
 392         } else {
 393                 devad = MDIO_MMD_AN;
 394                 regnum = MDIO_STAT1;
 395                 regmask = MDIO_AN_STAT1_COMPLETE;
 396         }
 397         /* the register should be latched, do a double read */
 398         phy_read(phydev, devad, regnum);
 399         reg = phy_read(phydev, devad, regnum);
 400
 401         return !!(reg & regmask);
 402 }
 403
 404 int aquantia_config(struct phy_device *phydev)
 405 {
 406         int interface = phydev->interface;
 407         u32 val, id, rstatus, fault;
 408         u32 reg_val1 = 0;
 409         int num_retries = 5;
 410         int usx_an = 0;
 411
 412         /*
 413          * check if the system is out of reset and init sequence completed.
 414          * chip-wide reset for gen1 quad phys takes longer
 415          */
 416         while (--num_retries) {
 417                 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1);
 418                 if (rstatus & SYSTEM_READY_BIT)
 419                         break;
 420                 mdelay(10);
 421         }
 422
 423         id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
 424         rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
 425         fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT);
 426
 427         if (id != 0)
 428                 debug("%s running firmware version %X.%X.%X\n",
 429                       phydev->dev->name, (id >> 8), id & 0xff,
 430                       (rstatus >> 4) & 0xf);
 431
 432         if (fault != 0)
 433                 printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);
 434
 435         if (id == 0 || fault != 0) {
 436                 int ret;
 437
 438                 ret = aquantia_upload_firmware(phydev);
 439                 if (ret != 0)
 440                         return ret;
 441         }
 442         /*
 443          * for backward compatibility convert XGMII into either XFI or USX based
 444          * on FW config
 445          */
 446         if (interface == PHY_INTERFACE_MODE_XGMII) {
 447                 debug("use XFI or USXGMII SI protos, XGMII is not valid\n");
 448
 449                 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
 450                                     AQUANTIA_SYSTEM_INTERFACE_SR);
 451                 if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
 452                         interface = PHY_INTERFACE_MODE_USXGMII;
 453                 else
 454                         interface = PHY_INTERFACE_MODE_XFI;
 455         }
 456
 457         /*
 458          * if link is up already we can just use it, otherwise configure
 459          * the protocols in the PHY.  If link is down set the system
 460          * interface protocol to use based on phydev->interface
 461          */
 462         if (!aquantia_link_is_up(phydev) &&
 463             (phydev->drv->data == AQUANTIA_GEN2 ||
 464              phydev->drv->data == AQUANTIA_GEN3)) {
 465                 /* set PHY in low power mode so we can configure protocols */
 466                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,
 467                           AQUANTIA_VND1_GLOBAL_SC_LP);
 468                 mdelay(10);
 469
 470                 /* configure protocol based on phydev->interface */
 471                 aquantia_set_proto(phydev, interface);
 472                 /* apply custom configuration based on DT */
 473                 aquantia_dts_config(phydev);
 474
 475                 /* wake PHY back up */
 476                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
 477                 mdelay(10);
 478         }
 479
 480         val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 481
 482         switch (interface) {
 483         case PHY_INTERFACE_MODE_SGMII:
 484                 /* 1000BASE-T mode */
 485                 phydev->advertising = SUPPORTED_1000baseT_Full;
 486                 phydev->supported = phydev->advertising;
 487
 488                 val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
 489                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 490                 break;
 491         case PHY_INTERFACE_MODE_USXGMII:
 492                 usx_an = 1;
 493                 /* FALLTHROUGH */
 494         case PHY_INTERFACE_MODE_XFI:
 495                 /* 10GBASE-T mode */
 496                 phydev->advertising = SUPPORTED_10000baseT_Full;
 497                 phydev->supported = phydev->advertising;
 498
 499                 if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
 500                     !(val & AQUNTIA_SPEED_MSB_MASK))
 501                         phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
 502                                   AQUNTIA_SPEED_LSB_MASK |
 503                                   AQUNTIA_SPEED_MSB_MASK);
 504
 505                 /* If SI is USXGMII then start USXGMII autoneg */
 506                 reg_val1 =  phy_read(phydev, MDIO_MMD_PHYXS,
 507                                      AQUANTIA_VENDOR_PROVISIONING_REG);
 508
 509                 if (usx_an) {
 510                         reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
 511                         debug("%s: system interface USXGMII\n",
 512                               phydev->dev->name);
 513                 } else {
 514                         reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
 515                         debug("%s: system interface XFI\n",
 516                               phydev->dev->name);
 517                 }
 518
 519                 phy_write(phydev, MDIO_MMD_PHYXS,
 520                           AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
 521                 break;
 522         case PHY_INTERFACE_MODE_SGMII_2500:
 523                 /* 2.5GBASE-T mode */
 524                 phydev->advertising = SUPPORTED_1000baseT_Full;
 525                 phydev->supported = phydev->advertising;
 526
 527                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
 528                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
 529                 break;
 530         case PHY_INTERFACE_MODE_MII:
 531                 /* 100BASE-TX mode */
 532                 phydev->advertising = SUPPORTED_100baseT_Full;
 533                 phydev->supported = phydev->advertising;
 534
 535                 val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
 536                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 537                 break;
 538         };
 539
 540         val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
 541         reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
 542
 543         debug("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
 544               phydev->drv->name,
 545               (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
 546               reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
 547               (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
 548
 549         return 0;
 550 }
 551
 552 int aquantia_startup(struct phy_device *phydev)
 553 {
 554         u32 reg, speed;
 555         int i = 0;
 556
 557         phydev->duplex = DUPLEX_FULL;
 558
 559         /* if the AN is still in progress, wait till timeout. */
 560         if (!aquantia_link_is_up(phydev)) {
 561                 printf("%s Waiting for PHY auto negotiation to complete",
 562                        phydev->dev->name);
 563                 do {
 564                         udelay(1000);
 565                         if ((i++ % 500) == 0)
 566                                 printf(".");
 567                 } while (!aquantia_link_is_up(phydev) &&
 568                          i < (4 * PHY_ANEG_TIMEOUT));
 569
 570                 if (i > PHY_ANEG_TIMEOUT)
 571                         printf(" TIMEOUT !\n");
 572         }
 573
 574         /* Read twice because link state is latched and a
 575          * read moves the current state into the register */
 576         phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 577         reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 578         if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
 579                 phydev->link = 0;
 580         else
 581                 phydev->link = 1;
 582
 583         speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 584         if (speed & AQUNTIA_SPEED_MSB_MASK) {
 585                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 586                         phydev->speed = SPEED_10000;
 587                 else
 588                         phydev->speed = SPEED_1000;
 589         } else {
 590                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 591                         phydev->speed = SPEED_100;
 592                 else
 593                         phydev->speed = SPEED_10;
 594         }
 595
 596         return 0;
 597 }
 598
 599 struct phy_driver aq1202_driver = {
 600         .name = "Aquantia AQ1202",
 601         .uid = 0x3a1b445,
 602         .mask = 0xfffffff0,
 603         .features = PHY_10G_FEATURES,
 604         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 605                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 606                         MDIO_MMD_VEND1),
 607         .config = &aquantia_config,
 608         .startup = &aquantia_startup,
 609         .shutdown = &gen10g_shutdown,
 610 };
 611
 612 struct phy_driver aq2104_driver = {
 613         .name = "Aquantia AQ2104",
 614         .uid = 0x3a1b460,
 615         .mask = 0xfffffff0,
 616         .features = PHY_10G_FEATURES,
 617         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 618                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 619                         MDIO_MMD_VEND1),
 620         .config = &aquantia_config,
 621         .startup = &aquantia_startup,
 622         .shutdown = &gen10g_shutdown,
 623 };
 624
 625 struct phy_driver aqr105_driver = {
 626         .name = "Aquantia AQR105",
 627         .uid = 0x3a1b4a2,
 628         .mask = 0xfffffff0,
 629         .features = PHY_10G_FEATURES,
 630         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 631                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 632                         MDIO_MMD_VEND1),
 633         .config = &aquantia_config,
 634         .startup = &aquantia_startup,
 635         .shutdown = &gen10g_shutdown,
 636         .data = AQUANTIA_GEN1,
 637 };
 638
 639 struct phy_driver aqr106_driver = {
 640         .name = "Aquantia AQR106",
 641         .uid = 0x3a1b4d0,
 642         .mask = 0xfffffff0,
 643         .features = PHY_10G_FEATURES,
 644         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 645                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 646                         MDIO_MMD_VEND1),
 647         .config = &aquantia_config,
 648         .startup = &aquantia_startup,
 649         .shutdown = &gen10g_shutdown,
 650 };
 651
 652 struct phy_driver aqr107_driver = {
 653         .name = "Aquantia AQR107",
 654         .uid = 0x3a1b4e0,
 655         .mask = 0xfffffff0,
 656         .features = PHY_10G_FEATURES,
 657         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 658                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 659                         MDIO_MMD_VEND1),
 660         .config = &aquantia_config,
 661         .startup = &aquantia_startup,
 662         .shutdown = &gen10g_shutdown,
 663         .data = AQUANTIA_GEN2,
 664 };
 665
 666 struct phy_driver aqr112_driver = {
 667         .name = "Aquantia AQR112",
 668         .uid = 0x3a1b660,
 669         .mask = 0xfffffff0,
 670         .features = PHY_10G_FEATURES,
 671         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 672                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 673                  MDIO_MMD_VEND1),
 674         .config = &aquantia_config,
 675         .startup = &aquantia_startup,
 676         .shutdown = &gen10g_shutdown,
 677         .data = AQUANTIA_GEN3,
 678 };
 679
 680 struct phy_driver aqr405_driver = {
 681         .name = "Aquantia AQR405",
 682         .uid = 0x3a1b4b2,
 683         .mask = 0xfffffff0,
 684         .features = PHY_10G_FEATURES,
 685         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 686                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 687                  MDIO_MMD_VEND1),
 688         .config = &aquantia_config,
 689         .startup = &aquantia_startup,
 690         .shutdown = &gen10g_shutdown,
 691         .data = AQUANTIA_GEN1,
 692 };
 693
 694 struct phy_driver aqr412_driver = {
 695         .name = "Aquantia AQR412",
 696         .uid = 0x3a1b710,
 697         .mask = 0xfffffff0,
 698         .features = PHY_10G_FEATURES,
 699         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 700                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 701                  MDIO_MMD_VEND1),
 702         .config = &aquantia_config,
 703         .startup = &aquantia_startup,
 704         .shutdown = &gen10g_shutdown,
 705         .data = AQUANTIA_GEN3,
 706 };
 707
 708 int phy_aquantia_init(void)
 709 {
 710         phy_register(&aq1202_driver);
 711         phy_register(&aq2104_driver);
 712         phy_register(&aqr105_driver);
 713         phy_register(&aqr106_driver);
 714         phy_register(&aqr107_driver);
 715         phy_register(&aqr112_driver);
 716         phy_register(&aqr405_driver);
 717         phy_register(&aqr412_driver);
 718
 719         return 0;
 720 }