1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2014 Freescale Semiconductor, Inc.
13 #include <asm/byteorder.h>
16 #define AQUNTIA_10G_CTL 0x20
17 #define AQUNTIA_VENDOR_P1 0xc400
19 #define AQUNTIA_SPEED_LSB_MASK 0x2000
20 #define AQUNTIA_SPEED_MSB_MASK 0x40
22 /* registers in MDIO_MMD_VEND1 region */
23 #define GLOBAL_FIRMWARE_ID 0x20
24 #define GLOBAL_FAULT 0xc850
25 #define GLOBAL_RSTATUS_1 0xc885
27 #define GLOBAL_STANDARD_CONTROL 0x0
28 #define SOFT_RESET BIT(15)
29 #define LOW_POWER BIT(11)
31 #define MAILBOX_CONTROL 0x0200
32 #define MAILBOX_EXECUTE BIT(15)
33 #define MAILBOX_WRITE BIT(14)
34 #define MAILBOX_RESET_CRC BIT(12)
35 #define MAILBOX_BUSY BIT(8)
37 #define MAILBOX_CRC 0x0201
39 #define MAILBOX_ADDR_MSW 0x0202
40 #define MAILBOX_ADDR_LSW 0x0203
42 #define MAILBOX_DATA_MSW 0x0204
43 #define MAILBOX_DATA_LSW 0x0205
45 #define UP_CONTROL 0xc001
46 #define UP_RESET BIT(15)
47 #define UP_RUN_STALL_OVERRIDE BIT(6)
48 #define UP_RUN_STALL BIT(0)
50 /* addresses of memory segments in the phy */
51 #define DRAM_BASE_ADDR 0x3FFE0000
52 #define IRAM_BASE_ADDR 0x40000000
54 /* firmware image format constants */
55 #define VERSION_STRING_SIZE 0x40
56 #define VERSION_STRING_OFFSET 0x0200
57 #define HEADER_OFFSET 0x300
70 #if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW)
71 static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
79 debug("Loading Acquantia microcode from %s %s\n",
80 CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME);
81 ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
85 ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length);
89 addr = malloc(length);
95 ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
99 ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,
106 debug("Found Acquantia microcode.\n");
110 printf("loading firmware file %s %s failed with error %d\n",
111 CONFIG_PHY_AQUANTIA_FW_PART,
112 CONFIG_PHY_AQUANTIA_FW_NAME, ret);
118 /* load data into the phy's memory */
119 static int aquantia_load_memory(struct phy_device *phydev, u32 addr,
120 const u8 *data, size_t len)
125 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC);
126 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16);
127 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);
129 for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {
132 memcpy(&word, &data[pos], min(sizeof(u32), len - pos));
134 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW,
136 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW,
139 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL,
140 MAILBOX_EXECUTE | MAILBOX_WRITE);
142 /* keep a big endian CRC to match the phy processor */
143 word = cpu_to_be32(word);
144 crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word));
147 up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC);
149 printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",
150 phydev->dev->name, crc, up_crc);
156 static u32 unpack_u24(const u8 *data)
158 return (data[2] << 16) + (data[1] << 8) + data[0];
161 static int aquantia_upload_firmware(struct phy_device *phydev)
165 size_t fw_length = 0;
166 u16 calculated_crc, read_crc;
167 char version[VERSION_STRING_SIZE];
168 u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size;
169 const struct fw_header *header;
171 ret = aquantia_read_fw(&addr, &fw_length);
175 read_crc = (addr[fw_length - 2] << 8) | addr[fw_length - 1];
176 calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
177 if (read_crc != calculated_crc) {
178 printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
179 phydev->dev->name, read_crc, calculated_crc);
184 /* Find the DRAM and IRAM sections within the firmware file. */
185 primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;
187 header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET];
189 iram_offset = primary_offset + unpack_u24(header->iram_offset);
190 iram_size = unpack_u24(header->iram_size);
192 dram_offset = primary_offset + unpack_u24(header->dram_offset);
193 dram_size = unpack_u24(header->dram_size);
195 debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n",
196 primary_offset, iram_offset, iram_size, dram_offset, dram_size);
198 strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
199 VERSION_STRING_SIZE);
200 printf("%s loading firmare version '%s'\n", phydev->dev->name, version);
202 /* stall the microcprocessor */
203 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
204 UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
206 debug("loading dram 0x%08x from offset=%d size=%d\n",
207 DRAM_BASE_ADDR, dram_offset, dram_size);
208 ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
213 debug("loading iram 0x%08x from offset=%d size=%d\n",
214 IRAM_BASE_ADDR, iram_offset, iram_size);
215 ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
220 /* make sure soft reset and low power mode are clear */
221 phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);
223 /* Release the microprocessor. UP_RESET must be held for 100 usec. */
224 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
225 UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET);
229 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE);
231 printf("%s firmare loading done.\n", phydev->dev->name);
237 static int aquantia_upload_firmware(struct phy_device *phydev)
243 int aquantia_config(struct phy_device *phydev)
248 ret = aquantia_upload_firmware(phydev);
252 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
254 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
255 /* 1000BASE-T mode */
256 phydev->advertising = SUPPORTED_1000baseT_Full;
257 phydev->supported = phydev->advertising;
259 val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
260 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
261 } else if (phydev->interface == PHY_INTERFACE_MODE_XGMII) {
263 phydev->advertising = SUPPORTED_10000baseT_Full;
264 phydev->supported = phydev->advertising;
266 if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
267 !(val & AQUNTIA_SPEED_MSB_MASK))
268 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
269 AQUNTIA_SPEED_LSB_MASK |
270 AQUNTIA_SPEED_MSB_MASK);
271 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) {
272 /* 2.5GBASE-T mode */
273 phydev->advertising = SUPPORTED_1000baseT_Full;
274 phydev->supported = phydev->advertising;
276 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
277 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
278 } else if (phydev->interface == PHY_INTERFACE_MODE_MII) {
279 /* 100BASE-TX mode */
280 phydev->advertising = SUPPORTED_100baseT_Full;
281 phydev->supported = phydev->advertising;
283 val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
284 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
289 int aquantia_startup(struct phy_device *phydev)
294 phydev->duplex = DUPLEX_FULL;
296 /* if the AN is still in progress, wait till timeout. */
297 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
298 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
299 if (!(reg & MDIO_AN_STAT1_COMPLETE)) {
300 printf("%s Waiting for PHY auto negotiation to complete",
304 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
305 if ((i++ % 500) == 0)
307 } while (!(reg & MDIO_AN_STAT1_COMPLETE) &&
308 i < (4 * PHY_ANEG_TIMEOUT));
310 if (i > PHY_ANEG_TIMEOUT)
311 printf(" TIMEOUT !\n");
314 /* Read twice because link state is latched and a
315 * read moves the current state into the register */
316 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
317 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
318 if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
323 speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
324 if (speed & AQUNTIA_SPEED_MSB_MASK) {
325 if (speed & AQUNTIA_SPEED_LSB_MASK)
326 phydev->speed = SPEED_10000;
328 phydev->speed = SPEED_1000;
330 if (speed & AQUNTIA_SPEED_LSB_MASK)
331 phydev->speed = SPEED_100;
333 phydev->speed = SPEED_10;
339 struct phy_driver aq1202_driver = {
340 .name = "Aquantia AQ1202",
343 .features = PHY_10G_FEATURES,
344 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
345 MDIO_MMD_PHYXS | MDIO_MMD_AN |
347 .config = &aquantia_config,
348 .startup = &aquantia_startup,
349 .shutdown = &gen10g_shutdown,
352 struct phy_driver aq2104_driver = {
353 .name = "Aquantia AQ2104",
356 .features = PHY_10G_FEATURES,
357 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
358 MDIO_MMD_PHYXS | MDIO_MMD_AN |
360 .config = &aquantia_config,
361 .startup = &aquantia_startup,
362 .shutdown = &gen10g_shutdown,
365 struct phy_driver aqr105_driver = {
366 .name = "Aquantia AQR105",
369 .features = PHY_10G_FEATURES,
370 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
371 MDIO_MMD_PHYXS | MDIO_MMD_AN |
373 .config = &aquantia_config,
374 .startup = &aquantia_startup,
375 .shutdown = &gen10g_shutdown,
378 struct phy_driver aqr106_driver = {
379 .name = "Aquantia AQR106",
382 .features = PHY_10G_FEATURES,
383 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
384 MDIO_MMD_PHYXS | MDIO_MMD_AN |
386 .config = &aquantia_config,
387 .startup = &aquantia_startup,
388 .shutdown = &gen10g_shutdown,
391 struct phy_driver aqr107_driver = {
392 .name = "Aquantia AQR107",
395 .features = PHY_10G_FEATURES,
396 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
397 MDIO_MMD_PHYXS | MDIO_MMD_AN |
399 .config = &aquantia_config,
400 .startup = &aquantia_startup,
401 .shutdown = &gen10g_shutdown,
404 struct phy_driver aqr405_driver = {
405 .name = "Aquantia AQR405",
408 .features = PHY_10G_FEATURES,
409 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
410 MDIO_MMD_PHYXS | MDIO_MMD_AN |
412 .config = &aquantia_config,
413 .startup = &aquantia_startup,
414 .shutdown = &gen10g_shutdown,
417 int phy_aquantia_init(void)
419 phy_register(&aq1202_driver);
420 phy_register(&aq2104_driver);
421 phy_register(&aqr105_driver);
422 phy_register(&aqr106_driver);
423 phy_register(&aqr107_driver);
424 phy_register(&aqr405_driver);