1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
8 #include <dm/platform_data/pfe_dm_eth.h>
10 #include <net/pfe_eth/pfe_eth.h>
12 extern struct gemac_s gem_info[];
13 #if defined(CONFIG_PHYLIB)
15 #define MDIO_TIMEOUT 5000
16 static int pfe_write_addr(struct mii_dev *bus, int phy_addr, int dev_addr,
19 void *reg_base = bus->priv;
23 int timeout = MDIO_TIMEOUT;
25 devadr = ((dev_addr & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT);
26 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
28 reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr);
30 writel(reg_data, reg_base + EMAC_MII_DATA_REG);
33 * wait for the MII interrupt
35 while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
37 printf("Phy MDIO read/write timeout\n");
45 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
50 static int pfe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
53 void *reg_base = bus->priv;
58 int timeout = MDIO_TIMEOUT;
60 if (dev_addr == MDIO_DEVAD_NONE) {
61 reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
62 EMAC_MII_DATA_RA_SHIFT);
64 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
65 reg = ((dev_addr & EMAC_MII_DATA_RA_MASK) <<
66 EMAC_MII_DATA_RA_SHIFT);
69 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
71 if (dev_addr == MDIO_DEVAD_NONE)
72 reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD |
73 EMAC_MII_DATA_TA | phy | reg);
75 reg_data = (EMAC_MII_DATA_OP_CL45_RD | EMAC_MII_DATA_TA |
78 writel(reg_data, reg_base + EMAC_MII_DATA_REG);
81 * wait for the MII interrupt
83 while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
85 printf("Phy MDIO read/write timeout\n");
93 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
96 * it's now safe to read the PHY's register
98 val = (u16)readl(reg_base + EMAC_MII_DATA_REG);
99 debug("%s: %p phy: 0x%x reg:0x%08x val:%#x\n", __func__, reg_base,
100 phy_addr, reg_addr, val);
105 static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
106 int reg_addr, u16 data)
108 void *reg_base = bus->priv;
112 int timeout = MDIO_TIMEOUT;
115 if (dev_addr == MDIO_DEVAD_NONE) {
116 reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
117 EMAC_MII_DATA_RA_SHIFT);
119 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
120 reg = ((dev_addr & EMAC_MII_DATA_RA_MASK) <<
121 EMAC_MII_DATA_RA_SHIFT);
124 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
126 if (dev_addr == MDIO_DEVAD_NONE)
127 reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR |
128 EMAC_MII_DATA_TA | phy | reg | data);
130 reg_data = (EMAC_MII_DATA_OP_CL45_WR | EMAC_MII_DATA_TA |
133 writel(reg_data, reg_base + EMAC_MII_DATA_REG);
136 * wait for the MII interrupt
138 while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
139 if (timeout-- <= 0) {
140 printf("Phy MDIO read/write timeout\n");
146 * clear MII interrupt
148 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
150 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr,
156 static void pfe_configure_serdes(struct pfe_eth_dev *priv)
159 int value, sgmii_2500 = 0;
160 struct gemac_s *gem = priv->gem;
162 if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
166 /* PCS configuration done with corresponding GEMAC */
167 bus.priv = gem_info[priv->gemac_port].gemac_base;
169 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
170 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
171 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x2);
172 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x3);
175 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000);
177 /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
178 value = PHY_SGMII_IF_MODE_SGMII;
180 value |= PHY_SGMII_IF_MODE_AN;
182 value |= PHY_SGMII_IF_MODE_SGMII_GBT;
184 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
186 /* Dev ability according to SGMII specification */
187 value = PHY_SGMII_DEV_ABILITY_SGMII;
188 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
190 /* These values taken from validation team */
192 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0);
193 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0x400);
195 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x7);
196 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xa120);
200 value = PHY_SGMII_CR_DEF_VAL;
202 value |= PHY_SGMII_CR_RESET_AN;
203 /* Disable Auto neg for 2.5G SGMII as it doesn't support auto neg*/
205 value &= ~PHY_SGMII_ENABLE_AN;
206 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
209 int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id)
211 struct phy_device *phydev = NULL;
212 struct udevice *dev = priv->dev;
213 struct gemac_s *gem = priv->gem;
214 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
219 /* Configure SGMII PCS */
220 if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII ||
221 gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) {
222 out_be32(&scfg->mdioselcr, 0x00000000);
223 pfe_configure_serdes(priv);
228 /* By this time on-chip SGMII initialization is done
229 * we can switch mdio interface to external PHYs
231 out_be32(&scfg->mdioselcr, 0x80000000);
233 phydev = phy_connect(gem->bus, phy_id, dev, gem->phy_mode);
235 printf("phy_connect failed\n");
241 priv->phydev = phydev;
247 struct mii_dev *pfe_mdio_init(struct pfe_mdio_info *mdio_info)
252 u32 pclk = 250000000;
256 printf("mdio_alloc failed\n");
259 bus->read = pfe_phy_read;
260 bus->write = pfe_phy_write;
262 /* MAC1 MDIO used to communicate with external PHYS */
263 bus->priv = mdio_info->reg_base;
264 sprintf(bus->name, mdio_info->name);
266 /* configure mdio speed */
267 mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
268 mdio_speed |= EMAC_HOLDTIME(0x5);
269 writel(mdio_speed, mdio_info->reg_base + EMAC_MII_CTRL_REG);
271 ret = mdio_register(bus);
273 printf("mdio_register failed\n");
280 void pfe_set_mdio(int dev_id, struct mii_dev *bus)
282 gem_info[dev_id].bus = bus;
285 void pfe_set_phy_address_mode(int dev_id, int phy_id, int phy_mode)
287 gem_info[dev_id].phy_address = phy_id;
288 gem_info[dev_id].phy_mode = phy_mode;