2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier:GPL-2.0+
7 #include <net/pfe_eth/pfe_eth.h>
8 #include <net/pfe_eth/pfe/pfe_hw.h>
10 static struct pe_info pe[MAX_PE];
13 * Initializes the PFE library.
14 * Must be called before using any of the library functions.
16 void pfe_lib_init(void)
20 for (pfe_pe_id = CLASS0_ID; pfe_pe_id <= CLASS_MAX_ID; pfe_pe_id++) {
21 pe[pfe_pe_id].dmem_base_addr =
22 (u32)CLASS_DMEM_BASE_ADDR(pfe_pe_id);
23 pe[pfe_pe_id].pmem_base_addr =
24 (u32)CLASS_IMEM_BASE_ADDR(pfe_pe_id);
25 pe[pfe_pe_id].pmem_size = (u32)CLASS_IMEM_SIZE;
26 pe[pfe_pe_id].mem_access_wdata =
27 (void *)CLASS_MEM_ACCESS_WDATA;
28 pe[pfe_pe_id].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
29 pe[pfe_pe_id].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
32 for (pfe_pe_id = TMU0_ID; pfe_pe_id <= TMU_MAX_ID; pfe_pe_id++) {
33 if (pfe_pe_id == TMU2_ID)
35 pe[pfe_pe_id].dmem_base_addr =
36 (u32)TMU_DMEM_BASE_ADDR(pfe_pe_id - TMU0_ID);
37 pe[pfe_pe_id].pmem_base_addr =
38 (u32)TMU_IMEM_BASE_ADDR(pfe_pe_id - TMU0_ID);
39 pe[pfe_pe_id].pmem_size = (u32)TMU_IMEM_SIZE;
40 pe[pfe_pe_id].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
41 pe[pfe_pe_id].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
42 pe[pfe_pe_id].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
47 * Writes a buffer to PE internal memory from the host
48 * through indirect access registers.
50 * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
52 * @param[in] mem_access_addr DMEM destination address (must be 32bit
54 * @param[in] src Buffer source address
55 * @param[in] len Number of bytes to copy
57 static void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src,
60 u32 offset = 0, val, addr;
61 unsigned int len32 = len >> 2;
64 addr = mem_access_addr | PE_MEM_ACCESS_WRITE |
65 PE_MEM_ACCESS_BYTE_ENABLE(0, 4);
67 for (i = 0; i < len32; i++, offset += 4, src += 4) {
69 writel(cpu_to_be32(val), pe[id].mem_access_wdata);
70 writel(addr + offset, pe[id].mem_access_addr);
77 addr = (mem_access_addr | PE_MEM_ACCESS_WRITE |
78 PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;
80 for (i = 0; i < len; i++, src++)
81 val |= (*(u8 *)src) << (8 * i);
83 writel(cpu_to_be32(val), pe[id].mem_access_wdata);
84 writel(addr, pe[id].mem_access_addr);
89 * Writes a buffer to PE internal data memory (DMEM) from the host
90 * through indirect access registers.
91 * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
93 * @param[in] dst DMEM destination address (must be 32bit
95 * @param[in] src Buffer source address
96 * @param[in] len Number of bytes to copy
98 static void pe_dmem_memcpy_to32(int id, u32 dst, const void *src,
101 pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | PE_MEM_ACCESS_DMEM,
106 * Writes a buffer to PE internal program memory (PMEM) from the host
107 * through indirect access registers.
108 * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
110 * @param[in] dst PMEM destination address (must be 32bit
112 * @param[in] src Buffer source address
113 * @param[in] len Number of bytes to copy
115 static void pe_pmem_memcpy_to32(int id, u32 dst, const void *src,
118 pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size
119 - 1)) | PE_MEM_ACCESS_IMEM, src, len);
123 * Reads PE internal program memory (IMEM) from the host
124 * through indirect access registers.
125 * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
127 * @param[in] addr PMEM read address (must be aligned on size)
128 * @param[in] size Number of bytes to read (maximum 4, must not
129 * cross 32bit boundaries)
130 * @return the data read (in PE endianness, i.e BE).
132 u32 pe_pmem_read(int id, u32 addr, u8 size)
134 u32 offset = addr & 0x3;
135 u32 mask = 0xffffffff >> ((4 - size) << 3);
138 addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1))
139 | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_IMEM |
140 PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
142 writel(addr, pe[id].mem_access_addr);
143 val = be32_to_cpu(readl(pe[id].mem_access_rdata));
145 return (val >> (offset << 3)) & mask;
149 * Writes PE internal data memory (DMEM) from the host
150 * through indirect access registers.
151 * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
153 * @param[in] val Value to write (in PE endianness, i.e BE)
154 * @param[in] addr DMEM write address (must be aligned on size)
155 * @param[in] size Number of bytes to write (maximum 4, must not
156 * cross 32bit boundaries)
158 void pe_dmem_write(int id, u32 val, u32 addr, u8 size)
160 u32 offset = addr & 0x3;
162 addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE |
163 PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
165 /* Indirect access interface is byte swapping data being written */
166 writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);
167 writel(addr, pe[id].mem_access_addr);
171 * Reads PE internal data memory (DMEM) from the host
172 * through indirect access registers.
173 * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
175 * @param[in] addr DMEM read address (must be aligned on size)
176 * @param[in] size Number of bytes to read (maximum 4, must not
177 * cross 32bit boundaries)
178 * @return the data read (in PE endianness, i.e BE).
180 u32 pe_dmem_read(int id, u32 addr, u8 size)
182 u32 offset = addr & 0x3;
183 u32 mask = 0xffffffff >> ((4 - size) << 3);
186 addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_READ |
187 PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
189 writel(addr, pe[id].mem_access_addr);
191 /* Indirect access interface is byte swapping data being read */
192 val = be32_to_cpu(readl(pe[id].mem_access_rdata));
194 return (val >> (offset << 3)) & mask;
198 * This function is used to write to CLASS internal bus peripherals (ccu,
199 * pe-lem) from the host
200 * through indirect access registers.
201 * @param[in] val value to write
202 * @param[in] addr Address to write to (must be aligned on size)
203 * @param[in] size Number of bytes to write (1, 2 or 4)
206 static void class_bus_write(u32 val, u32 addr, u8 size)
208 u32 offset = addr & 0x3;
210 writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
212 addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE |
215 writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);
216 writel(addr, CLASS_BUS_ACCESS_ADDR);
220 * Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
221 * through indirect access registers.
222 * @param[in] addr Address to read from (must be aligned on size)
223 * @param[in] size Number of bytes to read (1, 2 or 4)
224 * @return the read data
226 static u32 class_bus_read(u32 addr, u8 size)
228 u32 offset = addr & 0x3;
229 u32 mask = 0xffffffff >> ((4 - size) << 3);
232 writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
234 addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24);
236 writel(addr, CLASS_BUS_ACCESS_ADDR);
237 val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));
239 return (val >> (offset << 3)) & mask;
243 * Writes data to the cluster memory (PE_LMEM)
244 * @param[in] dst PE LMEM destination address (must be 32bit aligned)
245 * @param[in] src Buffer source address
246 * @param[in] len Number of bytes to copy
248 static void class_pe_lmem_memcpy_to32(u32 dst, const void *src,
251 u32 len32 = len >> 2;
254 for (i = 0; i < len32; i++, src += 4, dst += 4)
255 class_bus_write(*(u32 *)src, dst, 4);
258 class_bus_write(*(u16 *)src, dst, 2);
264 class_bus_write(*(u8 *)src, dst, 1);
271 * Writes value to the cluster memory (PE_LMEM)
272 * @param[in] dst PE LMEM destination address (must be 32bit aligned)
273 * @param[in] val Value to write
274 * @param[in] len Number of bytes to write
276 static void class_pe_lmem_memset(u32 dst, int val, unsigned int len)
278 u32 len32 = len >> 2;
281 val = val | (val << 8) | (val << 16) | (val << 24);
283 for (i = 0; i < len32; i++, dst += 4)
284 class_bus_write(val, dst, 4);
287 class_bus_write(val, dst, 2);
292 class_bus_write(val, dst, 1);
298 * Reads data from the cluster memory (PE_LMEM)
299 * @param[out] dst pointer to the source buffer data are copied to
300 * @param[in] len length in bytes of the amount of data to read
301 * from cluster memory
302 * @param[in] offset offset in bytes in the cluster memory where data are
305 void pe_lmem_read(u32 *dst, u32 len, u32 offset)
307 u32 len32 = len >> 2;
310 for (i = 0; i < len32; dst++, i++, offset += 4)
311 *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, 4);
314 *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, (len & 0x03));
318 * Writes data to the cluster memory (PE_LMEM)
319 * @param[in] src pointer to the source buffer data are copied from
320 * @param[in] len length in bytes of the amount of data to write to the
322 * @param[in] offset offset in bytes in the cluster memory where data are
325 void pe_lmem_write(u32 *src, u32 len, u32 offset)
327 u32 len32 = len >> 2;
330 for (i = 0; i < len32; src++, i++, offset += 4)
331 class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, 4);
334 class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, (len &
339 * Loads an elf section into pmem
340 * Code needs to be at least 16bit aligned and only PROGBITS sections are
343 * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ...,
345 * @param[in] data pointer to the elf firmware
346 * @param[in] shdr pointer to the elf section header
348 static int pe_load_pmem_section(int id, const void *data, Elf32_Shdr *shdr)
350 u32 offset = be32_to_cpu(shdr->sh_offset);
351 u32 addr = be32_to_cpu(shdr->sh_addr);
352 u32 size = be32_to_cpu(shdr->sh_size);
353 u32 type = be32_to_cpu(shdr->sh_type);
355 if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
357 "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
358 __func__, addr, (unsigned long)data + offset);
364 printf("%s: load address(%x) is not 16bit aligned\n",
370 printf("%s: load size(%x) is not 16bit aligned\n", __func__,
375 debug("pmem pe%d @%x len %d\n", id, addr, size);
378 pe_pmem_memcpy_to32(id, addr, data + offset, size);
382 printf("%s: unsupported section type(%x)\n", __func__, type);
390 * Loads an elf section into dmem
391 * Data needs to be at least 32bit aligned, NOBITS sections are correctly
394 * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
396 * @param[in] data pointer to the elf firmware
397 * @param[in] shdr pointer to the elf section header
399 static int pe_load_dmem_section(int id, const void *data, Elf32_Shdr *shdr)
401 u32 offset = be32_to_cpu(shdr->sh_offset);
402 u32 addr = be32_to_cpu(shdr->sh_addr);
403 u32 size = be32_to_cpu(shdr->sh_size);
404 u32 type = be32_to_cpu(shdr->sh_type);
405 u32 size32 = size >> 2;
408 if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
410 "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
411 __func__, addr, (unsigned long)data + offset);
417 printf("%s: load address(%x) is not 32bit aligned\n",
424 debug("dmem pe%d @%x len %d\n", id, addr, size);
425 pe_dmem_memcpy_to32(id, addr, data + offset, size);
429 debug("dmem zero pe%d @%x len %d\n", id, addr, size);
430 for (i = 0; i < size32; i++, addr += 4)
431 pe_dmem_write(id, 0, addr, 4);
434 pe_dmem_write(id, 0, addr, size & 0x3);
439 printf("%s: unsupported section type(%x)\n", __func__, type);
447 * Loads an elf section into DDR
448 * Data needs to be at least 32bit aligned, NOBITS sections are correctly
451 * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
453 * @param[in] data pointer to the elf firmware
454 * @param[in] shdr pointer to the elf section header
456 static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
458 u32 offset = be32_to_cpu(shdr->sh_offset);
459 u32 addr = be32_to_cpu(shdr->sh_addr);
460 u32 size = be32_to_cpu(shdr->sh_size);
461 u32 type = be32_to_cpu(shdr->sh_type);
462 u32 flags = be32_to_cpu(shdr->sh_flags);
466 debug("ddr pe%d @%x len %d\n", id, addr, size);
467 if (flags & SHF_EXECINSTR) {
468 if (id <= CLASS_MAX_ID) {
469 /* DO the loading only once in DDR */
470 if (id == CLASS0_ID) {
472 "%s: load address(%x) and elf file address(%lx) rcvd\n"
474 (unsigned long)data + offset);
475 if (((unsigned long)(data + offset)
476 & 0x3) != (addr & 0x3)) {
478 "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
480 (unsigned long)data +
488 "%s: load address(%x) is not 16bit aligned\n"
495 "%s: load length(%x) is not 16bit aligned\n"
500 memcpy((void *)DDR_PFE_TO_VIRT(addr),
501 data + offset, size);
505 "%s: unsupported ddr section type(%x) for PE(%d)\n"
506 , __func__, type, id);
511 memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset,
518 debug("ddr zero pe%d @%x len %d\n", id, addr, size);
519 memset((void *)DDR_PFE_TO_VIRT(addr), 0, size);
524 printf("%s: unsupported section type(%x)\n", __func__, type);
532 * Loads an elf section into pe lmem
533 * Data needs to be at least 32bit aligned, NOBITS sections are correctly
536 * @param[in] id PE identification (CLASS0_ID,..., CLASS5_ID)
537 * @param[in] data pointer to the elf firmware
538 * @param[in] shdr pointer to the elf section header
540 static int pe_load_pe_lmem_section(int id, const void *data, Elf32_Shdr *shdr)
542 u32 offset = be32_to_cpu(shdr->sh_offset);
543 u32 addr = be32_to_cpu(shdr->sh_addr);
544 u32 size = be32_to_cpu(shdr->sh_size);
545 u32 type = be32_to_cpu(shdr->sh_type);
547 if (id > CLASS_MAX_ID) {
548 printf("%s: unsupported pe-lmem section type(%x) for PE(%d)\n",
553 if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
555 "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
556 __func__, addr, (unsigned long)data + offset);
562 printf("%s: load address(%x) is not 32bit aligned\n",
567 debug("lmem pe%d @%x len %d\n", id, addr, size);
571 class_pe_lmem_memcpy_to32(addr, data + offset, size);
575 class_pe_lmem_memset(addr, 0, size);
579 printf("%s: unsupported section type(%x)\n", __func__, type);
587 * Loads an elf section into a PE
588 * For now only supports loading a section to dmem (all PE's), pmem (class and
589 * tmu PE's), DDDR (util PE code)
590 * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
592 * @param[in] data pointer to the elf firmware
593 * @param[in] shdr pointer to the elf section header
595 int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr)
597 u32 addr = be32_to_cpu(shdr->sh_addr);
598 u32 size = be32_to_cpu(shdr->sh_size);
600 if (IS_DMEM(addr, size))
601 return pe_load_dmem_section(id, data, shdr);
602 else if (IS_PMEM(addr, size))
603 return pe_load_pmem_section(id, data, shdr);
604 else if (IS_PFE_LMEM(addr, size))
606 else if (IS_PHYS_DDR(addr, size))
607 return pe_load_ddr_section(id, data, shdr);
608 else if (IS_PE_LMEM(addr, size))
609 return pe_load_pe_lmem_section(id, data, shdr);
611 printf("%s: unsupported memory range(%x)\n", __func__, addr);
616 /**************************** BMU ***************************/
618 * Resets a BMU block.
619 * @param[in] base BMU block base address
621 static inline void bmu_reset(void *base)
623 writel(CORE_SW_RESET, base + BMU_CTRL);
625 /* Wait for self clear */
626 while (readl(base + BMU_CTRL) & CORE_SW_RESET)
631 * Enabled a BMU block.
632 * @param[in] base BMU block base address
634 void bmu_enable(void *base)
636 writel(CORE_ENABLE, base + BMU_CTRL);
640 * Disables a BMU block.
641 * @param[in] base BMU block base address
643 static inline void bmu_disable(void *base)
645 writel(CORE_DISABLE, base + BMU_CTRL);
649 * Sets the configuration of a BMU block.
650 * @param[in] base BMU block base address
651 * @param[in] cfg BMU configuration
653 static inline void bmu_set_config(void *base, struct bmu_cfg *cfg)
655 writel(cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);
656 writel(cfg->count & 0xffff, base + BMU_UCAST_CONFIG);
657 writel(cfg->size & 0xffff, base + BMU_BUF_SIZE);
659 /* Interrupts are never used */
660 writel(0x0, base + BMU_INT_ENABLE);
664 * Initializes a BMU block.
665 * @param[in] base BMU block base address
666 * @param[in] cfg BMU configuration
668 void bmu_init(void *base, struct bmu_cfg *cfg)
672 bmu_set_config(base, cfg);
677 /**************************** GPI ***************************/
679 * Resets a GPI block.
680 * @param[in] base GPI base address
682 static inline void gpi_reset(void *base)
684 writel(CORE_SW_RESET, base + GPI_CTRL);
688 * Enables a GPI block.
689 * @param[in] base GPI base address
691 void gpi_enable(void *base)
693 writel(CORE_ENABLE, base + GPI_CTRL);
697 * Disables a GPI block.
698 * @param[in] base GPI base address
700 void gpi_disable(void *base)
702 writel(CORE_DISABLE, base + GPI_CTRL);
706 * Sets the configuration of a GPI block.
707 * @param[in] base GPI base address
708 * @param[in] cfg GPI configuration
710 static inline void gpi_set_config(void *base, struct gpi_cfg *cfg)
712 writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base
713 + GPI_LMEM_ALLOC_ADDR);
714 writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base
715 + GPI_LMEM_FREE_ADDR);
716 writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base
717 + GPI_DDR_ALLOC_ADDR);
718 writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base
719 + GPI_DDR_FREE_ADDR);
720 writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR);
721 writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET);
722 writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET);
723 writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET);
724 writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET);
725 writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE);
726 writel((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE);
728 writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) |
729 GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);
730 writel(cfg->tmlf_txthres, base + GPI_TMLF_TX);
731 writel(cfg->aseq_len, base + GPI_DTX_ASEQ);
733 /*Make GPI AXI transactions non-bufferable */
734 writel(0x1, base + GPI_AXI_CTRL);
738 * Initializes a GPI block.
739 * @param[in] base GPI base address
740 * @param[in] cfg GPI configuration
742 void gpi_init(void *base, struct gpi_cfg *cfg)
748 gpi_set_config(base, cfg);
751 /**************************** CLASSIFIER ***************************/
753 * Resets CLASSIFIER block.
755 static inline void class_reset(void)
757 writel(CORE_SW_RESET, CLASS_TX_CTRL);
761 * Enables all CLASS-PE's cores.
763 void class_enable(void)
765 writel(CORE_ENABLE, CLASS_TX_CTRL);
769 * Disables all CLASS-PE's cores.
771 void class_disable(void)
773 writel(CORE_DISABLE, CLASS_TX_CTRL);
777 * Sets the configuration of the CLASSIFIER block.
778 * @param[in] cfg CLASSIFIER configuration
780 static inline void class_set_config(struct class_cfg *cfg)
782 if (PLL_CLK_EN == 0) {
783 /* Clock ratio: for 1:1 the value is 0 */
784 writel(0x0, CLASS_PE_SYS_CLK_RATIO);
786 /* Clock ratio: for 1:2 the value is 1 */
787 writel(0x1, CLASS_PE_SYS_CLK_RATIO);
789 writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, CLASS_HDR_SIZE);
790 writel(LMEM_BUF_SIZE, CLASS_LMEM_BUF_SIZE);
791 writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) |
792 CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits),
793 CLASS_ROUTE_HASH_ENTRY_SIZE);
794 writel(HASH_CRC_PORT_IP | QB2BUS_LE, CLASS_ROUTE_MULTI);
796 writel(cfg->route_table_baseaddr, CLASS_ROUTE_TABLE_BASE);
797 memset((void *)DDR_PFE_TO_VIRT(cfg->route_table_baseaddr), 0,
800 writel(CLASS_PE0_RO_DM_ADDR0_VAL, CLASS_PE0_RO_DM_ADDR0);
801 writel(CLASS_PE0_RO_DM_ADDR1_VAL, CLASS_PE0_RO_DM_ADDR1);
802 writel(CLASS_PE0_QB_DM_ADDR0_VAL, CLASS_PE0_QB_DM_ADDR0);
803 writel(CLASS_PE0_QB_DM_ADDR1_VAL, CLASS_PE0_QB_DM_ADDR1);
804 writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), CLASS_TM_INQ_ADDR);
806 writel(23, CLASS_AFULL_THRES);
807 writel(23, CLASS_TSQ_FIFO_THRES);
809 writel(24, CLASS_MAX_BUF_CNT);
810 writel(24, CLASS_TSQ_MAX_CNT);
812 /*Make Class AXI transactions non-bufferable */
813 writel(0x1, CLASS_AXI_CTRL);
815 /*Make Util AXI transactions non-bufferable */
816 /*Util is disabled in U-boot, do it from here */
817 writel(0x1, UTIL_AXI_CTRL);
821 * Initializes CLASSIFIER block.
822 * @param[in] cfg CLASSIFIER configuration
824 void class_init(struct class_cfg *cfg)
830 class_set_config(cfg);
833 /**************************** TMU ***************************/
835 * Enables TMU-PE cores.
836 * @param[in] pe_mask TMU PE mask
838 void tmu_enable(u32 pe_mask)
840 writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL);
844 * Disables TMU cores.
845 * @param[in] pe_mask TMU PE mask
847 void tmu_disable(u32 pe_mask)
849 writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL);
853 * Initializes TMU block.
854 * @param[in] cfg TMU configuration
856 void tmu_init(struct tmu_cfg *cfg)
860 /* keep in soft reset */
861 writel(SW_RESET, TMU_CTRL);
863 /*Make Class AXI transactions non-bufferable */
864 writel(0x1, TMU_AXI_CTRL);
866 /* enable EMAC PHY ports */
867 writel(0x3, TMU_SYS_GENERIC_CONTROL);
869 writel(750, TMU_INQ_WATERMARK);
871 writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR + GPI_INQ_PKTPTR),
873 writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR + GPI_INQ_PKTPTR),
876 writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR + GPI_INQ_PKTPTR),
878 writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR);
879 writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR);
880 writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),
883 /* enabling all 10 schedulers [9:0] of each TDQ */
884 writel(0x3FF, TMU_TDQ0_SCH_CTRL);
885 writel(0x3FF, TMU_TDQ1_SCH_CTRL);
886 writel(0x3FF, TMU_TDQ3_SCH_CTRL);
888 if (PLL_CLK_EN == 0) {
889 /* Clock ratio: for 1:1 the value is 0 */
890 writel(0x0, TMU_PE_SYS_CLK_RATIO);
892 /* Clock ratio: for 1:2 the value is 1 */
893 writel(0x1, TMU_PE_SYS_CLK_RATIO);
896 /* Extra packet pointers will be stored from this address onwards */
897 debug("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
898 writel(cfg->llm_base_addr, TMU_LLM_BASE_ADDR);
900 debug("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
901 writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN);
903 writel(5, TMU_TDQ_IIFG_CFG);
904 writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE);
906 writel(0x0, TMU_CTRL);
909 writel(MEM_INIT, TMU_CTRL);
911 while (!(readl(TMU_CTRL) & MEM_INIT_DONE))
915 writel(LLM_INIT, TMU_CTRL);
917 while (!(readl(TMU_CTRL) & LLM_INIT_DONE))
920 /* set up each queue for tail drop */
921 for (phyno = 0; phyno < 4; phyno++) {
924 for (q = 0; q < 16; q++) {
927 writel((phyno << 8) | q, TMU_TEQ_CTRL);
928 writel(BIT(22), TMU_TEQ_QCFG);
931 qmax = DEFAULT_TMU3_QDEPTH;
933 qmax = (q == 0) ? DEFAULT_Q0_QDEPTH :
936 writel(qmax << 18, TMU_TEQ_HW_PROB_CFG2);
937 writel(qmax >> 14, TMU_TEQ_HW_PROB_CFG3);
940 writel(0x05, TMU_TEQ_DISABLE_DROPCHK);
944 /**************************** HIF ***************************/
946 * Enable hif tx DMA and interrupt
948 void hif_tx_enable(void)
950 writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL);
954 * Disable hif tx DMA and interrupt
956 void hif_tx_disable(void)
960 writel(0, HIF_TX_CTRL);
962 hif_int = readl(HIF_INT_ENABLE);
963 hif_int &= HIF_TXPKT_INT_EN;
964 writel(hif_int, HIF_INT_ENABLE);
968 * Enable hif rx DMA and interrupt
970 void hif_rx_enable(void)
972 writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
976 * Disable hif rx DMA and interrupt
978 void hif_rx_disable(void)
982 writel(0, HIF_RX_CTRL);
984 hif_int = readl(HIF_INT_ENABLE);
985 hif_int &= HIF_RXPKT_INT_EN;
986 writel(hif_int, HIF_INT_ENABLE);
990 * Initializes HIF copy block.
994 /* Initialize HIF registers */
995 writel(HIF_RX_POLL_CTRL_CYCLE << 16 | HIF_TX_POLL_CTRL_CYCLE,
997 /* Make HIF AXI transactions non-bufferable */
998 writel(0x1, HIF_AXI_CTRL);