2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <net/pfe_eth/pfe_eth.h>
9 #include <net/pfe_eth/pfe_firmware.h>
11 static struct tx_desc_s *g_tx_desc;
12 static struct rx_desc_s *g_rx_desc;
15 * HIF Rx interface function
16 * Reads the rx descriptor from the current location (rx_to_read).
17 * - If the descriptor has a valid data/pkt, then get the data pointer
18 * - check for the input rx phy number
19 * - increment the rx data pointer by pkt_head_room_size
20 * - decrement the data length by pkt_head_room_size
21 * - handover the packet to caller.
23 * @param[out] pkt_ptr - Pointer to store rx packet
24 * @param[out] phy_port - Pointer to store recv phy port
26 * @return -1 if no packet, else return length of packet.
28 int pfe_recv(uchar **pkt_ptr, int *phy_port)
30 struct rx_desc_s *rx_desc = g_rx_desc;
34 struct hif_header_s *hif_header;
36 bd = rx_desc->rx_base + rx_desc->rx_to_read;
38 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
39 return len; /* No pending Rx packet */
41 /* this len include hif_header(8 bytes) */
42 len = readl(&bd->ctrl) & 0xFFFF;
44 hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(readl(&bd->data));
46 /* Get the receive port info from the packet */
47 debug("Pkt received:");
48 debug(" Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
49 hif_header, len, hif_header->port_no, readl(&bd->status));
53 unsigned char *p = (unsigned char *)hif_header;
55 for (i = 0; i < len; i++) {
58 printf(" %02x", p[i]);
64 *pkt_ptr = (uchar *)(hif_header + 1);
65 *phy_port = hif_header->port_no;
66 len -= sizeof(struct hif_header_s);
72 * HIF function to check the Rx done
73 * This function will check the rx done indication of the current rx_to_read
75 * if success, moves the rx_to_read to next location.
77 int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
79 struct rx_desc_s *rx_desc = g_rx_desc;
82 debug("%s:rx_base: %p, rx_to_read: %d\n", __func__, rx_desc->rx_base,
85 bd = rx_desc->rx_base + rx_desc->rx_to_read;
87 /* reset the control field */
88 writel((MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
89 | BD_CTRL_DIR), &bd->ctrl);
90 writel(0, &bd->status);
92 debug("Rx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
95 /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
96 * BDP need not wait for rx_poll_cycle time to fetch the descriptor,
97 * In idle state (ie., no rx pkt), BDP will not fetch
98 * the descriptor even if strobe is given.
100 writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
102 /* increment the rx_to_read index to next location */
103 rx_desc->rx_to_read = (rx_desc->rx_to_read + 1)
104 & (rx_desc->rx_ring_size - 1);
106 debug("Rx next pkt location: %d\n", rx_desc->rx_to_read);
112 * HIF Tx interface function
113 * This function sends a single packet to PFE from HIF interface.
114 * - No interrupt indication on tx completion.
115 * - Data is copied to tx buffers before tx descriptor is updated
116 * and TX DMA is enabled.
118 * @param[in] phy_port Phy port number to send out this packet
119 * @param[in] data Pointer to the data
120 * @param[in] length Length of the ethernet packet to be transferred.
122 * @return -1 if tx Q is full, else returns the tx location where the pkt is
125 int pfe_send(int phy_port, void *data, int length)
127 struct tx_desc_s *tx_desc = g_tx_desc;
129 struct hif_header_s hif_header;
132 debug("%s:pkt: %p, len: %d, tx_base: %p, tx_to_send: %d\n", __func__,
133 data, length, tx_desc->tx_base, tx_desc->tx_to_send);
135 bd = tx_desc->tx_base + tx_desc->tx_to_send;
137 /* check queue-full condition */
138 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
141 /* PFE checks for min pkt size */
142 if (length < MIN_PKT_SIZE)
143 length = MIN_PKT_SIZE;
145 tx_buf_va = (void *)DDR_PFE_TO_VIRT(readl(&bd->data));
146 debug("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va,
149 /* Fill the gemac/phy port number to send this packet out */
150 memset(&hif_header, 0, sizeof(struct hif_header_s));
151 hif_header.port_no = phy_port;
153 memcpy(tx_buf_va, (u8 *)&hif_header, sizeof(struct hif_header_s));
154 memcpy(tx_buf_va + sizeof(struct hif_header_s), data, length);
155 length += sizeof(struct hif_header_s);
160 unsigned char *p = (unsigned char *)tx_buf_va;
162 for (i = 0; i < length; i++) {
165 printf("%02x ", p[i]);
170 debug("Tx Done: status: %08x, ctrl: %08x\n", readl(&bd->status),
173 /* fill the tx desc */
174 writel((u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0xFFFF)),
176 writel(0, &bd->status);
178 writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL);
182 return tx_desc->tx_to_send;
186 * HIF function to check the Tx done
187 * This function will check the tx done indication of the current tx_to_send
189 * if success, moves the tx_to_send to next location.
191 * @return -1 if TX ownership bit is not cleared by hw.
192 * else on success (tx done completion) return zero.
194 int pfe_tx_done(void)
196 struct tx_desc_s *tx_desc = g_tx_desc;
199 debug("%s:tx_base: %p, tx_to_send: %d\n", __func__, tx_desc->tx_base,
200 tx_desc->tx_to_send);
202 bd = tx_desc->tx_base + tx_desc->tx_to_send;
204 /* check queue-full condition */
205 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
208 /* reset the control field */
209 writel(0, &bd->ctrl);
210 writel(0, &bd->status);
212 debug("Tx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
215 /* increment the txtosend index to next location */
216 tx_desc->tx_to_send = (tx_desc->tx_to_send + 1)
217 & (tx_desc->tx_ring_size - 1);
219 debug("Tx next pkt location: %d\n", tx_desc->tx_to_send);
225 * Helper function to dump Rx descriptors.
227 static inline void hif_rx_desc_dump(void)
229 struct buf_desc *bd_va;
231 struct rx_desc_s *rx_desc;
234 printf("%s: HIF Rx desc no init\n", __func__);
239 bd_va = rx_desc->rx_base;
241 debug("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rx_base,
242 rx_desc->rx_base_pa);
243 for (i = 0; i < rx_desc->rx_ring_size; i++) {
244 debug("status: %08x, ctrl: %08x, data: %08x, next: 0x%08x\n",
245 readl(&bd_va->status),
248 readl(&bd_va->next));
254 * This function mark all Rx descriptors as LAST_BD.
256 void hif_rx_desc_disable(void)
259 struct rx_desc_s *rx_desc;
260 struct buf_desc *bd_va;
263 printf("%s: HIF Rx desc not initialized\n", __func__);
268 bd_va = rx_desc->rx_base;
270 for (i = 0; i < rx_desc->rx_ring_size; i++) {
271 writel(readl(&bd_va->ctrl) | BD_CTRL_LAST_BD, &bd_va->ctrl);
277 * HIF Rx Desc initialization function.
279 static int hif_rx_desc_init(struct pfe_ddr_address *pfe_addr)
282 struct buf_desc *bd_va;
283 struct buf_desc *bd_pa;
284 struct rx_desc_s *rx_desc;
290 printf("%s: HIF Rx desc re-init request\n", __func__);
294 rx_desc = (struct rx_desc_s *)malloc(sizeof(struct rx_desc_s));
296 printf("%s: Memory allocation failure\n", __func__);
299 memset(rx_desc, 0, sizeof(struct rx_desc_s));
301 /* init: Rx ring buffer */
302 rx_desc->rx_ring_size = HIF_RX_DESC_NT;
304 /* NOTE: must be 64bit aligned */
305 bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
307 bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
310 rx_desc->rx_base = bd_va;
311 rx_desc->rx_base_pa = (unsigned long)bd_pa;
313 rx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR;
315 debug("%s: Rx desc base: %p, base_pa: %08x, desc_count: %d\n",
316 __func__, rx_desc->rx_base, rx_desc->rx_base_pa,
317 rx_desc->rx_ring_size);
319 memset(bd_va, 0, sizeof(struct buf_desc) * rx_desc->rx_ring_size);
321 ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
323 for (i = 0; i < rx_desc->rx_ring_size; i++) {
324 writel((unsigned long)(bd_pa + 1), &bd_va->next);
325 writel(ctrl, &bd_va->ctrl);
326 writel(rx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
331 writel((u32)rx_desc->rx_base_pa, &bd_va->next);
333 writel(rx_desc->rx_base_pa, HIF_RX_BDP_ADDR);
334 writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
342 * Helper function to dump Tx Descriptors.
344 static inline void hif_tx_desc_dump(void)
346 struct tx_desc_s *tx_desc;
348 struct buf_desc *bd_va;
351 printf("%s: HIF Tx desc no init\n", __func__);
356 bd_va = tx_desc->tx_base;
358 debug("HIF tx desc: base_va: %p, base_pa: %08x\n", tx_desc->tx_base,
359 tx_desc->tx_base_pa);
361 for (i = 0; i < tx_desc->tx_ring_size; i++)
366 * HIF Tx descriptor initialization function.
368 static int hif_tx_desc_init(struct pfe_ddr_address *pfe_addr)
370 struct buf_desc *bd_va;
371 struct buf_desc *bd_pa;
373 struct tx_desc_s *tx_desc;
378 printf("%s: HIF Tx desc re-init request\n", __func__);
382 tx_desc = (struct tx_desc_s *)malloc(sizeof(struct tx_desc_s));
384 printf("%s:%d:Memory allocation failure\n", __func__,
388 memset(tx_desc, 0, sizeof(struct tx_desc_s));
390 /* init: Tx ring buffer */
391 tx_desc->tx_ring_size = HIF_TX_DESC_NT;
393 /* NOTE: must be 64bit aligned */
394 bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
396 bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
399 tx_desc->tx_base_pa = (unsigned long)bd_pa;
400 tx_desc->tx_base = bd_va;
402 debug("%s: Tx desc_base: %p, base_pa: %08x, desc_count: %d\n",
403 __func__, tx_desc->tx_base, tx_desc->tx_base_pa,
404 tx_desc->tx_ring_size);
406 memset(bd_va, 0, sizeof(struct buf_desc) * tx_desc->tx_ring_size);
408 tx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
410 for (i = 0; i < tx_desc->tx_ring_size; i++) {
411 writel((unsigned long)(bd_pa + 1), &bd_va->next);
412 writel(tx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
417 writel((u32)tx_desc->tx_base_pa, &bd_va->next);
419 writel(tx_desc->tx_base_pa, HIF_TX_BDP_ADDR);
427 * PFE/Class initialization.
429 static void pfe_class_init(struct pfe_ddr_address *pfe_addr)
431 struct class_cfg class_cfg = {
432 .route_table_baseaddr = pfe_addr->ddr_pfe_phys_baseaddr +
433 ROUTE_TABLE_BASEADDR,
434 .route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
437 class_init(&class_cfg);
439 debug("class init complete\n");
443 * PFE/TMU initialization.
445 static void pfe_tmu_init(struct pfe_ddr_address *pfe_addr)
447 struct tmu_cfg tmu_cfg = {
448 .llm_base_addr = pfe_addr->ddr_pfe_phys_baseaddr
450 .llm_queue_len = TMU_LLM_QUEUE_LEN,
455 debug("tmu init complete\n");
459 * PFE/BMU (both BMU1 & BMU2) initialization.
461 static void pfe_bmu_init(struct pfe_ddr_address *pfe_addr)
463 struct bmu_cfg bmu1_cfg = {
464 .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR +
466 .count = BMU1_BUF_COUNT,
467 .size = BMU1_BUF_SIZE,
470 struct bmu_cfg bmu2_cfg = {
471 .baseaddr = pfe_addr->ddr_pfe_phys_baseaddr + BMU2_DDR_BASEADDR,
472 .count = BMU2_BUF_COUNT,
473 .size = BMU2_BUF_SIZE,
476 bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
477 debug("bmu1 init: done\n");
479 bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
480 debug("bmu2 init: done\n");
484 * PFE/GPI initialization function.
485 * - egpi1, egpi2, egpi3, hgpi
487 static void pfe_gpi_init(struct pfe_ddr_address *pfe_addr)
489 struct gpi_cfg egpi1_cfg = {
490 .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
491 .tmlf_txthres = EGPI1_TMLF_TXTHRES,
492 .aseq_len = EGPI1_ASEQ_LEN,
495 struct gpi_cfg egpi2_cfg = {
496 .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
497 .tmlf_txthres = EGPI2_TMLF_TXTHRES,
498 .aseq_len = EGPI2_ASEQ_LEN,
501 struct gpi_cfg hgpi_cfg = {
502 .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
503 .tmlf_txthres = HGPI_TMLF_TXTHRES,
504 .aseq_len = HGPI_ASEQ_LEN,
507 gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
508 debug("GPI1 init complete\n");
510 gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
511 debug("GPI2 init complete\n");
513 gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
514 debug("HGPI init complete\n");
518 * PFE/HIF initialization function.
520 static int pfe_hif_init(struct pfe_ddr_address *pfe_addr)
527 ret = hif_tx_desc_init(pfe_addr);
530 ret = hif_rx_desc_init(pfe_addr);
542 debug("HIF init complete\n");
548 * - Firmware loading (CLASS-PE and TMU-PE)
549 * - BMU1 and BMU2 init
554 * - HIF tx and rx descriptors init
556 * @param[in] edev Pointer to eth device structure.
558 * @return 0, on success.
560 static int pfe_hw_init(struct pfe_ddr_address *pfe_addr)
564 debug("%s: start\n", __func__);
566 writel(0x3, CLASS_PE_SYS_CLK_RATIO);
567 writel(0x3, TMU_PE_SYS_CLK_RATIO);
568 writel(0x3, UTIL_PE_SYS_CLK_RATIO);
571 pfe_class_init(pfe_addr);
573 pfe_tmu_init(pfe_addr);
575 pfe_bmu_init(pfe_addr);
577 pfe_gpi_init(pfe_addr);
579 ret = pfe_hif_init(pfe_addr);
583 bmu_enable(BMU1_BASE_ADDR);
584 debug("bmu1 enabled\n");
586 bmu_enable(BMU2_BASE_ADDR);
587 debug("bmu2 enabled\n");
589 debug("%s: done\n", __func__);
595 * PFE driver init function.
596 * - Initializes pfe_lib
598 * - fw loading and enables PEs
599 * - should be executed once.
601 * @param[in] pfe Pointer the pfe control block
603 int pfe_drv_init(struct pfe_ddr_address *pfe_addr)
609 ret = pfe_hw_init(pfe_addr);
613 /* Load the class,TM, Util fw.
615 * - out of reset + disabled + configured.
616 * Fw loading should be done after pfe_hw_init()
618 /* It loads default inbuilt sbl firmware */
625 * PFE remove function
627 * - frees tx/rx descriptor resources
628 * - should be called once.
630 * @param[in] pfe Pointer to pfe control block.
632 int pfe_eth_remove(struct udevice *dev)