1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
7 #include <net/pfe_eth/pfe_eth.h>
8 #include <net/pfe_eth/pfe_firmware.h>
10 static struct tx_desc_s *g_tx_desc;
11 static struct rx_desc_s *g_rx_desc;
14 * HIF Rx interface function
15 * Reads the rx descriptor from the current location (rx_to_read).
16 * - If the descriptor has a valid data/pkt, then get the data pointer
17 * - check for the input rx phy number
18 * - increment the rx data pointer by pkt_head_room_size
19 * - decrement the data length by pkt_head_room_size
20 * - handover the packet to caller.
22 * @param[out] pkt_ptr - Pointer to store rx packet
23 * @param[out] phy_port - Pointer to store recv phy port
25 * @return -1 if no packet, else return length of packet.
27 int pfe_recv(uchar **pkt_ptr, int *phy_port)
29 struct rx_desc_s *rx_desc = g_rx_desc;
33 struct hif_header_s *hif_header;
35 bd = rx_desc->rx_base + rx_desc->rx_to_read;
37 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
38 return len; /* No pending Rx packet */
40 /* this len include hif_header(8 bytes) */
41 len = readl(&bd->ctrl) & 0xFFFF;
43 hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(readl(&bd->data));
45 /* Get the receive port info from the packet */
46 debug("Pkt received:");
47 debug(" Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
48 hif_header, len, hif_header->port_no, readl(&bd->status));
52 unsigned char *p = (unsigned char *)hif_header;
54 for (i = 0; i < len; i++) {
57 printf(" %02x", p[i]);
63 *pkt_ptr = (uchar *)(hif_header + 1);
64 *phy_port = hif_header->port_no;
65 len -= sizeof(struct hif_header_s);
71 * HIF function to check the Rx done
72 * This function will check the rx done indication of the current rx_to_read
74 * if success, moves the rx_to_read to next location.
76 int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
78 struct rx_desc_s *rx_desc = g_rx_desc;
81 debug("%s:rx_base: %p, rx_to_read: %d\n", __func__, rx_desc->rx_base,
84 bd = rx_desc->rx_base + rx_desc->rx_to_read;
86 /* reset the control field */
87 writel((MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
88 | BD_CTRL_DIR), &bd->ctrl);
89 writel(0, &bd->status);
91 debug("Rx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
94 /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
95 * BDP need not wait for rx_poll_cycle time to fetch the descriptor,
96 * In idle state (ie., no rx pkt), BDP will not fetch
97 * the descriptor even if strobe is given.
99 writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
101 /* increment the rx_to_read index to next location */
102 rx_desc->rx_to_read = (rx_desc->rx_to_read + 1)
103 & (rx_desc->rx_ring_size - 1);
105 debug("Rx next pkt location: %d\n", rx_desc->rx_to_read);
111 * HIF Tx interface function
112 * This function sends a single packet to PFE from HIF interface.
113 * - No interrupt indication on tx completion.
114 * - Data is copied to tx buffers before tx descriptor is updated
115 * and TX DMA is enabled.
117 * @param[in] phy_port Phy port number to send out this packet
118 * @param[in] data Pointer to the data
119 * @param[in] length Length of the ethernet packet to be transferred.
121 * @return -1 if tx Q is full, else returns the tx location where the pkt is
124 int pfe_send(int phy_port, void *data, int length)
126 struct tx_desc_s *tx_desc = g_tx_desc;
128 struct hif_header_s hif_header;
131 debug("%s:pkt: %p, len: %d, tx_base: %p, tx_to_send: %d\n", __func__,
132 data, length, tx_desc->tx_base, tx_desc->tx_to_send);
134 bd = tx_desc->tx_base + tx_desc->tx_to_send;
136 /* check queue-full condition */
137 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
140 /* PFE checks for min pkt size */
141 if (length < MIN_PKT_SIZE)
142 length = MIN_PKT_SIZE;
144 tx_buf_va = (void *)DDR_PFE_TO_VIRT(readl(&bd->data));
145 debug("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va,
148 /* Fill the gemac/phy port number to send this packet out */
149 memset(&hif_header, 0, sizeof(struct hif_header_s));
150 hif_header.port_no = phy_port;
152 memcpy(tx_buf_va, (u8 *)&hif_header, sizeof(struct hif_header_s));
153 memcpy(tx_buf_va + sizeof(struct hif_header_s), data, length);
154 length += sizeof(struct hif_header_s);
159 unsigned char *p = (unsigned char *)tx_buf_va;
161 for (i = 0; i < length; i++) {
164 printf("%02x ", p[i]);
169 debug("Tx Done: status: %08x, ctrl: %08x\n", readl(&bd->status),
172 /* fill the tx desc */
173 writel((u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0xFFFF)),
175 writel(0, &bd->status);
177 writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL);
181 return tx_desc->tx_to_send;
185 * HIF function to check the Tx done
186 * This function will check the tx done indication of the current tx_to_send
188 * if success, moves the tx_to_send to next location.
190 * @return -1 if TX ownership bit is not cleared by hw.
191 * else on success (tx done completion) return zero.
193 int pfe_tx_done(void)
195 struct tx_desc_s *tx_desc = g_tx_desc;
198 debug("%s:tx_base: %p, tx_to_send: %d\n", __func__, tx_desc->tx_base,
199 tx_desc->tx_to_send);
201 bd = tx_desc->tx_base + tx_desc->tx_to_send;
203 /* check queue-full condition */
204 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
207 /* reset the control field */
208 writel(0, &bd->ctrl);
209 writel(0, &bd->status);
211 debug("Tx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
214 /* increment the txtosend index to next location */
215 tx_desc->tx_to_send = (tx_desc->tx_to_send + 1)
216 & (tx_desc->tx_ring_size - 1);
218 debug("Tx next pkt location: %d\n", tx_desc->tx_to_send);
224 * Helper function to dump Rx descriptors.
226 static inline void hif_rx_desc_dump(void)
228 struct buf_desc *bd_va;
230 struct rx_desc_s *rx_desc;
233 printf("%s: HIF Rx desc no init\n", __func__);
238 bd_va = rx_desc->rx_base;
240 debug("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rx_base,
241 rx_desc->rx_base_pa);
242 for (i = 0; i < rx_desc->rx_ring_size; i++) {
243 debug("status: %08x, ctrl: %08x, data: %08x, next: 0x%08x\n",
244 readl(&bd_va->status),
247 readl(&bd_va->next));
253 * This function mark all Rx descriptors as LAST_BD.
255 void hif_rx_desc_disable(void)
258 struct rx_desc_s *rx_desc;
259 struct buf_desc *bd_va;
262 printf("%s: HIF Rx desc not initialized\n", __func__);
267 bd_va = rx_desc->rx_base;
269 for (i = 0; i < rx_desc->rx_ring_size; i++) {
270 writel(readl(&bd_va->ctrl) | BD_CTRL_LAST_BD, &bd_va->ctrl);
276 * HIF Rx Desc initialization function.
278 static int hif_rx_desc_init(struct pfe_ddr_address *pfe_addr)
281 struct buf_desc *bd_va;
282 struct buf_desc *bd_pa;
283 struct rx_desc_s *rx_desc;
289 printf("%s: HIF Rx desc re-init request\n", __func__);
293 rx_desc = (struct rx_desc_s *)malloc(sizeof(struct rx_desc_s));
295 printf("%s: Memory allocation failure\n", __func__);
298 memset(rx_desc, 0, sizeof(struct rx_desc_s));
300 /* init: Rx ring buffer */
301 rx_desc->rx_ring_size = HIF_RX_DESC_NT;
303 /* NOTE: must be 64bit aligned */
304 bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
306 bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
309 rx_desc->rx_base = bd_va;
310 rx_desc->rx_base_pa = (unsigned long)bd_pa;
312 rx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR;
314 debug("%s: Rx desc base: %p, base_pa: %08x, desc_count: %d\n",
315 __func__, rx_desc->rx_base, rx_desc->rx_base_pa,
316 rx_desc->rx_ring_size);
318 memset(bd_va, 0, sizeof(struct buf_desc) * rx_desc->rx_ring_size);
320 ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
322 for (i = 0; i < rx_desc->rx_ring_size; i++) {
323 writel((unsigned long)(bd_pa + 1), &bd_va->next);
324 writel(ctrl, &bd_va->ctrl);
325 writel(rx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
330 writel((u32)rx_desc->rx_base_pa, &bd_va->next);
332 writel(rx_desc->rx_base_pa, HIF_RX_BDP_ADDR);
333 writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
341 * Helper function to dump Tx Descriptors.
343 static inline void hif_tx_desc_dump(void)
345 struct tx_desc_s *tx_desc;
347 struct buf_desc *bd_va;
350 printf("%s: HIF Tx desc no init\n", __func__);
355 bd_va = tx_desc->tx_base;
357 debug("HIF tx desc: base_va: %p, base_pa: %08x\n", tx_desc->tx_base,
358 tx_desc->tx_base_pa);
360 for (i = 0; i < tx_desc->tx_ring_size; i++)
365 * HIF Tx descriptor initialization function.
367 static int hif_tx_desc_init(struct pfe_ddr_address *pfe_addr)
369 struct buf_desc *bd_va;
370 struct buf_desc *bd_pa;
372 struct tx_desc_s *tx_desc;
377 printf("%s: HIF Tx desc re-init request\n", __func__);
381 tx_desc = (struct tx_desc_s *)malloc(sizeof(struct tx_desc_s));
383 printf("%s:%d:Memory allocation failure\n", __func__,
387 memset(tx_desc, 0, sizeof(struct tx_desc_s));
389 /* init: Tx ring buffer */
390 tx_desc->tx_ring_size = HIF_TX_DESC_NT;
392 /* NOTE: must be 64bit aligned */
393 bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
395 bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
398 tx_desc->tx_base_pa = (unsigned long)bd_pa;
399 tx_desc->tx_base = bd_va;
401 debug("%s: Tx desc_base: %p, base_pa: %08x, desc_count: %d\n",
402 __func__, tx_desc->tx_base, tx_desc->tx_base_pa,
403 tx_desc->tx_ring_size);
405 memset(bd_va, 0, sizeof(struct buf_desc) * tx_desc->tx_ring_size);
407 tx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
409 for (i = 0; i < tx_desc->tx_ring_size; i++) {
410 writel((unsigned long)(bd_pa + 1), &bd_va->next);
411 writel(tx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
416 writel((u32)tx_desc->tx_base_pa, &bd_va->next);
418 writel(tx_desc->tx_base_pa, HIF_TX_BDP_ADDR);
426 * PFE/Class initialization.
428 static void pfe_class_init(struct pfe_ddr_address *pfe_addr)
430 struct class_cfg class_cfg = {
431 .route_table_baseaddr = pfe_addr->ddr_pfe_phys_baseaddr +
432 ROUTE_TABLE_BASEADDR,
433 .route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
436 class_init(&class_cfg);
438 debug("class init complete\n");
442 * PFE/TMU initialization.
444 static void pfe_tmu_init(struct pfe_ddr_address *pfe_addr)
446 struct tmu_cfg tmu_cfg = {
447 .llm_base_addr = pfe_addr->ddr_pfe_phys_baseaddr
449 .llm_queue_len = TMU_LLM_QUEUE_LEN,
454 debug("tmu init complete\n");
458 * PFE/BMU (both BMU1 & BMU2) initialization.
460 static void pfe_bmu_init(struct pfe_ddr_address *pfe_addr)
462 struct bmu_cfg bmu1_cfg = {
463 .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR +
465 .count = BMU1_BUF_COUNT,
466 .size = BMU1_BUF_SIZE,
469 struct bmu_cfg bmu2_cfg = {
470 .baseaddr = pfe_addr->ddr_pfe_phys_baseaddr + BMU2_DDR_BASEADDR,
471 .count = BMU2_BUF_COUNT,
472 .size = BMU2_BUF_SIZE,
475 bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
476 debug("bmu1 init: done\n");
478 bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
479 debug("bmu2 init: done\n");
483 * PFE/GPI initialization function.
484 * - egpi1, egpi2, egpi3, hgpi
486 static void pfe_gpi_init(struct pfe_ddr_address *pfe_addr)
488 struct gpi_cfg egpi1_cfg = {
489 .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
490 .tmlf_txthres = EGPI1_TMLF_TXTHRES,
491 .aseq_len = EGPI1_ASEQ_LEN,
494 struct gpi_cfg egpi2_cfg = {
495 .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
496 .tmlf_txthres = EGPI2_TMLF_TXTHRES,
497 .aseq_len = EGPI2_ASEQ_LEN,
500 struct gpi_cfg hgpi_cfg = {
501 .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
502 .tmlf_txthres = HGPI_TMLF_TXTHRES,
503 .aseq_len = HGPI_ASEQ_LEN,
506 gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
507 debug("GPI1 init complete\n");
509 gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
510 debug("GPI2 init complete\n");
512 gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
513 debug("HGPI init complete\n");
517 * PFE/HIF initialization function.
519 static int pfe_hif_init(struct pfe_ddr_address *pfe_addr)
526 ret = hif_tx_desc_init(pfe_addr);
529 ret = hif_rx_desc_init(pfe_addr);
541 debug("HIF init complete\n");
547 * - Firmware loading (CLASS-PE and TMU-PE)
548 * - BMU1 and BMU2 init
553 * - HIF tx and rx descriptors init
555 * @param[in] edev Pointer to eth device structure.
557 * @return 0, on success.
559 static int pfe_hw_init(struct pfe_ddr_address *pfe_addr)
563 debug("%s: start\n", __func__);
565 writel(0x3, CLASS_PE_SYS_CLK_RATIO);
566 writel(0x3, TMU_PE_SYS_CLK_RATIO);
567 writel(0x3, UTIL_PE_SYS_CLK_RATIO);
570 pfe_class_init(pfe_addr);
572 pfe_tmu_init(pfe_addr);
574 pfe_bmu_init(pfe_addr);
576 pfe_gpi_init(pfe_addr);
578 ret = pfe_hif_init(pfe_addr);
582 bmu_enable(BMU1_BASE_ADDR);
583 debug("bmu1 enabled\n");
585 bmu_enable(BMU2_BASE_ADDR);
586 debug("bmu2 enabled\n");
588 debug("%s: done\n", __func__);
594 * PFE driver init function.
595 * - Initializes pfe_lib
597 * - fw loading and enables PEs
598 * - should be executed once.
600 * @param[in] pfe Pointer the pfe control block
602 int pfe_drv_init(struct pfe_ddr_address *pfe_addr)
608 ret = pfe_hw_init(pfe_addr);
612 /* Load the class,TM, Util fw.
614 * - out of reset + disabled + configured.
615 * Fw loading should be done after pfe_hw_init()
617 /* It loads default inbuilt sbl firmware */
624 * PFE remove function
626 * - frees tx/rx descriptor resources
627 * - should be called once.
629 * @param[in] pfe Pointer to pfe control block.
631 int pfe_eth_remove(struct udevice *dev)