2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
4 * This driver for AMD PCnet network controllers is derived from the
5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
36 #if PCNET_DEBUG_LEVEL > 0
37 #define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args)
38 #if PCNET_DEBUG_LEVEL > 1
39 #define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args)
41 #define PCNET_DEBUG2(fmt,args...)
44 #define PCNET_DEBUG1(fmt,args...)
45 #define PCNET_DEBUG2(fmt,args...)
48 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
49 #error "Macro for PCnet chip version is not defined!"
53 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
54 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
55 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
57 #define PCNET_LOG_TX_BUFFERS 0
58 #define PCNET_LOG_RX_BUFFERS 2
60 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
61 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
63 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
64 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
66 #define PKT_BUF_SZ 1544
68 /* The PCNET Rx and Tx ring descriptors. */
69 struct pcnet_rx_head {
77 struct pcnet_tx_head {
85 /* The PCNET 32-Bit initialization block, described in databook. */
86 struct pcnet_init_block {
92 /* Receive and transmit ring base, along with extra bits. */
98 typedef struct pcnet_priv {
99 struct pcnet_rx_head rx_ring[RX_RING_SIZE];
100 struct pcnet_tx_head tx_ring[TX_RING_SIZE];
101 struct pcnet_init_block init_block;
102 /* Receive Buffer space */
103 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
108 static pcnet_priv_t *lp;
110 /* Offsets from base I/O address for WIO mode */
111 #define PCNET_RDP 0x10
112 #define PCNET_RAP 0x12
113 #define PCNET_RESET 0x14
114 #define PCNET_BDP 0x16
116 static u16 pcnet_read_csr (struct eth_device *dev, int index)
118 outw (index, dev->iobase + PCNET_RAP);
119 return inw (dev->iobase + PCNET_RDP);
122 static void pcnet_write_csr (struct eth_device *dev, int index, u16 val)
124 outw (index, dev->iobase + PCNET_RAP);
125 outw (val, dev->iobase + PCNET_RDP);
128 static u16 pcnet_read_bcr (struct eth_device *dev, int index)
130 outw (index, dev->iobase + PCNET_RAP);
131 return inw (dev->iobase + PCNET_BDP);
134 static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val)
136 outw (index, dev->iobase + PCNET_RAP);
137 outw (val, dev->iobase + PCNET_BDP);
140 static void pcnet_reset (struct eth_device *dev)
142 inw (dev->iobase + PCNET_RESET);
145 static int pcnet_check (struct eth_device *dev)
147 outw (88, dev->iobase + PCNET_RAP);
148 return (inw (dev->iobase + PCNET_RAP) == 88);
151 static int pcnet_init (struct eth_device *dev, bd_t * bis);
152 static int pcnet_send (struct eth_device *dev, volatile void *packet,
154 static int pcnet_recv (struct eth_device *dev);
155 static void pcnet_halt (struct eth_device *dev);
156 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
158 #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a))
159 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
161 static struct pci_device_id supported[] = {
162 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
167 int pcnet_initialize (bd_t * bis)
170 struct eth_device *dev;
174 PCNET_DEBUG1 ("\npcnet_initialize...\n");
176 for (dev_nr = 0;; dev_nr++) {
179 * Find the PCnet PCI device(s).
181 if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) {
186 * Allocate and pre-fill the device structure.
188 dev = (struct eth_device *) malloc (sizeof *dev);
189 dev->priv = (void *) devbusfn;
190 sprintf (dev->name, "pcnet#%d", dev_nr);
193 * Setup the PCI device.
195 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
196 (unsigned int *) &dev->iobase);
197 dev->iobase=pci_io_to_phys (devbusfn, dev->iobase);
200 PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ",
201 dev->name, devbusfn, dev->iobase);
203 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
204 pci_write_config_word (devbusfn, PCI_COMMAND, command);
205 pci_read_config_word (devbusfn, PCI_COMMAND, &status);
206 if ((status & command) != command) {
207 printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name);
212 pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40);
215 * Probe the PCnet chip.
217 if (pcnet_probe (dev, bis, dev_nr) < 0) {
223 * Setup device structure and register the driver.
225 dev->init = pcnet_init;
226 dev->halt = pcnet_halt;
227 dev->send = pcnet_send;
228 dev->recv = pcnet_recv;
238 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr)
243 #ifdef PCNET_HAS_PROM
247 /* Reset the PCnet controller */
250 /* Check if register access is working */
251 if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) {
252 printf ("%s: CSR register access check failed\n", dev->name);
256 /* Identify the chip */
258 pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16);
259 if ((chip_version & 0xfff) != 0x003)
261 chip_version = (chip_version >> 12) & 0xffff;
262 switch (chip_version) {
264 chipname = "PCnet/PCI II 79C970A"; /* PCI */
266 #ifdef CONFIG_PCNET_79C973
268 chipname = "PCnet/FAST III 79C973"; /* PCI */
271 #ifdef CONFIG_PCNET_79C975
273 chipname = "PCnet/FAST III 79C975"; /* PCI */
277 printf ("%s: PCnet version %#x not supported\n",
278 dev->name, chip_version);
282 PCNET_DEBUG1 ("AMD %s\n", chipname);
284 #ifdef PCNET_HAS_PROM
286 * In most chips, after a chip reset, the ethernet address is read from
287 * the station address PROM at the base address and programmed into the
288 * "Physical Address Registers" CSR12-14.
290 for (i = 0; i < 3; i++) {
293 val = pcnet_read_csr (dev, i + 12) & 0x0ffff;
294 /* There may be endianness issues here. */
295 dev->enetaddr[2 * i] = val & 0x0ff;
296 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
298 #endif /* PCNET_HAS_PROM */
303 static int pcnet_init (struct eth_device *dev, bd_t * bis)
308 PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name);
310 /* Switch pcnet to 32bit mode */
311 pcnet_write_bcr (dev, 20, 2);
314 /* Setup LED registers */
315 val = pcnet_read_bcr (dev, 2) | 0x1000;
316 pcnet_write_bcr (dev, 2, val); /* enable LEDPE */
317 pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */
318 pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */
319 pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */
320 pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */
323 /* Set/reset autoselect bit */
324 val = pcnet_read_bcr (dev, 2) & ~2;
326 pcnet_write_bcr (dev, 2, val);
328 /* Enable auto negotiate, setup, disable fd */
329 val = pcnet_read_bcr (dev, 32) & ~0x98;
331 pcnet_write_bcr (dev, 32, val);
334 * We only maintain one structure because the drivers will never
335 * be used concurrently. In 32bit mode the RX and TX ring entries
336 * must be aligned on 16-byte boundaries.
339 addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10);
340 addr = (addr + 0xf) & ~0xf;
341 lp = (pcnet_priv_t *) addr;
344 lp->init_block.mode = cpu_to_le16 (0x0000);
345 lp->init_block.filter[0] = 0x00000000;
346 lp->init_block.filter[1] = 0x00000000;
349 * Initialize the Rx ring.
352 for (i = 0; i < RX_RING_SIZE; i++) {
353 lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]);
354 lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ);
355 lp->rx_ring[i].status = cpu_to_le16 (0x8000);
357 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
358 lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
359 lp->rx_ring[i].status);
363 * Initialize the Tx ring. The Tx buffer address is filled in as
364 * needed, but we do need to clear the upper ownership bit.
367 for (i = 0; i < TX_RING_SIZE; i++) {
368 lp->tx_ring[i].base = 0;
369 lp->tx_ring[i].status = 0;
375 PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block);
377 for (i = 0; i < 6; i++) {
378 lp->init_block.phys_addr[i] = dev->enetaddr[i];
379 PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]);
382 lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS |
384 lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring);
385 lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring);
387 PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
388 lp->init_block.tlen_rlen,
389 lp->init_block.rx_ring, lp->init_block.tx_ring);
392 * Tell the controller where the Init Block is located.
394 addr = PCI_TO_MEM (dev, &lp->init_block);
395 pcnet_write_csr (dev, 1, addr & 0xffff);
396 pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff);
398 pcnet_write_csr (dev, 4, 0x0915);
399 pcnet_write_csr (dev, 0, 0x0001); /* start */
401 /* Wait for Init Done bit */
402 for (i = 10000; i > 0; i--) {
403 if (pcnet_read_csr (dev, 0) & 0x0100)
408 printf ("%s: TIMEOUT: controller init failed\n", dev->name);
414 * Finally start network controller operation.
416 pcnet_write_csr (dev, 0, 0x0002);
421 static int pcnet_send (struct eth_device *dev, volatile void *packet,
425 struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
427 PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
430 /* Wait for completion by testing the OWN bit */
431 for (i = 1000; i > 0; i--) {
432 status = le16_to_cpu (entry->status);
433 if ((status & 0x8000) == 0)
439 printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
440 dev->name, lp->cur_tx, status);
446 * Setup Tx ring. Caution: the write order is important here,
447 * set the status with the "ownership" bits last.
450 entry->length = le16_to_cpu (-pkt_len);
451 entry->misc = 0x00000000;
452 entry->base = PCI_TO_MEM_LE (dev, packet);
453 entry->status = le16_to_cpu (status);
455 /* Trigger an immediate send poll. */
456 pcnet_write_csr (dev, 0, 0x0008);
459 if (++lp->cur_tx >= TX_RING_SIZE)
462 PCNET_DEBUG2 ("done\n");
466 static int pcnet_recv (struct eth_device *dev)
468 struct pcnet_rx_head *entry;
473 entry = &lp->rx_ring[lp->cur_rx];
475 * If we own the next entry, it's a new packet. Send it up.
477 if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) {
482 if (status != 0x03) { /* There was an error. */
484 printf ("%s: Rx%d", dev->name, lp->cur_rx);
485 PCNET_DEBUG1 (" (status=0x%x)", status);
489 printf (" Overflow");
495 entry->status &= le16_to_cpu (0x03ff);
500 (le32_to_cpu (entry->msg_length) & 0xfff) - 4;
502 printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len);
504 NetReceive (lp->rx_buf[lp->cur_rx], pkt_len);
505 PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n",
507 lp->rx_buf[lp->cur_rx]);
510 entry->status |= cpu_to_le16 (0x8000);
512 if (++lp->cur_rx >= RX_RING_SIZE)
518 static void pcnet_halt (struct eth_device *dev)
522 PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name);
524 /* Reset the PCnet controller */
527 /* Wait for Stop bit */
528 for (i = 1000; i > 0; i--) {
529 if (pcnet_read_csr (dev, 0) & 0x4)
534 printf ("%s: TIMEOUT: controller reset failed\n", dev->name);