drivers/net/pch_gbe.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   4  *
   5  * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <malloc.h>
  13 #include <asm/io.h>
  14 #include <pci.h>
  15 #include <miiphy.h>
  16 #include "pch_gbe.h"
  17
  18 #if !defined(CONFIG_PHYLIB)
  19 # error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB"
  20 #endif
  21
  22 static struct pci_device_id supported[] = {
  23         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_GBE) },
  24         { }
  25 };
  26
  27 static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr)
  28 {
  29         u32 macid_hi, macid_lo;
  30
  31         macid_hi = readl(&mac_regs->mac_adr[0].high);
  32         macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff;
  33         debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo);
  34
  35         addr[0] = (u8)(macid_hi & 0xff);
  36         addr[1] = (u8)((macid_hi >> 8) & 0xff);
  37         addr[2] = (u8)((macid_hi >> 16) & 0xff);
  38         addr[3] = (u8)((macid_hi >> 24) & 0xff);
  39         addr[4] = (u8)(macid_lo & 0xff);
  40         addr[5] = (u8)((macid_lo >> 8) & 0xff);
  41 }
  42
  43 static int pch_gbe_mac_write(struct pch_gbe_regs *mac_regs, u8 *addr)
  44 {
  45         u32 macid_hi, macid_lo;
  46         ulong start;
  47
  48         macid_hi = addr[0] + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24);
  49         macid_lo = addr[4] + (addr[5] << 8);
  50
  51         writel(macid_hi, &mac_regs->mac_adr[0].high);
  52         writel(macid_lo, &mac_regs->mac_adr[0].low);
  53         writel(0xfffe, &mac_regs->addr_mask);
  54
  55         start = get_timer(0);
  56         while (get_timer(start) < PCH_GBE_TIMEOUT) {
  57                 if (!(readl(&mac_regs->addr_mask) & PCH_GBE_BUSY))
  58                         return 0;
  59
  60                 udelay(10);
  61         }
  62
  63         return -ETIME;
  64 }
  65
  66 static int pch_gbe_reset(struct udevice *dev)
  67 {
  68         struct pch_gbe_priv *priv = dev_get_priv(dev);
  69         struct eth_pdata *plat = dev_get_platdata(dev);
  70         struct pch_gbe_regs *mac_regs = priv->mac_regs;
  71         ulong start;
  72
  73         priv->rx_idx = 0;
  74         priv->tx_idx = 0;
  75
  76         writel(PCH_GBE_ALL_RST, &mac_regs->reset);
  77
  78         /*
  79          * Configure the MAC to RGMII mode after reset
  80          *
  81          * For some unknown reason, we must do the configuration here right
  82          * after resetting the whole MAC, otherwise the reset bit in the RESET
  83          * register will never be cleared by the hardware. And there is another
  84          * way of having the same magic, that is to configure the MODE register
  85          * to have the MAC work in MII/GMII mode, which is how current Linux
  86          * pch_gbe driver does. Since anyway we need program the MAC to RGMII
  87          * mode in the driver, we just do it here.
  88          *
  89          * Note: this behavior is not documented in the hardware manual.
  90          */
  91         writel(PCH_GBE_RGMII_MODE_RGMII | PCH_GBE_CHIP_TYPE_INTERNAL,
  92                &mac_regs->rgmii_ctrl);
  93
  94         start = get_timer(0);
  95         while (get_timer(start) < PCH_GBE_TIMEOUT) {
  96                 if (!(readl(&mac_regs->reset) & PCH_GBE_ALL_RST)) {
  97                         /*
  98                          * Soft reset clears hardware MAC address registers,
  99                          * so we have to reload MAC address here in order to
 100                          * make linux pch_gbe driver happy.
 101                          */
 102                         return pch_gbe_mac_write(mac_regs, plat->enetaddr);
 103                 }
 104
 105                 udelay(10);
 106         }
 107
 108         debug("pch_gbe: reset timeout\n");
 109         return -ETIME;
 110 }
 111
 112 static void pch_gbe_rx_descs_init(struct udevice *dev)
 113 {
 114         struct pch_gbe_priv *priv = dev_get_priv(dev);
 115         struct pch_gbe_regs *mac_regs = priv->mac_regs;
 116         struct pch_gbe_rx_desc *rx_desc = &priv->rx_desc[0];
 117         int i;
 118
 119         memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
 120         for (i = 0; i < PCH_GBE_DESC_NUM; i++)
 121                 rx_desc[i].buffer_addr = dm_pci_virt_to_mem(priv->dev,
 122                         priv->rx_buff[i]);
 123
 124         flush_dcache_range((ulong)rx_desc, (ulong)&rx_desc[PCH_GBE_DESC_NUM]);
 125
 126         writel(dm_pci_virt_to_mem(priv->dev, rx_desc),
 127                &mac_regs->rx_dsc_base);
 128         writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
 129                &mac_regs->rx_dsc_size);
 130
 131         writel(dm_pci_virt_to_mem(priv->dev, rx_desc + 1),
 132                &mac_regs->rx_dsc_sw_p);
 133 }
 134
 135 static void pch_gbe_tx_descs_init(struct udevice *dev)
 136 {
 137         struct pch_gbe_priv *priv = dev_get_priv(dev);
 138         struct pch_gbe_regs *mac_regs = priv->mac_regs;
 139         struct pch_gbe_tx_desc *tx_desc = &priv->tx_desc[0];
 140
 141         memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
 142
 143         flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[PCH_GBE_DESC_NUM]);
 144
 145         writel(dm_pci_virt_to_mem(priv->dev, tx_desc),
 146                &mac_regs->tx_dsc_base);
 147         writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
 148                &mac_regs->tx_dsc_size);
 149         writel(dm_pci_virt_to_mem(priv->dev, tx_desc + 1),
 150                &mac_regs->tx_dsc_sw_p);
 151 }
 152
 153 static void pch_gbe_adjust_link(struct pch_gbe_regs *mac_regs,
 154                                 struct phy_device *phydev)
 155 {
 156         if (!phydev->link) {
 157                 printf("%s: No link.\n", phydev->dev->name);
 158                 return;
 159         }
 160
 161         clrbits_le32(&mac_regs->rgmii_ctrl,
 162                      PCH_GBE_RGMII_RATE_2_5M | PCH_GBE_CRS_SEL);
 163         clrbits_le32(&mac_regs->mode,
 164                      PCH_GBE_MODE_GMII_ETHER | PCH_GBE_MODE_FULL_DUPLEX);
 165
 166         switch (phydev->speed) {
 167         case 1000:
 168                 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_125M);
 169                 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_GMII_ETHER);
 170                 break;
 171         case 100:
 172                 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_25M);
 173                 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
 174                 break;
 175         case 10:
 176                 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_2_5M);
 177                 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
 178                 break;
 179         }
 180
 181         if (phydev->duplex) {
 182                 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_CRS_SEL);
 183                 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_FULL_DUPLEX);
 184         }
 185
 186         printf("Speed: %d, %s duplex\n", phydev->speed,
 187                (phydev->duplex) ? "full" : "half");
 188
 189         return;
 190 }
 191
 192 static int pch_gbe_start(struct udevice *dev)
 193 {
 194         struct pch_gbe_priv *priv = dev_get_priv(dev);
 195         struct pch_gbe_regs *mac_regs = priv->mac_regs;
 196
 197         if (pch_gbe_reset(dev))
 198                 return -1;
 199
 200         pch_gbe_rx_descs_init(dev);
 201         pch_gbe_tx_descs_init(dev);
 202
 203         /* Enable frame bursting */
 204         writel(PCH_GBE_MODE_FR_BST, &mac_regs->mode);
 205         /* Disable TCP/IP accelerator */
 206         writel(PCH_GBE_RX_TCPIPACC_OFF, &mac_regs->tcpip_acc);
 207         /* Disable RX flow control */
 208         writel(0, &mac_regs->rx_fctrl);
 209         /* Configure RX/TX mode */
 210         writel(PCH_GBE_RH_ALM_EMP_16 | PCH_GBE_RH_ALM_FULL_16 |
 211                PCH_GBE_RH_RD_TRG_32, &mac_regs->rx_mode);
 212         writel(PCH_GBE_TM_TH_TX_STRT_32 | PCH_GBE_TM_TH_ALM_EMP_16 |
 213                PCH_GBE_TM_TH_ALM_FULL_32 | PCH_GBE_TM_ST_AND_FD |
 214                PCH_GBE_TM_SHORT_PKT, &mac_regs->tx_mode);
 215
 216         /* Start up the PHY */
 217         if (phy_startup(priv->phydev)) {
 218                 printf("Could not initialize PHY %s\n",
 219                        priv->phydev->dev->name);
 220                 return -1;
 221         }
 222
 223         pch_gbe_adjust_link(mac_regs, priv->phydev);
 224
 225         if (!priv->phydev->link)
 226                 return -1;
 227
 228         /* Enable TX & RX */
 229         writel(PCH_GBE_RX_DMA_EN | PCH_GBE_TX_DMA_EN, &mac_regs->dma_ctrl);
 230         writel(PCH_GBE_MRE_MAC_RX_EN, &mac_regs->mac_rx_en);
 231
 232         return 0;
 233 }
 234
 235 static void pch_gbe_stop(struct udevice *dev)
 236 {
 237         struct pch_gbe_priv *priv = dev_get_priv(dev);
 238
 239         pch_gbe_reset(dev);
 240
 241         phy_shutdown(priv->phydev);
 242 }
 243
 244 static int pch_gbe_send(struct udevice *dev, void *packet, int length)
 245 {
 246         struct pch_gbe_priv *priv = dev_get_priv(dev);
 247         struct pch_gbe_regs *mac_regs = priv->mac_regs;
 248         struct pch_gbe_tx_desc *tx_head, *tx_desc;
 249         u16 frame_ctrl = 0;
 250         u32 int_st;
 251         ulong start;
 252
 253         flush_dcache_range((ulong)packet, (ulong)packet + length);
 254
 255         tx_head = &priv->tx_desc[0];
 256         tx_desc = &priv->tx_desc[priv->tx_idx];
 257
 258         if (length < 64)
 259                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
 260
 261         tx_desc->buffer_addr = dm_pci_virt_to_mem(priv->dev, packet);
 262         tx_desc->length = length;
 263         tx_desc->tx_words_eob = length + 3;
 264         tx_desc->tx_frame_ctrl = frame_ctrl;
 265         tx_desc->dma_status = 0;
 266         tx_desc->gbec_status = 0;
 267
 268         flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[1]);
 269
 270         /* Test the wrap-around condition */
 271         if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
 272                 priv->tx_idx = 0;
 273
 274         writel(dm_pci_virt_to_mem(priv->dev, tx_head + priv->tx_idx),
 275                &mac_regs->tx_dsc_sw_p);
 276
 277         start = get_timer(0);
 278         while (get_timer(start) < PCH_GBE_TIMEOUT) {
 279                 int_st = readl(&mac_regs->int_st);
 280                 if (int_st & PCH_GBE_INT_TX_CMPLT)
 281                         return 0;
 282
 283                 udelay(10);
 284         }
 285
 286         debug("pch_gbe: sent failed\n");
 287         return -ETIME;
 288 }
 289
 290 static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp)
 291 {
 292         struct pch_gbe_priv *priv = dev_get_priv(dev);
 293         struct pch_gbe_regs *mac_regs = priv->mac_regs;
 294         struct pch_gbe_rx_desc *rx_desc;
 295         ulong hw_desc, length;
 296         void *buffer;
 297
 298         rx_desc = &priv->rx_desc[priv->rx_idx];
 299
 300         readl(&mac_regs->int_st);
 301         hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
 302
 303         /* Just return if not receiving any packet */
 304         if (virt_to_phys(rx_desc) == hw_desc)
 305                 return -EAGAIN;
 306
 307         /* Invalidate the descriptor */
 308         invalidate_dcache_range((ulong)rx_desc, (ulong)&rx_desc[1]);
 309
 310         length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
 311         buffer = dm_pci_mem_to_virt(priv->dev, rx_desc->buffer_addr, length, 0);
 312         invalidate_dcache_range((ulong)buffer, (ulong)buffer + length);
 313         *packetp = (uchar *)buffer;
 314
 315         return length;
 316 }
 317
 318 static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length)
 319 {
 320         struct pch_gbe_priv *priv = dev_get_priv(dev);
 321         struct pch_gbe_regs *mac_regs = priv->mac_regs;
 322         struct pch_gbe_rx_desc *rx_head = &priv->rx_desc[0];
 323         int rx_swp;
 324
 325         /* Test the wrap-around condition */
 326         if (++priv->rx_idx >= PCH_GBE_DESC_NUM)
 327                 priv->rx_idx = 0;
 328         rx_swp = priv->rx_idx;
 329         if (++rx_swp >= PCH_GBE_DESC_NUM)
 330                 rx_swp = 0;
 331
 332         writel(dm_pci_virt_to_mem(priv->dev, rx_head + rx_swp),
 333                &mac_regs->rx_dsc_sw_p);
 334
 335         return 0;
 336 }
 337
 338 static int pch_gbe_mdio_ready(struct pch_gbe_regs *mac_regs)
 339 {
 340         ulong start = get_timer(0);
 341
 342         while (get_timer(start) < PCH_GBE_TIMEOUT) {
 343                 if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY)
 344                         return 0;
 345
 346                 udelay(10);
 347         }
 348
 349         return -ETIME;
 350 }
 351
 352 static int pch_gbe_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 353 {
 354         struct pch_gbe_regs *mac_regs = bus->priv;
 355         u32 miim;
 356
 357         if (pch_gbe_mdio_ready(mac_regs))
 358                 return -ETIME;
 359
 360         miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
 361                (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
 362                PCH_GBE_MIIM_OPER_READ;
 363         writel(miim, &mac_regs->miim);
 364
 365         if (pch_gbe_mdio_ready(mac_regs))
 366                 return -ETIME;
 367
 368         return readl(&mac_regs->miim) & 0xffff;
 369 }
 370
 371 static int pch_gbe_mdio_write(struct mii_dev *bus, int addr, int devad,
 372                               int reg, u16 val)
 373 {
 374         struct pch_gbe_regs *mac_regs = bus->priv;
 375         u32 miim;
 376
 377         if (pch_gbe_mdio_ready(mac_regs))
 378                 return -ETIME;
 379
 380         miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
 381                (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
 382                PCH_GBE_MIIM_OPER_WRITE | val;
 383         writel(miim, &mac_regs->miim);
 384
 385         if (pch_gbe_mdio_ready(mac_regs))
 386                 return -ETIME;
 387         else
 388                 return 0;
 389 }
 390
 391 static int pch_gbe_mdio_init(const char *name, struct pch_gbe_regs *mac_regs)
 392 {
 393         struct mii_dev *bus;
 394
 395         bus = mdio_alloc();
 396         if (!bus) {
 397                 debug("pch_gbe: failed to allocate MDIO bus\n");
 398                 return -ENOMEM;
 399         }
 400
 401         bus->read = pch_gbe_mdio_read;
 402         bus->write = pch_gbe_mdio_write;
 403         strcpy(bus->name, name);
 404
 405         bus->priv = (void *)mac_regs;
 406
 407         return mdio_register(bus);
 408 }
 409
 410 static int pch_gbe_phy_init(struct udevice *dev)
 411 {
 412         struct pch_gbe_priv *priv = dev_get_priv(dev);
 413         struct eth_pdata *plat = dev_get_platdata(dev);
 414         struct phy_device *phydev;
 415         int mask = 0xffffffff;
 416
 417         phydev = phy_find_by_mask(priv->bus, mask, plat->phy_interface);
 418         if (!phydev) {
 419                 printf("pch_gbe: cannot find the phy\n");
 420                 return -1;
 421         }
 422
 423         phy_connect_dev(phydev, dev);
 424
 425         phydev->supported &= PHY_GBIT_FEATURES;
 426         phydev->advertising = phydev->supported;
 427
 428         priv->phydev = phydev;
 429         phy_config(phydev);
 430
 431         return 0;
 432 }
 433
 434 static int pch_gbe_probe(struct udevice *dev)
 435 {
 436         struct pch_gbe_priv *priv;
 437         struct eth_pdata *plat = dev_get_platdata(dev);
 438         void *iobase;
 439         int err;
 440
 441         /*
 442          * The priv structure contains the descriptors and frame buffers which
 443          * need a strict buswidth alignment (64 bytes). This is guaranteed by
 444          * DM_FLAG_ALLOC_PRIV_DMA flag in the U_BOOT_DRIVER.
 445          */
 446         priv = dev_get_priv(dev);
 447
 448         priv->dev = dev;
 449
 450         iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM);
 451
 452         plat->iobase = (ulong)iobase;
 453         priv->mac_regs = (struct pch_gbe_regs *)iobase;
 454
 455         /* Read MAC address from SROM and initialize dev->enetaddr with it */
 456         pch_gbe_mac_read(priv->mac_regs, plat->enetaddr);
 457
 458         plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
 459         pch_gbe_mdio_init(dev->name, priv->mac_regs);
 460         priv->bus = miiphy_get_dev_by_name(dev->name);
 461
 462         err = pch_gbe_reset(dev);
 463         if (err)
 464                 return err;
 465
 466         return pch_gbe_phy_init(dev);
 467 }
 468
 469 static int pch_gbe_remove(struct udevice *dev)
 470 {
 471         struct pch_gbe_priv *priv = dev_get_priv(dev);
 472
 473         free(priv->phydev);
 474         mdio_unregister(priv->bus);
 475         mdio_free(priv->bus);
 476
 477         return 0;
 478 }
 479
 480 static const struct eth_ops pch_gbe_ops = {
 481         .start = pch_gbe_start,
 482         .send = pch_gbe_send,
 483         .recv = pch_gbe_recv,
 484         .free_pkt = pch_gbe_free_pkt,
 485         .stop = pch_gbe_stop,
 486 };
 487
 488 static const struct udevice_id pch_gbe_ids[] = {
 489         { .compatible = "intel,pch-gbe" },
 490         { }
 491 };
 492
 493 U_BOOT_DRIVER(eth_pch_gbe) = {
 494         .name = "pch_gbe",
 495         .id = UCLASS_ETH,
 496         .of_match = pch_gbe_ids,
 497         .probe = pch_gbe_probe,
 498         .remove = pch_gbe_remove,
 499         .ops = &pch_gbe_ops,
 500         .priv_auto_alloc_size = sizeof(struct pch_gbe_priv),
 501         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 502         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 503 };
 504
 505 U_BOOT_PCI_DEVICE(eth_pch_gbe, supported);