2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs
4 /*-----------------------------------------------------------------------------+
8 | Function: This module has utilities for accessing the MII PHY through
15 | Date Description of Change BY
16 | --------- --------------------- ---
17 | 05-May-99 Created MKW
18 | 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to
19 | better match OPB speed. Also modified delay times. JWB
20 | 29-Jul-99 Added Full duplex support MKW
21 | 24-Aug-99 Removed printf from dp83843_duplex() JWB
22 | 19-Jul-00 Ported to esd cpci405 sr
23 | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
24 | <travis.sawyer@sandburst.com>
26 +-----------------------------------------------------------------------------*/
32 #include "IxEthAcc_p.h"
33 #include "IxEthAccMac_p.h"
34 #include "IxEthAccMii_p.h"
36 /***********************************************************/
37 /* Dump out to the screen PHY regs */
38 /***********************************************************/
40 void miiphy_dump (char *devname, unsigned char addr)
46 for (i = 0; i < 0x1A; i++) {
47 if (miiphy_read (devname, addr, i, &data)) {
48 printf ("read error for reg %lx\n", i);
51 printf ("Phy reg %lx ==> %4x\n", i, data);
53 /* jump to the next set of regs */
61 /***********************************************************/
62 /* (Re)start autonegotiation */
63 /***********************************************************/
64 int phy_setup_aneg (char *devname, unsigned char addr)
66 unsigned short ctl, adv;
68 /* Setup standard advertise */
69 miiphy_read (devname, addr, MII_ADVERTISE, &adv);
70 adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 |
71 LPA_100FULL | LPA_100HALF | LPA_10FULL |
73 miiphy_write (devname, addr, MII_ADVERTISE, adv);
75 /* Start/Restart aneg */
76 miiphy_read (devname, addr, MII_BMCR, &ctl);
77 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
78 miiphy_write (devname, addr, MII_BMCR, ctl);
84 int npe_miiphy_read (const char *devname, unsigned char addr,
85 unsigned char reg, unsigned short *value)
89 ixEthAccMiiReadRtn(addr, reg, &val);
96 int npe_miiphy_write (const char *devname, unsigned char addr,
97 unsigned char reg, unsigned short value)
99 ixEthAccMiiWriteRtn(addr, reg, value);