4 * IXP400 SW Release version 2.0
6 * -- Copyright Notice --
9 * Copyright 2001-2005, Intel Corporation.
10 * All rights reserved.
13 * SPDX-License-Identifier: BSD-3-Clause
15 * -- End of Copyright Notice --
19 #ifndef IxEthAccMac_p_H
20 #define IxEthAccMac_p_H
24 #define IX_ETH_ACC_MAX_MULTICAST_ADDRESSES 256
25 #define IX_ETH_ACC_NUM_PORTS 3
26 #define IX_ETH_ACC_MAX_FRAME_SIZE_DEFAULT 1536
27 #define IX_ETH_ACC_MAX_FRAME_SIZE_UPPER_RANGE (65536-64)
28 #define IX_ETH_ACC_MAX_FRAME_SIZE_LOWER_RANGE 64
32 * MAC register definitions
35 #define IX_ETH_ACC_MAC_0_BASE IX_OSAL_IXP400_ETHA_PHYS_BASE
36 #define IX_ETH_ACC_MAC_1_BASE IX_OSAL_IXP400_ETHB_PHYS_BASE
37 #define IX_ETH_ACC_MAC_2_BASE IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE
39 #define IX_ETH_ACC_MAC_TX_CNTRL1 0x000
40 #define IX_ETH_ACC_MAC_TX_CNTRL2 0x004
41 #define IX_ETH_ACC_MAC_RX_CNTRL1 0x010
42 #define IX_ETH_ACC_MAC_RX_CNTRL2 0x014
43 #define IX_ETH_ACC_MAC_RANDOM_SEED 0x020
44 #define IX_ETH_ACC_MAC_THRESH_P_EMPTY 0x030
45 #define IX_ETH_ACC_MAC_THRESH_P_FULL 0x038
46 #define IX_ETH_ACC_MAC_BUF_SIZE_TX 0x040
47 #define IX_ETH_ACC_MAC_TX_DEFER 0x050
48 #define IX_ETH_ACC_MAC_RX_DEFER 0x054
49 #define IX_ETH_ACC_MAC_TX_TWO_DEFER_1 0x060
50 #define IX_ETH_ACC_MAC_TX_TWO_DEFER_2 0x064
51 #define IX_ETH_ACC_MAC_SLOT_TIME 0x070
52 #define IX_ETH_ACC_MAC_MDIO_CMD_1 0x080
53 #define IX_ETH_ACC_MAC_MDIO_CMD_2 0x084
54 #define IX_ETH_ACC_MAC_MDIO_CMD_3 0x088
55 #define IX_ETH_ACC_MAC_MDIO_CMD_4 0x08c
56 #define IX_ETH_ACC_MAC_MDIO_STS_1 0x090
57 #define IX_ETH_ACC_MAC_MDIO_STS_2 0x094
58 #define IX_ETH_ACC_MAC_MDIO_STS_3 0x098
59 #define IX_ETH_ACC_MAC_MDIO_STS_4 0x09c
60 #define IX_ETH_ACC_MAC_ADDR_MASK_1 0x0A0
61 #define IX_ETH_ACC_MAC_ADDR_MASK_2 0x0A4
62 #define IX_ETH_ACC_MAC_ADDR_MASK_3 0x0A8
63 #define IX_ETH_ACC_MAC_ADDR_MASK_4 0x0AC
64 #define IX_ETH_ACC_MAC_ADDR_MASK_5 0x0B0
65 #define IX_ETH_ACC_MAC_ADDR_MASK_6 0x0B4
66 #define IX_ETH_ACC_MAC_ADDR_1 0x0C0
67 #define IX_ETH_ACC_MAC_ADDR_2 0x0C4
68 #define IX_ETH_ACC_MAC_ADDR_3 0x0C8
69 #define IX_ETH_ACC_MAC_ADDR_4 0x0CC
70 #define IX_ETH_ACC_MAC_ADDR_5 0x0D0
71 #define IX_ETH_ACC_MAC_ADDR_6 0x0D4
72 #define IX_ETH_ACC_MAC_INT_CLK_THRESH 0x0E0
73 #define IX_ETH_ACC_MAC_UNI_ADDR_1 0x0F0
74 #define IX_ETH_ACC_MAC_UNI_ADDR_2 0x0F4
75 #define IX_ETH_ACC_MAC_UNI_ADDR_3 0x0F8
76 #define IX_ETH_ACC_MAC_UNI_ADDR_4 0x0FC
77 #define IX_ETH_ACC_MAC_UNI_ADDR_5 0x100
78 #define IX_ETH_ACC_MAC_UNI_ADDR_6 0x104
79 #define IX_ETH_ACC_MAC_CORE_CNTRL 0x1FC
88 /* TX Control Register 1*/
90 #define IX_ETH_ACC_TX_CNTRL1_TX_EN BIT(0)
91 #define IX_ETH_ACC_TX_CNTRL1_DUPLEX BIT(1)
92 #define IX_ETH_ACC_TX_CNTRL1_RETRY BIT(2)
93 #define IX_ETH_ACC_TX_CNTRL1_PAD_EN BIT(3)
94 #define IX_ETH_ACC_TX_CNTRL1_FCS_EN BIT(4)
95 #define IX_ETH_ACC_TX_CNTRL1_2DEFER BIT(5)
96 #define IX_ETH_ACC_TX_CNTRL1_RMII BIT(6)
98 /* TX Control Register 2 */
99 #define IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK 0xf
101 /* RX Control Register 1 */
102 #define IX_ETH_ACC_RX_CNTRL1_RX_EN BIT(0)
103 #define IX_ETH_ACC_RX_CNTRL1_PADSTRIP_EN BIT(1)
104 #define IX_ETH_ACC_RX_CNTRL1_CRC_EN BIT(2)
105 #define IX_ETH_ACC_RX_CNTRL1_PAUSE_EN BIT(3)
106 #define IX_ETH_ACC_RX_CNTRL1_LOOP_EN BIT(4)
107 #define IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN BIT(5)
108 #define IX_ETH_ACC_RX_CNTRL1_RX_RUNT_EN BIT(6)
109 #define IX_ETH_ACC_RX_CNTRL1_BCAST_DIS BIT(7)
111 /* RX Control Register 2 */
112 #define IX_ETH_ACC_RX_CNTRL2_DEFER_EN BIT(0)
116 /* Core Control Register */
117 #define IX_ETH_ACC_CORE_RESET BIT(0)
118 #define IX_ETH_ACC_CORE_RX_FIFO_FLUSH BIT(1)
119 #define IX_ETH_ACC_CORE_TX_FIFO_FLUSH BIT(2)
120 #define IX_ETH_ACC_CORE_SEND_JAM BIT(3)
121 #define IX_ETH_ACC_CORE_MDC_EN BIT(4)
123 /* 1st bit of 1st MAC octet */
124 #define IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ( 1)
134 #define IX_ETH_ACC_TX_CNTRL1_DEFAULT (IX_ETH_ACC_TX_CNTRL1_TX_EN | \
135 IX_ETH_ACC_TX_CNTRL1_RETRY | \
136 IX_ETH_ACC_TX_CNTRL1_FCS_EN | \
137 IX_ETH_ACC_TX_CNTRL1_2DEFER | \
138 IX_ETH_ACC_TX_CNTRL1_PAD_EN)
140 #define IX_ETH_ACC_TX_MAX_RETRIES_DEFAULT 0x0f
142 #define IX_ETH_ACC_RX_CNTRL1_DEFAULT (IX_ETH_ACC_RX_CNTRL1_CRC_EN \
143 | IX_ETH_ACC_RX_CNTRL1_RX_EN)
145 #define IX_ETH_ACC_RX_CNTRL2_DEFAULT 0x0
147 /* Thresholds determined by NPE firmware FS */
148 #define IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT 0x12
149 #define IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT 0x30
151 /* Number of bytes that must be in the tx fifo before
152 transmission commences*/
153 #define IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT 0x8
155 /* One-part deferral values */
156 #define IX_ETH_ACC_MAC_TX_DEFER_DEFAULT 0x15
157 #define IX_ETH_ACC_MAC_RX_DEFER_DEFAULT 0x16
159 /* Two-part deferral values... */
160 #define IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT 0x08
161 #define IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT 0x07
163 /* This value applies to MII */
164 #define IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT 0x80
166 /* This value applies to RMII */
167 #define IX_ETH_ACC_MAC_SLOT_TIME_RMII_DEFAULT 0xFF
169 #define IX_ETH_ACC_MAC_ADDR_MASK_DEFAULT 0xFF
171 #define IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT 0x1
172 /*The following is a value chosen at random*/
173 #define IX_ETH_ACC_RANDOM_SEED_DEFAULT 0x8
175 /*By default we must configure the MAC to generate the
177 #define IX_ETH_ACC_CORE_DEFAULT (IX_ETH_ACC_CORE_MDC_EN)
179 #define IXP425_ETH_ACC_MAX_PHY 2
180 #define IXP425_ETH_ACC_MAX_AN_ENTRIES 20
181 #define IX_ETH_ACC_MAC_RESET_DELAY 1
183 #define IX_ETH_ACC_MAC_ALL_BITS_SET 0xFF
185 #define IX_ETH_ACC_MAC_MSGID_SHL 24
187 #define IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS 20
188 #define IX_ETH_ACC_PORT_DISABLE_DELAY_COUNT 200 /* 4 seconds timeout */
189 #define IX_ETH_ACC_PORT_DISABLE_RETRY_COUNT 3
190 #define IX_ETH_ACC_MIB_STATS_DELAY_MSECS 2000 /* 2 seconds delay for ethernet stats */
192 /*Register access macros*/
193 #if (CPU == SIMSPARCSOLARIS)
194 extern void registerWriteStub (UINT32 base, UINT32 offset, UINT32 val);
195 extern UINT32 registerReadStub (UINT32 base, UINT32 offset);
197 #define REG_WRITE(b,o,v) registerWriteStub(b, o, v)
198 #define REG_READ(b,o,v) do { v = registerReadStub(b, o); } while (0)
200 #define REG_WRITE(b,o,v) IX_OSAL_WRITE_LONG((volatile UINT32 *)(b + o), v)
201 #define REG_READ(b,o,v) (v = IX_OSAL_READ_LONG((volatile UINT32 *)(b + o)))
205 void ixEthAccMacUnload(void);
206 IxEthAccStatus ixEthAccMacMemInit(void);
208 /* MAC core loopback */
209 IxEthAccStatus ixEthAccPortLoopbackEnable(IxEthAccPortId portId);
210 IxEthAccStatus ixEthAccPortLoopbackDisable(IxEthAccPortId portId);
212 /* MAC core traffic control */
213 IxEthAccStatus ixEthAccPortTxEnablePriv(IxEthAccPortId portId);
214 IxEthAccStatus ixEthAccPortTxDisablePriv(IxEthAccPortId portId);
215 IxEthAccStatus ixEthAccPortRxEnablePriv(IxEthAccPortId portId);
216 IxEthAccStatus ixEthAccPortRxDisablePriv(IxEthAccPortId portId);
217 IxEthAccStatus ixEthAccPortMacResetPriv(IxEthAccPortId portId);
219 /* NPE software loopback */
220 IxEthAccStatus ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId);
221 IxEthAccStatus ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId);
223 #endif /*IxEthAccMac_p_H*/