2 * @file IxNpeDlNpeMgrUtils.c
4 * @author Intel Corporation
5 * @date 18 February 2002
7 * @brief This file contains the implementation of the private API for the
8 * IXP425 NPE Downloader NpeMgr Utils module
12 * IXP400 SW Release version 2.0
14 * -- Copyright Notice --
17 * Copyright 2001-2005, Intel Corporation.
18 * All rights reserved.
21 * SPDX-License-Identifier: BSD-3-Clause
23 * -- End of Copyright Notice --
28 * Put the system defined include files required.
30 #define IX_NPE_DL_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of
36 * Put the user defined include files required.
40 #include "IxNpeDlNpeMgrUtils_p.h"
41 #include "IxNpeDlNpeMgrEcRegisters_p.h"
42 #include "IxNpeDlMacros_p.h"
45 * #defines and macros used in this file.
48 /* used to bit-mask a number of bytes */
49 #define IX_NPEDL_MASK_LOWER_BYTE_OF_WORD 0x000000FF
50 #define IX_NPEDL_MASK_LOWER_SHORT_OF_WORD 0x0000FFFF
51 #define IX_NPEDL_MASK_FULL_WORD 0xFFFFFFFF
53 #define IX_NPEDL_BYTES_PER_WORD 4
54 #define IX_NPEDL_BYTES_PER_SHORT 2
56 #define IX_NPEDL_REG_SIZE_BYTE 8
57 #define IX_NPEDL_REG_SIZE_SHORT 16
58 #define IX_NPEDL_REG_SIZE_WORD 32
61 * Introduce extra read cycles after issuing read command to NPE
62 * so that we read the register after the NPE has updated it
63 * This is to overcome race condition between XScale and NPE
65 #define IX_NPEDL_DELAY_READ_CYCLES 2
67 * To mask top three MSBs of 32bit word to download into NPE IMEM
69 #define IX_NPEDL_MASK_UNUSED_IMEM_BITS 0x1FFFFFFF;
79 } IxNpeDlCtxtRegAccessInfo;
81 /* module statistics counters */
85 UINT32 insMemWriteFails;
87 UINT32 dataMemWriteFails;
90 UINT32 dbgInstructionExecs;
91 UINT32 contextRegWrites;
92 UINT32 physicalRegWrites;
94 } IxNpeDlNpeMgrUtilsStats;
98 * Variable declarations global to this file only. Externs are followed by
103 * contains useful address and function pointers to read/write Context Regs,
104 * eliminating some switch or if-else statements in places
106 static IxNpeDlCtxtRegAccessInfo ixNpeDlCtxtRegAccInfo[IX_NPEDL_CTXT_REG_MAX] =
109 IX_NPEDL_CTXT_REG_ADDR_STEVT,
110 IX_NPEDL_REG_SIZE_BYTE
113 IX_NPEDL_CTXT_REG_ADDR_STARTPC,
114 IX_NPEDL_REG_SIZE_SHORT
117 IX_NPEDL_CTXT_REG_ADDR_REGMAP,
118 IX_NPEDL_REG_SIZE_SHORT
121 IX_NPEDL_CTXT_REG_ADDR_CINDEX,
122 IX_NPEDL_REG_SIZE_BYTE
126 static UINT32 ixNpeDlSavedExecCount = 0;
127 static UINT32 ixNpeDlSavedEcsDbgCtxtReg2 = 0;
129 static IxNpeDlNpeMgrUtilsStats ixNpeDlNpeMgrUtilsStats;
133 * static function prototypes.
135 PRIVATE __inline__ void
136 ixNpeDlNpeMgrWriteCommandIssue (UINT32 npeBaseAddress, UINT32 cmd,
137 UINT32 addr, UINT32 data);
139 PRIVATE __inline__ UINT32
140 ixNpeDlNpeMgrReadCommandIssue (UINT32 npeBaseAddress, UINT32 cmd, UINT32 addr);
143 ixNpeDlNpeMgrLogicalRegRead (UINT32 npeBaseAddress, UINT32 regAddr,
144 UINT32 regSize, UINT32 ctxtNum, UINT32 *regVal);
147 ixNpeDlNpeMgrLogicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr,
148 UINT32 regVal, UINT32 regSize,
149 UINT32 ctxtNum, BOOL verify);
152 * Function definition: ixNpeDlNpeMgrWriteCommandIssue
154 PRIVATE __inline__ void
155 ixNpeDlNpeMgrWriteCommandIssue (
156 UINT32 npeBaseAddress,
161 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, data);
162 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
163 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
168 * Function definition: ixNpeDlNpeMgrReadCommandIssue
170 PRIVATE __inline__ UINT32
171 ixNpeDlNpeMgrReadCommandIssue (
172 UINT32 npeBaseAddress,
179 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
180 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
181 for (i = 0; i <= IX_NPEDL_DELAY_READ_CYCLES; i++)
183 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, &data);
190 * Function definition: ixNpeDlNpeMgrInsMemWrite
193 ixNpeDlNpeMgrInsMemWrite (
194 UINT32 npeBaseAddress,
195 UINT32 insMemAddress,
199 UINT32 insMemDataRtn;
201 ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
202 IX_NPEDL_EXCTL_CMD_WR_INS_MEM,
203 insMemAddress, insMemData);
206 /* write invalid data to this reg, so we can see if we're reading
207 the EXDATA register too early */
208 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA,
211 /*Disabled since top 3 MSB are not used for Azusa hardware Refer WR:IXA00053900*/
212 insMemData&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
214 insMemDataRtn=ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
215 IX_NPEDL_EXCTL_CMD_RD_INS_MEM,
218 insMemDataRtn&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
220 if (insMemData != insMemDataRtn)
222 ixNpeDlNpeMgrUtilsStats.insMemWriteFails++;
227 ixNpeDlNpeMgrUtilsStats.insMemWrites++;
233 * Function definition: ixNpeDlNpeMgrDataMemWrite
236 ixNpeDlNpeMgrDataMemWrite (
237 UINT32 npeBaseAddress,
238 UINT32 dataMemAddress,
242 ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
243 IX_NPEDL_EXCTL_CMD_WR_DATA_MEM,
244 dataMemAddress, dataMemData);
247 /* write invalid data to this reg, so we can see if we're reading
248 the EXDATA register too early */
249 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, ~dataMemData);
252 ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
253 IX_NPEDL_EXCTL_CMD_RD_DATA_MEM,
256 ixNpeDlNpeMgrUtilsStats.dataMemWriteFails++;
261 ixNpeDlNpeMgrUtilsStats.dataMemWrites++;
267 * Function definition: ixNpeDlNpeMgrExecAccRegWrite
270 ixNpeDlNpeMgrExecAccRegWrite (
271 UINT32 npeBaseAddress,
275 ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
276 IX_NPEDL_EXCTL_CMD_WR_ECS_REG,
277 regAddress, regData);
278 ixNpeDlNpeMgrUtilsStats.ecsRegWrites++;
283 * Function definition: ixNpeDlNpeMgrExecAccRegRead
286 ixNpeDlNpeMgrExecAccRegRead (
287 UINT32 npeBaseAddress,
290 ixNpeDlNpeMgrUtilsStats.ecsRegReads++;
291 return ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
292 IX_NPEDL_EXCTL_CMD_RD_ECS_REG,
298 * Function definition: ixNpeDlNpeMgrCommandIssue
301 ixNpeDlNpeMgrCommandIssue (
302 UINT32 npeBaseAddress,
305 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
306 "Entering ixNpeDlNpeMgrCommandIssue\n");
308 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, command);
310 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
311 "Exiting ixNpeDlNpeMgrCommandIssue\n");
316 * Function definition: ixNpeDlNpeMgrDebugInstructionPreExec
319 ixNpeDlNpeMgrDebugInstructionPreExec(
320 UINT32 npeBaseAddress)
322 /* turn off the halt bit by clearing Execution Count register. */
323 /* save reg contents 1st and restore later */
324 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
325 &ixNpeDlSavedExecCount);
326 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, 0);
328 /* ensure that IF and IE are on (temporarily), so that we don't end up
329 * stepping forever */
330 ixNpeDlSavedEcsDbgCtxtReg2 = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
331 IX_NPEDL_ECS_DBG_CTXT_REG_2);
333 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
334 (ixNpeDlSavedEcsDbgCtxtReg2 |
335 IX_NPEDL_MASK_ECS_DBG_REG_2_IF |
336 IX_NPEDL_MASK_ECS_DBG_REG_2_IE));
341 * Function definition: ixNpeDlNpeMgrDebugInstructionExec
344 ixNpeDlNpeMgrDebugInstructionExec(
345 UINT32 npeBaseAddress,
346 UINT32 npeInstruction,
351 UINT32 oldWatchcount, newWatchcount;
352 UINT32 retriesCount = 0;
353 IX_STATUS status = IX_SUCCESS;
355 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
356 "Entering ixNpeDlNpeMgrDebugInstructionExec\n");
358 /* set the Active bit, and the LDUR, in the debug level */
359 ecsDbgRegVal = IX_NPEDL_MASK_ECS_REG_0_ACTIVE |
360 (ldur << IX_NPEDL_OFFSET_ECS_REG_0_LDUR);
362 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
366 * set CCTXT at ECS DEBUG L3 to specify in which context to execute the
367 * instruction, and set SELCTXT at ECS DEBUG Level to specify which context
369 * Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
371 ecsDbgRegVal = (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_CCTXT) |
372 (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT);
374 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_1,
377 /* clear the pipeline */
378 ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
380 /* load NPE instruction into the instruction register */
381 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_INSTRUCT_REG,
384 /* we need this value later to wait for completion of NPE execution step */
385 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, &oldWatchcount);
387 /* issue a Step One command via the Execution Control register */
388 ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STEP);
390 /* Watch Count register increments when NPE completes an instruction */
391 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
395 * force the XScale to wait until the NPE has finished execution step
396 * NOTE that this delay will be very small, just long enough to allow a
397 * single NPE instruction to complete execution; if instruction execution
398 * is not completed before timeout retries, exit the while loop
400 while ((IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount)
401 && (newWatchcount == oldWatchcount))
403 /* Watch Count register increments when NPE completes an instruction */
404 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
410 if (IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount)
412 ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs++;
416 /* Return timeout status as the instruction has not been executed
417 * after maximum retries */
418 status = IX_NPEDL_CRITICAL_NPE_ERR;
421 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
422 "Exiting ixNpeDlNpeMgrDebugInstructionExec\n");
429 * Function definition: ixNpeDlNpeMgrDebugInstructionPostExec
432 ixNpeDlNpeMgrDebugInstructionPostExec(
433 UINT32 npeBaseAddress)
435 /* clear active bit in debug level */
436 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
439 /* clear the pipeline */
440 ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
442 /* restore Execution Count register contents. */
443 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
444 ixNpeDlSavedExecCount);
446 /* restore IF and IE bits to original values */
447 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
448 ixNpeDlSavedEcsDbgCtxtReg2);
453 * Function definition: ixNpeDlNpeMgrLogicalRegRead
456 ixNpeDlNpeMgrLogicalRegRead (
457 UINT32 npeBaseAddress,
463 IX_STATUS status = IX_SUCCESS;
464 UINT32 npeInstruction = 0;
467 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
468 "Entering ixNpeDlNpeMgrLogicalRegRead\n");
472 case IX_NPEDL_REG_SIZE_BYTE:
473 npeInstruction = IX_NPEDL_INSTR_RD_REG_BYTE;
474 mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break;
475 case IX_NPEDL_REG_SIZE_SHORT:
476 npeInstruction = IX_NPEDL_INSTR_RD_REG_SHORT;
477 mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break;
478 case IX_NPEDL_REG_SIZE_WORD:
479 npeInstruction = IX_NPEDL_INSTR_RD_REG_WORD;
480 mask = IX_NPEDL_MASK_FULL_WORD; break;
483 /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */
484 npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) |
485 (regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
487 /* step execution of NPE intruction using Debug Executing Context stack */
488 status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, npeInstruction,
489 ctxtNum, IX_NPEDL_RD_INSTR_LDUR);
491 if (IX_SUCCESS != status)
496 /* read value of register from Execution Data register */
497 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, regVal);
499 /* align value from left to right */
500 *regVal = (*regVal >> (IX_NPEDL_REG_SIZE_WORD - regSize)) & mask;
502 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
503 "Exiting ixNpeDlNpeMgrLogicalRegRead\n");
510 * Function definition: ixNpeDlNpeMgrLogicalRegWrite
513 ixNpeDlNpeMgrLogicalRegWrite (
514 UINT32 npeBaseAddress,
521 UINT32 npeInstruction = 0;
523 IX_STATUS status = IX_SUCCESS;
526 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
527 "Entering ixNpeDlNpeMgrLogicalRegWrite\n");
529 if (regSize == IX_NPEDL_REG_SIZE_WORD)
531 /* NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| */
532 /* Write upper half-word (short) to |d0|d1| */
533 status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr,
534 regVal >> IX_NPEDL_REG_SIZE_SHORT,
535 IX_NPEDL_REG_SIZE_SHORT,
538 if (IX_SUCCESS != status)
543 /* Write lower half-word (short) to |d2|d3| */
544 status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
545 regAddr + IX_NPEDL_BYTES_PER_SHORT,
546 regVal & IX_NPEDL_MASK_LOWER_SHORT_OF_WORD,
547 IX_NPEDL_REG_SIZE_SHORT,
550 if (IX_SUCCESS != status)
559 case IX_NPEDL_REG_SIZE_BYTE:
560 npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE;
561 mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break;
562 case IX_NPEDL_REG_SIZE_SHORT:
563 npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT;
564 mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break;
566 /* mask out any redundant bits, so verify will work later */
569 /* fill dest operand field of instruction with destination reg addr */
570 npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
572 /* fill src operand field of instruction with least-sig 5 bits of val*/
573 npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) <<
574 IX_NPEDL_OFFSET_INSTR_SRC);
576 /* fill coprocessor field of instruction with most-sig 11 bits of val*/
577 npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) <<
578 IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA);
580 /* step execution of NPE intruction using Debug ECS */
581 status = ixNpeDlNpeMgrDebugInstructionExec(npeBaseAddress, npeInstruction,
582 ctxtNum, IX_NPEDL_WR_INSTR_LDUR);
584 if (IX_SUCCESS != status)
588 }/* condition: if reg to be written is 8-bit or 16-bit (not 32-bit) */
592 status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr,
593 regSize, ctxtNum, &retRegVal);
595 if (IX_SUCCESS == status)
597 if (regVal != retRegVal)
604 IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
605 "Exiting ixNpeDlNpeMgrLogicalRegWrite : status = %d\n",
613 * Function definition: ixNpeDlNpeMgrPhysicalRegWrite
616 ixNpeDlNpeMgrPhysicalRegWrite (
617 UINT32 npeBaseAddress,
624 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
625 "Entering ixNpeDlNpeMgrPhysicalRegWrite\n");
628 * There are 32 physical registers used in an NPE. These are
629 * treated as 16 pairs of 32-bit registers. To write one of the pair,
630 * write the pair number (0-16) to the REGMAP for Context 0. Then write
631 * the value to register 0 or 4 in the regfile, depending on which
632 * register of the pair is to be written
636 * set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16)
637 * of physical registers to write
639 status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
640 IX_NPEDL_CTXT_REG_ADDR_REGMAP,
642 IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP),
643 IX_NPEDL_REG_SIZE_SHORT, 0, verify);
644 if (status == IX_SUCCESS)
646 /* regAddr = 0 or 4 */
647 regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) *
648 IX_NPEDL_BYTES_PER_WORD;
650 status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr, regValue,
651 IX_NPEDL_REG_SIZE_WORD, 0, verify);
654 if (status != IX_SUCCESS)
656 IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrPhysicalRegWrite: "
657 "error writing to physical register\n");
660 ixNpeDlNpeMgrUtilsStats.physicalRegWrites++;
662 IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
663 "Exiting ixNpeDlNpeMgrPhysicalRegWrite : status = %d\n",
670 * Function definition: ixNpeDlNpeMgrCtxtRegWrite
673 ixNpeDlNpeMgrCtxtRegWrite (
674 UINT32 npeBaseAddress,
676 IxNpeDlCtxtRegNum ctxtReg,
683 IX_STATUS status = IX_SUCCESS;
685 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
686 "Entering ixNpeDlNpeMgrCtxtRegWrite\n");
689 * Context 0 has no STARTPC. Instead, this value is used to set
690 * NextPC for Background ECS, to set where NPE starts executing code
692 if ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STARTPC))
694 /* read BG_CTXT_REG_0, update NEXTPC bits, and write back to reg */
695 tempRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
696 IX_NPEDL_ECS_BG_CTXT_REG_0);
697 tempRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
698 tempRegVal |= (ctxtRegVal << IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC) &
699 IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
701 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress,
702 IX_NPEDL_ECS_BG_CTXT_REG_0, tempRegVal);
704 ixNpeDlNpeMgrUtilsStats.nextPcWrites++;
708 ctxtRegAddr = ixNpeDlCtxtRegAccInfo[ctxtReg].regAddress;
709 ctxtRegSize = ixNpeDlCtxtRegAccInfo[ctxtReg].regSize;
710 status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, ctxtRegAddr,
711 ctxtRegVal, ctxtRegSize,
713 if (status != IX_SUCCESS)
715 IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrCtxtRegWrite: "
716 "error writing to context store register\n");
719 ixNpeDlNpeMgrUtilsStats.contextRegWrites++;
722 IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
723 "Exiting ixNpeDlNpeMgrCtxtRegWrite : status = %d\n",
731 * Function definition: ixNpeDlNpeMgrUtilsStatsShow
734 ixNpeDlNpeMgrUtilsStatsShow (void)
736 ixOsalLog (IX_OSAL_LOG_LVL_USER,
737 IX_OSAL_LOG_DEV_STDOUT,
738 "\nixNpeDlNpeMgrUtilsStatsShow:\n"
739 "\tInstruction Memory writes: %u\n"
740 "\tInstruction Memory writes failed: %u\n"
741 "\tData Memory writes: %u\n"
742 "\tData Memory writes failed: %u\n",
743 ixNpeDlNpeMgrUtilsStats.insMemWrites,
744 ixNpeDlNpeMgrUtilsStats.insMemWriteFails,
745 ixNpeDlNpeMgrUtilsStats.dataMemWrites,
746 ixNpeDlNpeMgrUtilsStats.dataMemWriteFails,
749 ixOsalLog (IX_OSAL_LOG_LVL_USER,
750 IX_OSAL_LOG_DEV_STDOUT,
751 "\tExecuting Context Stack Register writes: %u\n"
752 "\tExecuting Context Stack Register reads: %u\n"
753 "\tPhysical Register writes: %u\n"
754 "\tContext Store Register writes: %u\n"
755 "\tExecution Backgound Context NextPC writes: %u\n"
756 "\tDebug Instructions Executed: %u\n\n",
757 ixNpeDlNpeMgrUtilsStats.ecsRegWrites,
758 ixNpeDlNpeMgrUtilsStats.ecsRegReads,
759 ixNpeDlNpeMgrUtilsStats.physicalRegWrites,
760 ixNpeDlNpeMgrUtilsStats.contextRegWrites,
761 ixNpeDlNpeMgrUtilsStats.nextPcWrites,
762 ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs);
767 * Function definition: ixNpeDlNpeMgrUtilsStatsReset
770 ixNpeDlNpeMgrUtilsStatsReset (void)
772 ixNpeDlNpeMgrUtilsStats.insMemWrites = 0;
773 ixNpeDlNpeMgrUtilsStats.insMemWriteFails = 0;
774 ixNpeDlNpeMgrUtilsStats.dataMemWrites = 0;
775 ixNpeDlNpeMgrUtilsStats.dataMemWriteFails = 0;
776 ixNpeDlNpeMgrUtilsStats.ecsRegWrites = 0;
777 ixNpeDlNpeMgrUtilsStats.ecsRegReads = 0;
778 ixNpeDlNpeMgrUtilsStats.physicalRegWrites = 0;
779 ixNpeDlNpeMgrUtilsStats.contextRegWrites = 0;
780 ixNpeDlNpeMgrUtilsStats.nextPcWrites = 0;
781 ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs = 0;