2 * @file IxNpeDlNpeMgr.c
4 * @author Intel Corporation
5 * @date 09 January 2002
7 * @brief This file contains the implementation of the private API for the
8 * IXP425 NPE Downloader NpeMgr module
12 * IXP400 SW Release version 2.0
14 * -- Copyright Notice --
17 * Copyright 2001-2005, Intel Corporation.
18 * All rights reserved.
21 * SPDX-License-Identifier: BSD-3-Clause
23 * -- End of Copyright Notice --
28 * Put the user defined include files required.
32 #include "IxNpeDlNpeMgr_p.h"
33 #include "IxNpeDlNpeMgrUtils_p.h"
34 #include "IxNpeDlNpeMgrEcRegisters_p.h"
35 #include "IxNpeDlMacros_p.h"
36 #include "IxFeatureCtrl.h"
39 * #defines and macros used in this file.
41 #define IX_NPEDL_BYTES_PER_WORD 4
43 /* used to read download map from version in microcode image */
44 #define IX_NPEDL_BLOCK_TYPE_INSTRUCTION 0x00000000
45 #define IX_NPEDL_BLOCK_TYPE_DATA 0x00000001
46 #define IX_NPEDL_BLOCK_TYPE_STATE 0x00000002
47 #define IX_NPEDL_END_OF_DOWNLOAD_MAP 0x0000000F
50 * masks used to extract address info from State information context
51 * register addresses as read from microcode image
53 #define IX_NPEDL_MASK_STATE_ADDR_CTXT_REG 0x0000000F
54 #define IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM 0x000000F0
56 /* LSB offset of Context Number field in State-Info Context Address */
57 #define IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM 4
59 /* size (in words) of single State Information entry (ctxt reg address|data) */
60 #define IX_NPEDL_STATE_INFO_ENTRY_SIZE 2
63 #define IX_NPEDL_RESET_NPE_PARITY 0x0800
64 #define IX_NPEDL_PARITY_BIT_MASK 0x3F00FFFF
65 #define IX_NPEDL_CONFIG_CTRL_REG_MASK 0x3F3FFFFF
69 * Typedefs whose scope is limited to this file.
76 } IxNpeDlNpeMgrDownloadMapBlockEntry;
80 IxNpeDlNpeMgrDownloadMapBlockEntry block;
82 } IxNpeDlNpeMgrDownloadMapEntry;
86 /* 1st entry in the download map (there may be more than one) */
87 IxNpeDlNpeMgrDownloadMapEntry entry[1];
88 } IxNpeDlNpeMgrDownloadMap;
91 /* used to access an instruction or data block in a microcode image */
97 } IxNpeDlNpeMgrCodeBlock;
99 /* used to access each Context Reg entry state-information block */
104 } IxNpeDlNpeMgrStateInfoCtxtRegEntry;
106 /* used to access a state-information block in a microcode image */
110 IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1];
111 } IxNpeDlNpeMgrStateInfoBlock;
113 /* used to store some useful NPE information for easy access */
121 /* used to distinguish instruction and data memory operations */
124 IX_NPEDL_MEM_TYPE_INSTRUCTION = 0,
125 IX_NPEDL_MEM_TYPE_DATA
128 /* used to hold a reset value for a particular ECS register */
133 } IxNpeDlEcsRegResetValue;
135 /* prototype of function to write either Instruction or Data memory */
136 typedef IX_STATUS (*IxNpeDlNpeMgrMemWrite) (UINT32 npeBaseAddress,
137 UINT32 npeMemAddress,
141 /* module statistics counters */
144 UINT32 instructionBlocksLoaded;
145 UINT32 dataBlocksLoaded;
146 UINT32 stateInfoBlocksLoaded;
147 UINT32 criticalNpeErrors;
148 UINT32 criticalMicrocodeErrors;
152 } IxNpeDlNpeMgrStats;
156 * Variable declarations global to this file only. Externs are followed by
159 static IxNpeDlNpeInfo ixNpeDlNpeInfo[] =
163 IX_NPEDL_INS_MEMSIZE_WORDS_NPEA,
164 IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
168 IX_NPEDL_INS_MEMSIZE_WORDS_NPEB,
169 IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
173 IX_NPEDL_INS_MEMSIZE_WORDS_NPEC,
174 IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
178 /* contains Reset values for Context Store Registers */
179 static UINT32 ixNpeDlCtxtRegResetValues[] =
181 IX_NPEDL_CTXT_REG_RESET_STEVT,
182 IX_NPEDL_CTXT_REG_RESET_STARTPC,
183 IX_NPEDL_CTXT_REG_RESET_REGMAP,
184 IX_NPEDL_CTXT_REG_RESET_CINDEX,
187 /* contains Reset values for Context Store Registers */
188 static IxNpeDlEcsRegResetValue ixNpeDlEcsRegResetValues[] =
190 {IX_NPEDL_ECS_BG_CTXT_REG_0, IX_NPEDL_ECS_BG_CTXT_REG_0_RESET},
191 {IX_NPEDL_ECS_BG_CTXT_REG_1, IX_NPEDL_ECS_BG_CTXT_REG_1_RESET},
192 {IX_NPEDL_ECS_BG_CTXT_REG_2, IX_NPEDL_ECS_BG_CTXT_REG_2_RESET},
193 {IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET},
194 {IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET},
195 {IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET},
196 {IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET},
197 {IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET},
198 {IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET},
199 {IX_NPEDL_ECS_DBG_CTXT_REG_0, IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET},
200 {IX_NPEDL_ECS_DBG_CTXT_REG_1, IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET},
201 {IX_NPEDL_ECS_DBG_CTXT_REG_2, IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET},
202 {IX_NPEDL_ECS_INSTRUCT_REG, IX_NPEDL_ECS_INSTRUCT_REG_RESET}
205 static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats;
207 /* Set when NPE register memory has been mapped */
208 static BOOL ixNpeDlMemInitialised = false;
212 * static function prototypes.
215 ixNpeDlNpeMgrMemLoad (IxNpeDlNpeId npeId, UINT32 npeBaseAddress,
216 IxNpeDlNpeMgrCodeBlock *codeBlockPtr,
217 BOOL verify, IxNpeDlNpeMemType npeMemType);
219 ixNpeDlNpeMgrStateInfoLoad (UINT32 npeBaseAddress,
220 IxNpeDlNpeMgrStateInfoBlock *codeBlockPtr,
223 ixNpeDlNpeMgrBitsSetCheck (UINT32 npeBaseAddress, UINT32 regOffset,
224 UINT32 expectedBitsSet);
227 ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId);
230 * Function definition: ixNpeDlNpeMgrBaseAddressGet
233 ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId)
235 IX_OSAL_ASSERT (ixNpeDlMemInitialised);
236 return ixNpeDlNpeInfo[npeId].baseAddress;
241 * Function definition: ixNpeDlNpeMgrInit
244 ixNpeDlNpeMgrInit (void)
246 /* Only map the memory once */
247 if (!ixNpeDlMemInitialised)
251 /* map the register memory for NPE-A */
252 virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEA,
253 IX_OSAL_IXP400_NPEA_MAP_SIZE);
254 IX_OSAL_ASSERT(virtAddr);
255 ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = virtAddr;
257 /* map the register memory for NPE-B */
258 virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEB,
259 IX_OSAL_IXP400_NPEB_MAP_SIZE);
260 IX_OSAL_ASSERT(virtAddr);
261 ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = virtAddr;
263 /* map the register memory for NPE-C */
264 virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEC,
265 IX_OSAL_IXP400_NPEC_MAP_SIZE);
266 IX_OSAL_ASSERT(virtAddr);
267 ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr;
269 ixNpeDlMemInitialised = true;
275 * Function definition: ixNpeDlNpeMgrUninit
278 ixNpeDlNpeMgrUninit (void)
280 if (!ixNpeDlMemInitialised)
285 IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress);
286 IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress);
287 IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress);
289 ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = 0;
290 ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0;
291 ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0;
293 ixNpeDlMemInitialised = false;
299 * Function definition: ixNpeDlNpeMgrImageLoad
302 ixNpeDlNpeMgrImageLoad (
304 UINT32 *imageCodePtr,
307 UINT32 npeBaseAddress;
308 IxNpeDlNpeMgrDownloadMap *downloadMap;
311 IX_STATUS status = IX_SUCCESS;
313 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
314 "Entering ixNpeDlNpeMgrImageLoad\n");
316 /* get base memory address of NPE from npeId */
317 npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
319 /* check execution status of NPE to verify NPE Stop was successful */
320 if (!ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
321 IX_NPEDL_EXCTL_STATUS_STOP))
323 IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageDownload - "
324 "NPE was not stopped before download\n");
330 * Read Download Map, checking each block type and calling
331 * appropriate function to perform download
333 downloadMap = (IxNpeDlNpeMgrDownloadMap *) imageCodePtr;
334 while ((downloadMap->entry[mapIndex].eodmMarker !=
335 IX_NPEDL_END_OF_DOWNLOAD_MAP)
336 && (status == IX_SUCCESS))
338 /* calculate pointer to block to be downloaded */
339 blockPtr = imageCodePtr +
340 downloadMap->entry[mapIndex].block.offset;
342 switch (downloadMap->entry[mapIndex].block.type)
344 case IX_NPEDL_BLOCK_TYPE_INSTRUCTION:
345 status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress,
346 (IxNpeDlNpeMgrCodeBlock *)blockPtr,
348 IX_NPEDL_MEM_TYPE_INSTRUCTION);
350 case IX_NPEDL_BLOCK_TYPE_DATA:
351 status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress,
352 (IxNpeDlNpeMgrCodeBlock *)blockPtr,
353 verify, IX_NPEDL_MEM_TYPE_DATA);
355 case IX_NPEDL_BLOCK_TYPE_STATE:
356 status = ixNpeDlNpeMgrStateInfoLoad (npeBaseAddress,
357 (IxNpeDlNpeMgrStateInfoBlock *) blockPtr,
361 IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageLoad: "
362 "unknown block type in download map\n");
363 status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
364 ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
368 }/* loop: for each entry in download map, while status == SUCCESS */
369 }/* condition: NPE stopped before attempting download */
371 IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
372 "Exiting ixNpeDlNpeMgrImageLoad : status = %d\n",
379 * Function definition: ixNpeDlNpeMgrMemLoad
382 ixNpeDlNpeMgrMemLoad (
384 UINT32 npeBaseAddress,
385 IxNpeDlNpeMgrCodeBlock *blockPtr,
387 IxNpeDlNpeMemType npeMemType)
389 UINT32 npeMemAddress;
392 IxNpeDlNpeMgrMemWrite memWriteFunc = NULL;
393 UINT32 localIndex = 0;
394 IX_STATUS status = IX_SUCCESS;
396 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
397 "Entering ixNpeDlNpeMgrMemLoad\n");
400 * select NPE EXCTL reg read/write commands depending on memory
401 * type (instruction/data) to be accessed
403 if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
405 memSize = ixNpeDlNpeInfo[npeId].insMemSize;
406 memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrInsMemWrite;
408 else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
410 memSize = ixNpeDlNpeInfo[npeId].dataMemSize;
411 memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrDataMemWrite;
415 * NPE memory is loaded contiguously from each block, so only address
416 * of 1st word in block is needed
418 npeMemAddress = blockPtr->npeMemAddress;
419 /* number of words of instruction/data microcode in block to download */
420 blockSize = blockPtr->size;
421 if ((npeMemAddress + blockSize) > memSize)
423 IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
424 "Block size too big for NPE memory\n");
425 status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
426 ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
430 for (localIndex = 0; localIndex < blockSize; localIndex++)
432 status = memWriteFunc (npeBaseAddress, npeMemAddress,
433 blockPtr->data[localIndex], verify);
435 if (status != IX_SUCCESS)
437 IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
438 "write to NPE memory failed\n");
439 status = IX_NPEDL_CRITICAL_NPE_ERR;
440 ixNpeDlNpeMgrStats.criticalNpeErrors++;
441 break; /* abort download */
443 /* increment target (word)address in NPE memory */
446 }/* condition: block size will fit in NPE memory */
448 if (status == IX_SUCCESS)
450 if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
452 ixNpeDlNpeMgrStats.instructionBlocksLoaded++;
454 else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
456 ixNpeDlNpeMgrStats.dataBlocksLoaded++;
460 IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
461 "Exiting ixNpeDlNpeMgrMemLoad : status = %d\n", status);
467 * Function definition: ixNpeDlNpeMgrStateInfoLoad
470 ixNpeDlNpeMgrStateInfoLoad (
471 UINT32 npeBaseAddress,
472 IxNpeDlNpeMgrStateInfoBlock *blockPtr,
476 UINT32 ctxtRegAddrInfo;
478 IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
479 UINT32 ctxtNum; /* identifies Context number (0-16) */
481 IX_STATUS status = IX_SUCCESS;
483 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
484 "Entering ixNpeDlNpeMgrStateInfoLoad\n");
486 /* block size contains number of words of state-info in block */
487 blockSize = blockPtr->size;
489 ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
491 /* for each state-info context register entry in block */
492 for (i = 0; i < (blockSize/IX_NPEDL_STATE_INFO_ENTRY_SIZE); i++)
494 /* each state-info entry is 2 words (address, value) in length */
495 ctxtRegAddrInfo = (blockPtr->ctxtRegEntry[i]).addressInfo;
496 ctxtRegVal = (blockPtr->ctxtRegEntry[i]).value;
498 ctxtReg = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG);
499 ctxtNum = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >>
500 IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM;
502 /* error-check Context Register No. and Context Number values */
503 /* NOTE that there is no STEVT register for Context 0 */
505 (ctxtReg >= IX_NPEDL_CTXT_REG_MAX) ||
506 (ctxtNum > IX_NPEDL_CTXT_NUM_MAX) ||
507 ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
509 IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
510 "invalid Context Register Address\n");
511 status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
512 ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
513 break; /* abort download */
516 status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, ctxtReg,
518 if (status != IX_SUCCESS)
520 IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
521 "write of state-info to NPE failed\n");
522 status = IX_NPEDL_CRITICAL_NPE_ERR;
523 ixNpeDlNpeMgrStats.criticalNpeErrors++;
524 break; /* abort download */
526 }/* loop: for each context reg entry in State Info block */
528 ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
530 if (status == IX_SUCCESS)
532 ixNpeDlNpeMgrStats.stateInfoBlocksLoaded++;
535 IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
536 "Exiting ixNpeDlNpeMgrStateInfoLoad : status = %d\n",
543 * Function definition: ixNpeDlNpeMgrNpeReset
546 ixNpeDlNpeMgrNpeReset (
549 UINT32 npeBaseAddress;
550 IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
551 UINT32 ctxtNum; /* identifies Context number (0-16) */
556 IX_STATUS status = IX_SUCCESS;
557 IxFeatureCtrlReg unitFuseReg;
558 UINT32 ixNpeConfigCtrlRegVal;
560 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
561 "Entering ixNpeDlNpeMgrNpeReset\n");
563 /* get base memory address of NPE from npeId */
564 npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
566 /* pre-store the NPE Config Control Register Value */
567 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, &ixNpeConfigCtrlRegVal);
569 ixNpeConfigCtrlRegVal |= 0x3F000000;
571 /* disable the parity interrupt */
572 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK));
574 ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
579 while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
580 IX_NPEDL_REG_OFFSET_WFIFO,
581 IX_NPEDL_MASK_WFIFO_VALID))
583 /* read from the Watch-point FIFO until empty */
584 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WFIFO,
588 while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
589 IX_NPEDL_REG_OFFSET_STAT,
590 IX_NPEDL_MASK_STAT_OFNE))
592 /* read from the outFIFO until empty */
593 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_FIFO,
597 while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
598 IX_NPEDL_REG_OFFSET_STAT,
599 IX_NPEDL_MASK_STAT_IFNE))
602 * step execution of the NPE intruction to read inFIFO using
603 * the Debug Executing Context stack
605 status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
606 IX_NPEDL_INSTR_RD_FIFO, 0, 0);
608 if (IX_SUCCESS != status)
616 * Reset the mailbox reg
618 /* ...from XScale side */
619 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_MBST,
620 IX_NPEDL_REG_RESET_MBST);
621 /* ...from NPE side */
622 status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
623 IX_NPEDL_INSTR_RESET_MBOX, 0, 0);
625 if (IX_SUCCESS != status)
631 * Reset the physical registers in the NPE register file:
632 * Note: no need to save/restore REGMAP for Context 0 here
633 * since all Context Store regs are reset in subsequent code
636 (regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG) && (status != IX_FAIL);
639 /* for each physical register in the NPE reg file, write 0 : */
640 status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr,
642 if (status != IX_SUCCESS)
644 return status; /* abort reset */
650 * Reset the context store:
652 for (ctxtNum = IX_NPEDL_CTXT_NUM_MIN;
653 ctxtNum <= IX_NPEDL_CTXT_NUM_MAX; ctxtNum++)
655 /* set each context's Context Store registers to reset values: */
656 for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++)
658 /* NOTE that there is no STEVT register for Context 0 */
659 if (!((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
661 regVal = ixNpeDlCtxtRegResetValues[ctxtReg];
662 status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum,
663 ctxtReg, regVal, true);
664 if (status != IX_SUCCESS)
666 return status; /* abort reset */
672 ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
674 /* write Reset values to Execution Context Stack registers */
675 indexMax = sizeof (ixNpeDlEcsRegResetValues) /
676 sizeof (IxNpeDlEcsRegResetValue);
677 for (localIndex = 0; localIndex < indexMax; localIndex++)
679 regAddr = ixNpeDlEcsRegResetValues[localIndex].regAddr;
680 regVal = ixNpeDlEcsRegResetValues[localIndex].regResetVal;
681 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, regAddr, regVal);
684 /* clear the profile counter */
685 ixNpeDlNpeMgrCommandIssue (npeBaseAddress,
686 IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT);
688 /* clear registers EXCT, AP0, AP1, AP2 and AP3 */
689 for (regAddr = IX_NPEDL_REG_OFFSET_EXCT;
690 regAddr <= IX_NPEDL_REG_OFFSET_AP3;
691 regAddr += IX_NPEDL_BYTES_PER_WORD)
693 IX_NPEDL_REG_WRITE (npeBaseAddress, regAddr, 0);
696 /* Reset the Watch-count register */
697 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, 0);
700 * WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation
704 * Call the feature control API to fused out and reset the NPE and its
705 * coprocessor - to reset internal states and remove parity error
707 unitFuseReg = ixFeatureCtrlRead ();
708 unitFuseReg |= (IX_NPEDL_RESET_NPE_PARITY << npeId);
709 ixFeatureCtrlWrite (unitFuseReg);
711 /* call the feature control API to un-fused and un-reset the NPE & COP */
712 unitFuseReg &= (~(IX_NPEDL_RESET_NPE_PARITY << npeId));
713 ixFeatureCtrlWrite (unitFuseReg);
716 * Call NpeMgr function to stop the NPE again after the Feature Control
717 * has unfused and Un-Reset the NPE and its associated Coprocessors
719 status = ixNpeDlNpeMgrNpeStop (npeId);
721 /* restore NPE configuration bus Control Register - Parity Settings */
722 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL,
723 (ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK));
725 ixNpeDlNpeMgrStats.npeResets++;
727 IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
728 "Exiting ixNpeDlNpeMgrNpeReset : status = %d\n", status);
734 * Function definition: ixNpeDlNpeMgrNpeStart
737 ixNpeDlNpeMgrNpeStart (
740 UINT32 npeBaseAddress;
743 IX_STATUS status = IX_SUCCESS;
745 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
746 "Entering ixNpeDlNpeMgrNpeStart\n");
748 /* get base memory address of NPE from npeId */
749 npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
752 * ensure only Background Context Stack Level is Active by turning off
753 * the Active bit in each of the other Executing Context Stack levels
755 ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
756 IX_NPEDL_ECS_PRI_1_CTXT_REG_0);
757 ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
758 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_1_CTXT_REG_0,
761 ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
762 IX_NPEDL_ECS_PRI_2_CTXT_REG_0);
763 ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
764 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_2_CTXT_REG_0,
767 ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
768 IX_NPEDL_ECS_DBG_CTXT_REG_0);
769 ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
770 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
773 /* clear the pipeline */
774 ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
776 /* start NPE execution by issuing command through EXCTL register on NPE */
777 ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_START);
780 * check execution status of NPE to verify NPE Start operation was
783 npeRunning = ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
784 IX_NPEDL_REG_OFFSET_EXCTL,
785 IX_NPEDL_EXCTL_STATUS_RUN);
788 ixNpeDlNpeMgrStats.npeStarts++;
792 IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStart: "
793 "failed to start NPE execution\n");
798 IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
799 "Exiting ixNpeDlNpeMgrNpeStart : status = %d\n", status);
805 * Function definition: ixNpeDlNpeMgrNpeStop
808 ixNpeDlNpeMgrNpeStop (
811 UINT32 npeBaseAddress;
812 IX_STATUS status = IX_SUCCESS;
814 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
815 "Entering ixNpeDlNpeMgrNpeStop\n");
817 /* get base memory address of NPE from npeId */
818 npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
820 /* stop NPE execution by issuing command through EXCTL register on NPE */
821 ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STOP);
823 /* verify that NPE Stop was successful */
824 if (! ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
825 IX_NPEDL_EXCTL_STATUS_STOP))
827 IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStop: "
828 "failed to stop NPE execution\n");
832 ixNpeDlNpeMgrStats.npeStops++;
834 IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
835 "Exiting ixNpeDlNpeMgrNpeStop : status = %d\n", status);
841 * Function definition: ixNpeDlNpeMgrBitsSetCheck
844 ixNpeDlNpeMgrBitsSetCheck (
845 UINT32 npeBaseAddress,
847 UINT32 expectedBitsSet)
850 IX_NPEDL_REG_READ (npeBaseAddress, regOffset, ®Val);
852 return expectedBitsSet == (expectedBitsSet & regVal);
857 * Function definition: ixNpeDlNpeMgrStatsShow
860 ixNpeDlNpeMgrStatsShow (void)
862 ixOsalLog (IX_OSAL_LOG_LVL_USER,
863 IX_OSAL_LOG_DEV_STDOUT,
864 "\nixNpeDlNpeMgrStatsShow:\n"
865 "\tInstruction Blocks loaded: %u\n"
866 "\tData Blocks loaded: %u\n"
867 "\tState Information Blocks loaded: %u\n"
868 "\tCritical NPE errors: %u\n"
869 "\tCritical Microcode errors: %u\n",
870 ixNpeDlNpeMgrStats.instructionBlocksLoaded,
871 ixNpeDlNpeMgrStats.dataBlocksLoaded,
872 ixNpeDlNpeMgrStats.stateInfoBlocksLoaded,
873 ixNpeDlNpeMgrStats.criticalNpeErrors,
874 ixNpeDlNpeMgrStats.criticalMicrocodeErrors,
877 ixOsalLog (IX_OSAL_LOG_LVL_USER,
878 IX_OSAL_LOG_DEV_STDOUT,
879 "\tSuccessful NPE Starts: %u\n"
880 "\tSuccessful NPE Stops: %u\n"
881 "\tSuccessful NPE Resets: %u\n\n",
882 ixNpeDlNpeMgrStats.npeStarts,
883 ixNpeDlNpeMgrStats.npeStops,
884 ixNpeDlNpeMgrStats.npeResets,
887 ixNpeDlNpeMgrUtilsStatsShow ();
892 * Function definition: ixNpeDlNpeMgrStatsReset
895 ixNpeDlNpeMgrStatsReset (void)
897 ixNpeDlNpeMgrStats.instructionBlocksLoaded = 0;
898 ixNpeDlNpeMgrStats.dataBlocksLoaded = 0;
899 ixNpeDlNpeMgrStats.stateInfoBlocksLoaded = 0;
900 ixNpeDlNpeMgrStats.criticalNpeErrors = 0;
901 ixNpeDlNpeMgrStats.criticalMicrocodeErrors = 0;
902 ixNpeDlNpeMgrStats.npeStarts = 0;
903 ixNpeDlNpeMgrStats.npeStops = 0;
904 ixNpeDlNpeMgrStats.npeResets = 0;
906 ixNpeDlNpeMgrUtilsStatsReset ();