2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
18 #include <dm/device-internal.h>
25 #include <linux/errno.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/soc.h>
31 #include <linux/compat.h>
32 #include <linux/mbus.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 /* Some linux -> U-Boot compatibility stuff */
37 #define netdev_err(dev, fmt, args...) \
39 #define netdev_warn(dev, fmt, args...) \
41 #define netdev_info(dev, fmt, args...) \
43 #define netdev_dbg(dev, fmt, args...) \
46 #define ETH_ALEN 6 /* Octets in one ethernet addr */
48 #define __verify_pcpu_ptr(ptr) \
50 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
54 #define VERIFY_PERCPU_PTR(__p) \
56 __verify_pcpu_ptr(__p); \
57 (typeof(*(__p)) __kernel __force *)(__p); \
60 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
61 #define smp_processor_id() 0
62 #define num_present_cpus() 1
63 #define for_each_present_cpu(cpu) \
64 for ((cpu) = 0; (cpu) < 1; (cpu)++)
66 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
68 #define CONFIG_NR_CPUS 1
69 #define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
71 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
72 #define WRAP (2 + ETH_HLEN + 4 + 32)
74 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
76 #define MVPP2_SMI_TIMEOUT 10000
78 /* RX Fifo Registers */
79 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
80 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
81 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
82 #define MVPP2_RX_FIFO_INIT_REG 0x64
84 /* RX DMA Top Registers */
85 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
86 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
87 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
88 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
89 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
90 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
91 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
92 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
93 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
94 #define MVPP2_RXQ_POOL_SHORT_MASK 0x700000
95 #define MVPP2_RXQ_POOL_LONG_OFFS 24
96 #define MVPP2_RXQ_POOL_LONG_MASK 0x7000000
97 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
98 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
99 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
101 /* Parser Registers */
102 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
103 #define MVPP2_PRS_PORT_LU_MAX 0xf
104 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
105 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
106 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
107 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
108 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
109 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
110 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
111 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
112 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
113 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
114 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
115 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
117 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
118 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
120 /* Classifier Registers */
121 #define MVPP2_CLS_MODE_REG 0x1800
122 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
123 #define MVPP2_CLS_PORT_WAY_REG 0x1810
124 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
125 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
126 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
127 #define MVPP2_CLS_LKP_TBL_REG 0x1818
128 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
129 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
130 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
131 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
132 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
133 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
134 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
135 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
136 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
137 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
139 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
141 /* Descriptor Manager Top Registers */
142 #define MVPP2_RXQ_NUM_REG 0x2040
143 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
144 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
145 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
146 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
147 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
148 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
149 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
150 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
151 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
152 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
153 #define MVPP2_RXQ_THRESH_REG 0x204c
154 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
155 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
156 #define MVPP2_RXQ_INDEX_REG 0x2050
157 #define MVPP2_TXQ_NUM_REG 0x2080
158 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
159 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
160 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
161 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
162 #define MVPP2_TXQ_THRESH_REG 0x2094
163 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
164 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
165 #define MVPP2_TXQ_INDEX_REG 0x2098
166 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
167 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
168 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
169 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
170 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
171 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
172 #define MVPP2_TXQ_PENDING_REG 0x20a0
173 #define MVPP2_TXQ_PENDING_MASK 0x3fff
174 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
175 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
176 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
177 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
178 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
179 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
180 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
181 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
182 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
183 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
184 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
185 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
186 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
187 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
188 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
189 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
191 /* MBUS bridge registers */
192 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
193 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
194 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
195 #define MVPP2_BASE_ADDR_ENABLE 0x4060
197 /* Interrupt Cause and Mask registers */
198 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
199 #define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
200 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
201 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
202 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
203 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
204 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
205 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
206 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
207 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
208 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
209 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
210 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
211 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
212 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
213 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
214 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
215 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
216 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
217 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
219 /* Buffer Manager registers */
220 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
221 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
222 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
223 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
224 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
225 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
226 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
227 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
228 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
229 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
230 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
231 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
232 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
233 #define MVPP2_BM_START_MASK BIT(0)
234 #define MVPP2_BM_STOP_MASK BIT(1)
235 #define MVPP2_BM_STATE_MASK BIT(4)
236 #define MVPP2_BM_LOW_THRESH_OFFS 8
237 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
238 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
239 MVPP2_BM_LOW_THRESH_OFFS)
240 #define MVPP2_BM_HIGH_THRESH_OFFS 16
241 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
242 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
243 MVPP2_BM_HIGH_THRESH_OFFS)
244 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
245 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
246 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
247 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
248 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
249 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
250 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
251 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
252 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
253 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
254 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
255 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
256 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
257 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
258 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
259 #define MVPP2_BM_MC_RLS_REG 0x64c4
260 #define MVPP2_BM_MC_ID_MASK 0xfff
261 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
263 /* TX Scheduler registers */
264 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
265 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
266 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
267 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
268 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
269 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
270 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
271 #define MVPP2_TXP_MTU_MAX 0x7FFFF
272 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
273 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
274 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
275 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
276 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
277 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
278 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
279 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
280 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
281 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
282 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
283 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
284 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
285 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
287 /* TX general registers */
288 #define MVPP2_TX_SNOOP_REG 0x8800
289 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
290 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
293 #define MVPP2_SRC_ADDR_MIDDLE 0x24
294 #define MVPP2_SRC_ADDR_HIGH 0x28
295 #define MVPP2_PHY_AN_CFG0_REG 0x34
296 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
297 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
298 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
300 /* Per-port registers */
301 #define MVPP2_GMAC_CTRL_0_REG 0x0
302 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
303 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
304 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
305 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
306 #define MVPP2_GMAC_CTRL_1_REG 0x4
307 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
308 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
309 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
310 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
311 #define MVPP2_GMAC_SA_LOW_OFFS 7
312 #define MVPP2_GMAC_CTRL_2_REG 0x8
313 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
314 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
315 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
316 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
317 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
318 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
319 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
320 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
321 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
322 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
323 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
324 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
325 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
326 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
327 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
328 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
329 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
330 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
332 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
334 /* Descriptor ring Macros */
335 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
336 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
338 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
339 #define MVPP2_SMI 0x0054
340 #define MVPP2_PHY_REG_MASK 0x1f
341 /* SMI register fields */
342 #define MVPP2_SMI_DATA_OFFS 0 /* Data */
343 #define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
344 #define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
345 #define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
346 #define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
347 #define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
348 #define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
349 #define MVPP2_SMI_BUSY (1 << 28) /* Busy */
351 #define MVPP2_PHY_ADDR_MASK 0x1f
352 #define MVPP2_PHY_REG_MASK 0x1f
354 /* Various constants */
357 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
358 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
359 #define MVPP2_RX_COAL_PKTS 32
360 #define MVPP2_RX_COAL_USEC 100
362 /* The two bytes Marvell header. Either contains a special value used
363 * by Marvell switches when a specific hardware mode is enabled (not
364 * supported by this driver) or is filled automatically by zeroes on
365 * the RX side. Those two bytes being at the front of the Ethernet
366 * header, they allow to have the IP header aligned on a 4 bytes
367 * boundary automatically: the hardware skips those two bytes on its
370 #define MVPP2_MH_SIZE 2
371 #define MVPP2_ETH_TYPE_LEN 2
372 #define MVPP2_PPPOE_HDR_SIZE 8
373 #define MVPP2_VLAN_TAG_LEN 4
375 /* Lbtd 802.3 type */
376 #define MVPP2_IP_LBDT_TYPE 0xfffa
378 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
379 #define MVPP2_TX_CSUM_MAX_SIZE 9800
381 /* Timeout constants */
382 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
383 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
385 #define MVPP2_TX_MTU_MAX 0x7ffff
387 /* Maximum number of T-CONTs of PON port */
388 #define MVPP2_MAX_TCONT 16
390 /* Maximum number of supported ports */
391 #define MVPP2_MAX_PORTS 4
393 /* Maximum number of TXQs used by single port */
394 #define MVPP2_MAX_TXQ 8
396 /* Maximum number of RXQs used by single port */
397 #define MVPP2_MAX_RXQ 8
399 /* Default number of TXQs in use */
400 #define MVPP2_DEFAULT_TXQ 1
402 /* Dfault number of RXQs in use */
403 #define MVPP2_DEFAULT_RXQ 1
404 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
406 /* Total number of RXQs available to all ports */
407 #define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
409 /* Max number of Rx descriptors */
410 #define MVPP2_MAX_RXD 16
412 /* Max number of Tx descriptors */
413 #define MVPP2_MAX_TXD 16
415 /* Amount of Tx descriptors that can be reserved at once by CPU */
416 #define MVPP2_CPU_DESC_CHUNK 64
418 /* Max number of Tx descriptors in each aggregated queue */
419 #define MVPP2_AGGR_TXQ_SIZE 256
421 /* Descriptor aligned size */
422 #define MVPP2_DESC_ALIGNED_SIZE 32
424 /* Descriptor alignment mask */
425 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
427 /* RX FIFO constants */
428 #define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
429 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
430 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
432 /* RX buffer constants */
433 #define MVPP2_SKB_SHINFO_SIZE \
436 #define MVPP2_RX_PKT_SIZE(mtu) \
437 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
438 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
440 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
441 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
442 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
443 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
445 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
447 /* IPv6 max L3 address size */
448 #define MVPP2_MAX_L3_ADDR_SIZE 16
451 #define MVPP2_F_LOOPBACK BIT(0)
453 /* Marvell tag types */
454 enum mvpp2_tag_type {
455 MVPP2_TAG_TYPE_NONE = 0,
456 MVPP2_TAG_TYPE_MH = 1,
457 MVPP2_TAG_TYPE_DSA = 2,
458 MVPP2_TAG_TYPE_EDSA = 3,
459 MVPP2_TAG_TYPE_VLAN = 4,
460 MVPP2_TAG_TYPE_LAST = 5
463 /* Parser constants */
464 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
465 #define MVPP2_PRS_TCAM_WORDS 6
466 #define MVPP2_PRS_SRAM_WORDS 4
467 #define MVPP2_PRS_FLOW_ID_SIZE 64
468 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
469 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
470 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
471 #define MVPP2_PRS_IPV4_HEAD 0x40
472 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
473 #define MVPP2_PRS_IPV4_MC 0xe0
474 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
475 #define MVPP2_PRS_IPV4_BC_MASK 0xff
476 #define MVPP2_PRS_IPV4_IHL 0x5
477 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
478 #define MVPP2_PRS_IPV6_MC 0xff
479 #define MVPP2_PRS_IPV6_MC_MASK 0xff
480 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
481 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
482 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
483 #define MVPP2_PRS_DBL_VLANS_MAX 100
486 * - lookup ID - 4 bits
488 * - additional information - 1 byte
489 * - header data - 8 bytes
490 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
492 #define MVPP2_PRS_AI_BITS 8
493 #define MVPP2_PRS_PORT_MASK 0xff
494 #define MVPP2_PRS_LU_MASK 0xf
495 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
496 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
497 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
498 (((offs) * 2) - ((offs) % 2) + 2)
499 #define MVPP2_PRS_TCAM_AI_BYTE 16
500 #define MVPP2_PRS_TCAM_PORT_BYTE 17
501 #define MVPP2_PRS_TCAM_LU_BYTE 20
502 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
503 #define MVPP2_PRS_TCAM_INV_WORD 5
504 /* Tcam entries ID */
505 #define MVPP2_PE_DROP_ALL 0
506 #define MVPP2_PE_FIRST_FREE_TID 1
507 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
508 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
509 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
510 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
511 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
512 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
513 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
514 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
515 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
516 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
517 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
518 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
519 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
520 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
521 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
522 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
523 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
524 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
525 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
526 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
527 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
528 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
529 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
530 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
531 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
534 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
536 #define MVPP2_PRS_SRAM_RI_OFFS 0
537 #define MVPP2_PRS_SRAM_RI_WORD 0
538 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
539 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
540 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
541 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
542 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
543 #define MVPP2_PRS_SRAM_UDF_OFFS 73
544 #define MVPP2_PRS_SRAM_UDF_BITS 8
545 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
546 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
547 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
548 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
549 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
550 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
551 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
552 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
553 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
554 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
555 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
556 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
557 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
558 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
559 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
560 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
561 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
562 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
563 #define MVPP2_PRS_SRAM_AI_OFFS 90
564 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
565 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
566 #define MVPP2_PRS_SRAM_AI_MASK 0xff
567 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
568 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
569 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
570 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
572 /* Sram result info bits assignment */
573 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
574 #define MVPP2_PRS_RI_DSA_MASK 0x2
575 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
576 #define MVPP2_PRS_RI_VLAN_NONE 0x0
577 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
578 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
579 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
580 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
581 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
582 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
583 #define MVPP2_PRS_RI_L2_UCAST 0x0
584 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
585 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
586 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
587 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
588 #define MVPP2_PRS_RI_L3_UN 0x0
589 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
590 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
591 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
592 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
593 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
594 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
595 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
596 #define MVPP2_PRS_RI_L3_UCAST 0x0
597 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
598 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
599 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
600 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
601 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
602 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
603 #define MVPP2_PRS_RI_L4_TCP BIT(22)
604 #define MVPP2_PRS_RI_L4_UDP BIT(23)
605 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
606 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
607 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
608 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
610 /* Sram additional info bits assignment */
611 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
612 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
613 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
614 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
615 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
616 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
617 #define MVPP2_PRS_SINGLE_VLAN_AI 0
618 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
621 #define MVPP2_PRS_TAGGED true
622 #define MVPP2_PRS_UNTAGGED false
623 #define MVPP2_PRS_EDSA true
624 #define MVPP2_PRS_DSA false
626 /* MAC entries, shadow udf */
628 MVPP2_PRS_UDF_MAC_DEF,
629 MVPP2_PRS_UDF_MAC_RANGE,
630 MVPP2_PRS_UDF_L2_DEF,
631 MVPP2_PRS_UDF_L2_DEF_COPY,
632 MVPP2_PRS_UDF_L2_USER,
636 enum mvpp2_prs_lookup {
650 enum mvpp2_prs_l3_cast {
651 MVPP2_PRS_L3_UNI_CAST,
652 MVPP2_PRS_L3_MULTI_CAST,
653 MVPP2_PRS_L3_BROAD_CAST
656 /* Classifier constants */
657 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
658 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
659 #define MVPP2_CLS_LKP_TBL_SIZE 64
662 #define MVPP2_BM_POOLS_NUM 1
663 #define MVPP2_BM_LONG_BUF_NUM 16
664 #define MVPP2_BM_SHORT_BUF_NUM 16
665 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
666 #define MVPP2_BM_POOL_PTR_ALIGN 128
667 #define MVPP2_BM_SWF_LONG_POOL(port) 0
669 /* BM cookie (32 bits) definition */
670 #define MVPP2_BM_COOKIE_POOL_OFFS 8
671 #define MVPP2_BM_COOKIE_CPU_OFFS 24
673 /* BM short pool packet size
674 * These value assure that for SWF the total number
675 * of bytes allocated for each buffer will be 512
677 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
687 /* Shared Packet Processor resources */
689 /* Shared registers' base addresses */
691 void __iomem *lms_base;
693 /* List of pointers to port structures */
694 struct mvpp2_port **port_list;
696 /* Aggregated TXQs */
697 struct mvpp2_tx_queue *aggr_txqs;
700 struct mvpp2_bm_pool *bm_pools;
702 /* PRS shadow table */
703 struct mvpp2_prs_shadow *prs_shadow;
704 /* PRS auxiliary table for double vlan entries control */
705 bool *prs_double_vlans;
713 struct mvpp2_pcpu_stats {
727 /* Per-port registers' base address */
730 struct mvpp2_rx_queue **rxqs;
731 struct mvpp2_tx_queue **txqs;
735 u32 pending_cause_rx;
737 /* Per-CPU port control */
738 struct mvpp2_port_pcpu __percpu *pcpu;
745 struct mvpp2_pcpu_stats __percpu *stats;
747 struct phy_device *phy_dev;
748 phy_interface_t phy_interface;
756 struct mvpp2_bm_pool *pool_long;
757 struct mvpp2_bm_pool *pool_short;
759 /* Index of first port's physical RXQ */
762 u8 dev_addr[ETH_ALEN];
765 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
766 * layout of the transmit and reception DMA descriptors, and their
767 * layout is therefore defined by the hardware design
770 #define MVPP2_TXD_L3_OFF_SHIFT 0
771 #define MVPP2_TXD_IP_HLEN_SHIFT 8
772 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
773 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
774 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
775 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
776 #define MVPP2_TXD_L4_UDP BIT(24)
777 #define MVPP2_TXD_L3_IP6 BIT(26)
778 #define MVPP2_TXD_L_DESC BIT(28)
779 #define MVPP2_TXD_F_DESC BIT(29)
781 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
782 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
783 #define MVPP2_RXD_ERR_CRC 0x0
784 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
785 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
786 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
787 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
788 #define MVPP2_RXD_HWF_SYNC BIT(21)
789 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
790 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
791 #define MVPP2_RXD_L4_TCP BIT(25)
792 #define MVPP2_RXD_L4_UDP BIT(26)
793 #define MVPP2_RXD_L3_IP4 BIT(28)
794 #define MVPP2_RXD_L3_IP6 BIT(30)
795 #define MVPP2_RXD_BUF_HDR BIT(31)
797 struct mvpp2_tx_desc {
798 u32 command; /* Options used by HW for packet transmitting.*/
799 u8 packet_offset; /* the offset from the buffer beginning */
800 u8 phys_txq; /* destination queue ID */
801 u16 data_size; /* data size of transmitted packet in bytes */
802 u32 buf_phys_addr; /* physical addr of transmitted buffer */
803 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
804 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
805 u32 reserved2; /* reserved (for future use) */
808 struct mvpp2_rx_desc {
809 u32 status; /* info about received packet */
810 u16 reserved1; /* parser_info (for future use, PnC) */
811 u16 data_size; /* size of received packet in bytes */
812 u32 buf_phys_addr; /* physical address of the buffer */
813 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
814 u16 reserved2; /* gem_port_id (for future use, PON) */
815 u16 reserved3; /* csum_l4 (for future use, PnC) */
816 u8 reserved4; /* bm_qset (for future use, BM) */
818 u16 reserved6; /* classify_info (for future use, PnC) */
819 u32 reserved7; /* flow_id (for future use, PnC) */
823 /* Per-CPU Tx queue control */
824 struct mvpp2_txq_pcpu {
827 /* Number of Tx DMA descriptors in the descriptor ring */
830 /* Number of currently used Tx DMA descriptor in the
835 /* Number of Tx DMA descriptors reserved for each CPU */
838 /* Index of last TX DMA descriptor that was inserted */
841 /* Index of the TX DMA descriptor to be cleaned up */
845 struct mvpp2_tx_queue {
846 /* Physical number of this Tx queue */
849 /* Logical number of this Tx queue */
852 /* Number of Tx DMA descriptors in the descriptor ring */
855 /* Number of currently used Tx DMA descriptor in the descriptor ring */
858 /* Per-CPU control of physical Tx queues */
859 struct mvpp2_txq_pcpu __percpu *pcpu;
863 /* Virtual address of thex Tx DMA descriptors array */
864 struct mvpp2_tx_desc *descs;
866 /* DMA address of the Tx DMA descriptors array */
867 dma_addr_t descs_phys;
869 /* Index of the last Tx DMA descriptor */
872 /* Index of the next Tx DMA descriptor to process */
873 int next_desc_to_proc;
876 struct mvpp2_rx_queue {
877 /* RX queue number, in the range 0-31 for physical RXQs */
880 /* Num of rx descriptors in the rx descriptor ring */
886 /* Virtual address of the RX DMA descriptors array */
887 struct mvpp2_rx_desc *descs;
889 /* DMA address of the RX DMA descriptors array */
890 dma_addr_t descs_phys;
892 /* Index of the last RX DMA descriptor */
895 /* Index of the next RX DMA descriptor to process */
896 int next_desc_to_proc;
898 /* ID of port to which physical RXQ is mapped */
901 /* Port's logic RXQ number to which physical RXQ is mapped */
905 union mvpp2_prs_tcam_entry {
906 u32 word[MVPP2_PRS_TCAM_WORDS];
907 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
910 union mvpp2_prs_sram_entry {
911 u32 word[MVPP2_PRS_SRAM_WORDS];
912 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
915 struct mvpp2_prs_entry {
917 union mvpp2_prs_tcam_entry tcam;
918 union mvpp2_prs_sram_entry sram;
921 struct mvpp2_prs_shadow {
928 /* User defined offset */
936 struct mvpp2_cls_flow_entry {
938 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
941 struct mvpp2_cls_lookup_entry {
947 struct mvpp2_bm_pool {
948 /* Pool number in the range 0-7 */
950 enum mvpp2_bm_type type;
952 /* Buffer Pointers Pool External (BPPE) size */
954 /* Number of buffers for this pool */
956 /* Pool buffer size */
961 /* BPPE virtual base address */
963 /* BPPE physical base address */
964 dma_addr_t phys_addr;
966 /* Ports using BM pool */
969 /* Occupied buffers indicator */
973 struct mvpp2_buff_hdr {
974 u32 next_buff_phys_addr;
975 u32 next_buff_virt_addr;
978 u8 reserved1; /* bm_qset (for future use, BM) */
981 /* Buffer header info bits */
982 #define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff
983 #define MVPP2_B_HDR_INFO_MC_ID(info) ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)
984 #define MVPP2_B_HDR_INFO_LAST_OFFS 12
985 #define MVPP2_B_HDR_INFO_LAST_MASK BIT(12)
986 #define MVPP2_B_HDR_INFO_IS_LAST(info) \
987 ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
989 /* Static declaractions */
991 /* Number of RXQs used by single port */
992 static int rxq_number = MVPP2_DEFAULT_RXQ;
993 /* Number of TXQs used by single port */
994 static int txq_number = MVPP2_DEFAULT_TXQ;
996 #define MVPP2_DRIVER_NAME "mvpp2"
997 #define MVPP2_DRIVER_VERSION "1.0"
1000 * U-Boot internal data, mostly uncached buffers for descriptors and data
1002 struct buffer_location {
1003 struct mvpp2_tx_desc *aggr_tx_descs;
1004 struct mvpp2_tx_desc *tx_descs;
1005 struct mvpp2_rx_desc *rx_descs;
1006 u32 *bm_pool[MVPP2_BM_POOLS_NUM];
1007 u32 *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
1012 * All 4 interfaces use the same global buffer, since only one interface
1013 * can be enabled at once
1015 static struct buffer_location buffer_loc;
1018 * Page table entries are set to 1MB, or multiples of 1MB
1019 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1021 #define BD_SPACE (1 << 20)
1023 /* Utility/helper methods */
1025 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1027 writel(data, priv->base + offset);
1030 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1032 return readl(priv->base + offset);
1035 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1037 txq_pcpu->txq_get_index++;
1038 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1039 txq_pcpu->txq_get_index = 0;
1042 /* Get number of physical egress port */
1043 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1045 return MVPP2_MAX_TCONT + port->id;
1048 /* Get number of physical TXQ */
1049 static inline int mvpp2_txq_phys(int port, int txq)
1051 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1054 /* Parser configuration routines */
1056 /* Update parser tcam and sram hw entries */
1057 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1061 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1064 /* Clear entry invalidation bit */
1065 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1067 /* Write tcam index - indirect access */
1068 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1069 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1070 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1072 /* Write sram index - indirect access */
1073 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1074 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1075 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1080 /* Read tcam entry from hw */
1081 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1085 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1088 /* Write tcam index - indirect access */
1089 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1091 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1092 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1093 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1094 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1096 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1097 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1099 /* Write sram index - indirect access */
1100 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1101 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1102 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1107 /* Invalidate tcam hw entry */
1108 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1110 /* Write index - indirect access */
1111 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1112 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1113 MVPP2_PRS_TCAM_INV_MASK);
1116 /* Enable shadow table entry and set its lookup ID */
1117 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1119 priv->prs_shadow[index].valid = true;
1120 priv->prs_shadow[index].lu = lu;
1123 /* Update ri fields in shadow table entry */
1124 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1125 unsigned int ri, unsigned int ri_mask)
1127 priv->prs_shadow[index].ri_mask = ri_mask;
1128 priv->prs_shadow[index].ri = ri;
1131 /* Update lookup field in tcam sw entry */
1132 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1134 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1136 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1137 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1140 /* Update mask for single port in tcam sw entry */
1141 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1142 unsigned int port, bool add)
1144 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1147 pe->tcam.byte[enable_off] &= ~(1 << port);
1149 pe->tcam.byte[enable_off] |= 1 << port;
1152 /* Update port map in tcam sw entry */
1153 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1156 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1157 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1159 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1160 pe->tcam.byte[enable_off] &= ~port_mask;
1161 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1164 /* Obtain port map from tcam sw entry */
1165 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1167 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1169 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1172 /* Set byte of data and its enable bits in tcam sw entry */
1173 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1174 unsigned int offs, unsigned char byte,
1175 unsigned char enable)
1177 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1178 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1181 /* Get byte of data and its enable bits from tcam sw entry */
1182 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1183 unsigned int offs, unsigned char *byte,
1184 unsigned char *enable)
1186 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1187 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1190 /* Set ethertype in tcam sw entry */
1191 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1192 unsigned short ethertype)
1194 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1195 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1198 /* Set bits in sram sw entry */
1199 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1202 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1205 /* Clear bits in sram sw entry */
1206 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1209 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1212 /* Update ri bits in sram sw entry */
1213 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1214 unsigned int bits, unsigned int mask)
1218 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1219 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1221 if (!(mask & BIT(i)))
1225 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1227 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1229 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1233 /* Update ai bits in sram sw entry */
1234 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1235 unsigned int bits, unsigned int mask)
1238 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1240 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1242 if (!(mask & BIT(i)))
1246 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1248 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1250 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1254 /* Read ai bits from sram sw entry */
1255 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1258 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1259 int ai_en_off = ai_off + 1;
1260 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1262 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1263 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1268 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1271 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1274 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1276 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1277 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1278 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1281 /* In the sram sw entry set sign and value of the next lookup offset
1282 * and the offset value generated to the classifier
1284 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1289 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1292 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1296 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1297 (unsigned char)shift;
1299 /* Reset and set operation */
1300 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1301 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1302 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1304 /* Set base offset as current */
1305 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1308 /* In the sram sw entry set sign and value of the user defined offset
1309 * generated to the classifier
1311 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1312 unsigned int type, int offset,
1317 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1318 offset = 0 - offset;
1320 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1324 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1325 MVPP2_PRS_SRAM_UDF_MASK);
1326 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1327 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1328 MVPP2_PRS_SRAM_UDF_BITS)] &=
1329 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1330 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1331 MVPP2_PRS_SRAM_UDF_BITS)] |=
1332 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1334 /* Set offset type */
1335 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1336 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1337 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1339 /* Set offset operation */
1340 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1341 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1342 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1344 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1345 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1346 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1347 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1349 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1350 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1351 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1353 /* Set base offset as current */
1354 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1357 /* Find parser flow entry */
1358 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1360 struct mvpp2_prs_entry *pe;
1363 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1366 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1368 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1369 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1372 if (!priv->prs_shadow[tid].valid ||
1373 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1377 mvpp2_prs_hw_read(priv, pe);
1378 bits = mvpp2_prs_sram_ai_get(pe);
1380 /* Sram store classification lookup ID in AI bits [5:0] */
1381 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1389 /* Return first free tcam index, seeking from start to end */
1390 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1398 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1399 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1401 for (tid = start; tid <= end; tid++) {
1402 if (!priv->prs_shadow[tid].valid)
1409 /* Enable/disable dropping all mac da's */
1410 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1412 struct mvpp2_prs_entry pe;
1414 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1415 /* Entry exist - update port only */
1416 pe.index = MVPP2_PE_DROP_ALL;
1417 mvpp2_prs_hw_read(priv, &pe);
1419 /* Entry doesn't exist - create new */
1420 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1421 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1422 pe.index = MVPP2_PE_DROP_ALL;
1424 /* Non-promiscuous mode for all ports - DROP unknown packets */
1425 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1426 MVPP2_PRS_RI_DROP_MASK);
1428 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1429 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1431 /* Update shadow table */
1432 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1434 /* Mask all ports */
1435 mvpp2_prs_tcam_port_map_set(&pe, 0);
1438 /* Update port mask */
1439 mvpp2_prs_tcam_port_set(&pe, port, add);
1441 mvpp2_prs_hw_write(priv, &pe);
1444 /* Set port to promiscuous mode */
1445 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1447 struct mvpp2_prs_entry pe;
1449 /* Promiscuous mode - Accept unknown packets */
1451 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1452 /* Entry exist - update port only */
1453 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1454 mvpp2_prs_hw_read(priv, &pe);
1456 /* Entry doesn't exist - create new */
1457 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1458 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1459 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1461 /* Continue - set next lookup */
1462 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1464 /* Set result info bits */
1465 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1466 MVPP2_PRS_RI_L2_CAST_MASK);
1468 /* Shift to ethertype */
1469 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1470 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1472 /* Mask all ports */
1473 mvpp2_prs_tcam_port_map_set(&pe, 0);
1475 /* Update shadow table */
1476 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1479 /* Update port mask */
1480 mvpp2_prs_tcam_port_set(&pe, port, add);
1482 mvpp2_prs_hw_write(priv, &pe);
1485 /* Accept multicast */
1486 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1489 struct mvpp2_prs_entry pe;
1490 unsigned char da_mc;
1492 /* Ethernet multicast address first byte is
1493 * 0x01 for IPv4 and 0x33 for IPv6
1495 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1497 if (priv->prs_shadow[index].valid) {
1498 /* Entry exist - update port only */
1500 mvpp2_prs_hw_read(priv, &pe);
1502 /* Entry doesn't exist - create new */
1503 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1504 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1507 /* Continue - set next lookup */
1508 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1510 /* Set result info bits */
1511 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1512 MVPP2_PRS_RI_L2_CAST_MASK);
1514 /* Update tcam entry data first byte */
1515 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1517 /* Shift to ethertype */
1518 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1519 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1521 /* Mask all ports */
1522 mvpp2_prs_tcam_port_map_set(&pe, 0);
1524 /* Update shadow table */
1525 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1528 /* Update port mask */
1529 mvpp2_prs_tcam_port_set(&pe, port, add);
1531 mvpp2_prs_hw_write(priv, &pe);
1534 /* Parser per-port initialization */
1535 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1536 int lu_max, int offset)
1541 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1542 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1543 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1544 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1546 /* Set maximum number of loops for packet received from port */
1547 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1548 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1549 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1550 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1552 /* Set initial offset for packet header extraction for the first
1555 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1556 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1557 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1558 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1561 /* Default flow entries initialization for all ports */
1562 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1564 struct mvpp2_prs_entry pe;
1567 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1568 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1569 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1570 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1572 /* Mask all ports */
1573 mvpp2_prs_tcam_port_map_set(&pe, 0);
1576 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1577 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1579 /* Update shadow table and hw entry */
1580 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1581 mvpp2_prs_hw_write(priv, &pe);
1585 /* Set default entry for Marvell Header field */
1586 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1588 struct mvpp2_prs_entry pe;
1590 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1592 pe.index = MVPP2_PE_MH_DEFAULT;
1593 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1594 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1595 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1596 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1598 /* Unmask all ports */
1599 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1601 /* Update shadow table and hw entry */
1602 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1603 mvpp2_prs_hw_write(priv, &pe);
1606 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1607 * multicast MAC addresses
1609 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1611 struct mvpp2_prs_entry pe;
1613 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1615 /* Non-promiscuous mode for all ports - DROP unknown packets */
1616 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1617 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1619 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1620 MVPP2_PRS_RI_DROP_MASK);
1621 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1622 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1624 /* Unmask all ports */
1625 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1627 /* Update shadow table and hw entry */
1628 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1629 mvpp2_prs_hw_write(priv, &pe);
1631 /* place holders only - no ports */
1632 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1633 mvpp2_prs_mac_promisc_set(priv, 0, false);
1634 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1635 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1638 /* Match basic ethertypes */
1639 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1641 struct mvpp2_prs_entry pe;
1644 /* Ethertype: PPPoE */
1645 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1646 MVPP2_PE_LAST_FREE_TID);
1650 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1651 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1654 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
1656 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1657 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1658 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1659 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1660 MVPP2_PRS_RI_PPPOE_MASK);
1662 /* Update shadow table and hw entry */
1663 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1664 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1665 priv->prs_shadow[pe.index].finish = false;
1666 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
1667 MVPP2_PRS_RI_PPPOE_MASK);
1668 mvpp2_prs_hw_write(priv, &pe);
1670 /* Ethertype: ARP */
1671 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1672 MVPP2_PE_LAST_FREE_TID);
1676 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1677 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1680 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
1682 /* Generate flow in the next iteration*/
1683 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1684 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1685 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
1686 MVPP2_PRS_RI_L3_PROTO_MASK);
1688 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1690 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1692 /* Update shadow table and hw entry */
1693 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1694 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1695 priv->prs_shadow[pe.index].finish = true;
1696 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
1697 MVPP2_PRS_RI_L3_PROTO_MASK);
1698 mvpp2_prs_hw_write(priv, &pe);
1700 /* Ethertype: LBTD */
1701 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1702 MVPP2_PE_LAST_FREE_TID);
1706 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1707 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1710 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
1712 /* Generate flow in the next iteration*/
1713 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1714 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1715 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1716 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1717 MVPP2_PRS_RI_CPU_CODE_MASK |
1718 MVPP2_PRS_RI_UDF3_MASK);
1720 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1722 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1724 /* Update shadow table and hw entry */
1725 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1726 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1727 priv->prs_shadow[pe.index].finish = true;
1728 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1729 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1730 MVPP2_PRS_RI_CPU_CODE_MASK |
1731 MVPP2_PRS_RI_UDF3_MASK);
1732 mvpp2_prs_hw_write(priv, &pe);
1734 /* Ethertype: IPv4 without options */
1735 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1736 MVPP2_PE_LAST_FREE_TID);
1740 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1741 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1744 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
1745 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1746 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
1747 MVPP2_PRS_IPV4_HEAD_MASK |
1748 MVPP2_PRS_IPV4_IHL_MASK);
1750 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1751 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
1752 MVPP2_PRS_RI_L3_PROTO_MASK);
1753 /* Skip eth_type + 4 bytes of IP header */
1754 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
1755 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1757 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1759 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1761 /* Update shadow table and hw entry */
1762 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1763 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1764 priv->prs_shadow[pe.index].finish = false;
1765 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
1766 MVPP2_PRS_RI_L3_PROTO_MASK);
1767 mvpp2_prs_hw_write(priv, &pe);
1769 /* Ethertype: IPv4 with options */
1770 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1771 MVPP2_PE_LAST_FREE_TID);
1777 /* Clear tcam data before updating */
1778 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
1779 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
1781 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1782 MVPP2_PRS_IPV4_HEAD,
1783 MVPP2_PRS_IPV4_HEAD_MASK);
1785 /* Clear ri before updating */
1786 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
1787 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
1788 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
1789 MVPP2_PRS_RI_L3_PROTO_MASK);
1791 /* Update shadow table and hw entry */
1792 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1793 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1794 priv->prs_shadow[pe.index].finish = false;
1795 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
1796 MVPP2_PRS_RI_L3_PROTO_MASK);
1797 mvpp2_prs_hw_write(priv, &pe);
1799 /* Ethertype: IPv6 without options */
1800 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1801 MVPP2_PE_LAST_FREE_TID);
1805 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1806 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1809 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
1811 /* Skip DIP of IPV6 header */
1812 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
1813 MVPP2_MAX_L3_ADDR_SIZE,
1814 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1815 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
1816 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
1817 MVPP2_PRS_RI_L3_PROTO_MASK);
1819 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1821 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1823 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1824 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1825 priv->prs_shadow[pe.index].finish = false;
1826 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
1827 MVPP2_PRS_RI_L3_PROTO_MASK);
1828 mvpp2_prs_hw_write(priv, &pe);
1830 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
1831 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1832 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1833 pe.index = MVPP2_PE_ETH_TYPE_UN;
1835 /* Unmask all ports */
1836 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1838 /* Generate flow in the next iteration*/
1839 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1840 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1841 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
1842 MVPP2_PRS_RI_L3_PROTO_MASK);
1843 /* Set L3 offset even it's unknown L3 */
1844 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1846 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1848 /* Update shadow table and hw entry */
1849 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1850 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1851 priv->prs_shadow[pe.index].finish = true;
1852 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
1853 MVPP2_PRS_RI_L3_PROTO_MASK);
1854 mvpp2_prs_hw_write(priv, &pe);
1859 /* Parser default initialization */
1860 static int mvpp2_prs_default_init(struct udevice *dev,
1865 /* Enable tcam table */
1866 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
1868 /* Clear all tcam and sram entries */
1869 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
1870 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1871 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1872 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
1874 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
1875 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1876 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
1879 /* Invalidate all tcam entries */
1880 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
1881 mvpp2_prs_hw_inv(priv, index);
1883 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
1884 sizeof(struct mvpp2_prs_shadow),
1886 if (!priv->prs_shadow)
1889 /* Always start from lookup = 0 */
1890 for (index = 0; index < MVPP2_MAX_PORTS; index++)
1891 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
1892 MVPP2_PRS_PORT_LU_MAX, 0);
1894 mvpp2_prs_def_flow_init(priv);
1896 mvpp2_prs_mh_init(priv);
1898 mvpp2_prs_mac_init(priv);
1900 err = mvpp2_prs_etype_init(priv);
1907 /* Compare MAC DA with tcam entry data */
1908 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
1909 const u8 *da, unsigned char *mask)
1911 unsigned char tcam_byte, tcam_mask;
1914 for (index = 0; index < ETH_ALEN; index++) {
1915 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
1916 if (tcam_mask != mask[index])
1919 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
1926 /* Find tcam entry with matched pair <MAC DA, port> */
1927 static struct mvpp2_prs_entry *
1928 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
1929 unsigned char *mask, int udf_type)
1931 struct mvpp2_prs_entry *pe;
1934 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1937 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
1939 /* Go through the all entires with MVPP2_PRS_LU_MAC */
1940 for (tid = MVPP2_PE_FIRST_FREE_TID;
1941 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
1942 unsigned int entry_pmap;
1944 if (!priv->prs_shadow[tid].valid ||
1945 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
1946 (priv->prs_shadow[tid].udf != udf_type))
1950 mvpp2_prs_hw_read(priv, pe);
1951 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
1953 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
1962 /* Update parser's mac da entry */
1963 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
1964 const u8 *da, bool add)
1966 struct mvpp2_prs_entry *pe;
1967 unsigned int pmap, len, ri;
1968 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1971 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
1972 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
1973 MVPP2_PRS_UDF_MAC_DEF);
1980 /* Create new TCAM entry */
1981 /* Find first range mac entry*/
1982 for (tid = MVPP2_PE_FIRST_FREE_TID;
1983 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
1984 if (priv->prs_shadow[tid].valid &&
1985 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
1986 (priv->prs_shadow[tid].udf ==
1987 MVPP2_PRS_UDF_MAC_RANGE))
1990 /* Go through the all entries from first to last */
1991 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1996 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1999 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2002 /* Mask all ports */
2003 mvpp2_prs_tcam_port_map_set(pe, 0);
2006 /* Update port mask */
2007 mvpp2_prs_tcam_port_set(pe, port, add);
2009 /* Invalidate the entry if no ports are left enabled */
2010 pmap = mvpp2_prs_tcam_port_map_get(pe);
2016 mvpp2_prs_hw_inv(priv, pe->index);
2017 priv->prs_shadow[pe->index].valid = false;
2022 /* Continue - set next lookup */
2023 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2025 /* Set match on DA */
2028 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2030 /* Set result info bits */
2031 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2033 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2034 MVPP2_PRS_RI_MAC_ME_MASK);
2035 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2036 MVPP2_PRS_RI_MAC_ME_MASK);
2038 /* Shift to ethertype */
2039 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2040 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2042 /* Update shadow table and hw entry */
2043 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2044 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2045 mvpp2_prs_hw_write(priv, pe);
2052 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2056 /* Remove old parser entry */
2057 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2062 /* Add new parser entry */
2063 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2067 /* Set addr in the device */
2068 memcpy(port->dev_addr, da, ETH_ALEN);
2073 /* Set prs flow for the port */
2074 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2076 struct mvpp2_prs_entry *pe;
2079 pe = mvpp2_prs_flow_find(port->priv, port->id);
2081 /* Such entry not exist */
2083 /* Go through the all entires from last to first */
2084 tid = mvpp2_prs_tcam_first_free(port->priv,
2085 MVPP2_PE_LAST_FREE_TID,
2086 MVPP2_PE_FIRST_FREE_TID);
2090 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2094 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2098 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2099 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2101 /* Update shadow table */
2102 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2105 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2106 mvpp2_prs_hw_write(port->priv, pe);
2112 /* Classifier configuration routines */
2114 /* Update classification flow table registers */
2115 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2116 struct mvpp2_cls_flow_entry *fe)
2118 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2119 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2120 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2121 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2124 /* Update classification lookup table register */
2125 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2126 struct mvpp2_cls_lookup_entry *le)
2130 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2131 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2132 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2135 /* Classifier default initialization */
2136 static void mvpp2_cls_init(struct mvpp2 *priv)
2138 struct mvpp2_cls_lookup_entry le;
2139 struct mvpp2_cls_flow_entry fe;
2142 /* Enable classifier */
2143 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2145 /* Clear classifier flow table */
2146 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2147 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2149 mvpp2_cls_flow_write(priv, &fe);
2152 /* Clear classifier lookup table */
2154 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2157 mvpp2_cls_lookup_write(priv, &le);
2160 mvpp2_cls_lookup_write(priv, &le);
2164 static void mvpp2_cls_port_config(struct mvpp2_port *port)
2166 struct mvpp2_cls_lookup_entry le;
2169 /* Set way for the port */
2170 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2171 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2172 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2174 /* Pick the entry to be accessed in lookup ID decoding table
2175 * according to the way and lkpid.
2177 le.lkpid = port->id;
2181 /* Set initial CPU queue for receiving packets */
2182 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2183 le.data |= port->first_rxq;
2185 /* Disable classification engines */
2186 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2188 /* Update lookup ID table entry */
2189 mvpp2_cls_lookup_write(port->priv, &le);
2192 /* Set CPU queue number for oversize packets */
2193 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2197 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2198 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2200 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2201 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2203 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2204 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2205 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2208 /* Buffer Manager configuration routines */
2211 static int mvpp2_bm_pool_create(struct udevice *dev,
2213 struct mvpp2_bm_pool *bm_pool, int size)
2217 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
2218 bm_pool->phys_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
2219 if (!bm_pool->virt_addr)
2222 if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVPP2_BM_POOL_PTR_ALIGN)) {
2223 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2224 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2228 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
2229 bm_pool->phys_addr);
2230 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2232 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2233 val |= MVPP2_BM_START_MASK;
2234 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2236 bm_pool->type = MVPP2_BM_FREE;
2237 bm_pool->size = size;
2238 bm_pool->pkt_size = 0;
2239 bm_pool->buf_num = 0;
2244 /* Set pool buffer size */
2245 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2246 struct mvpp2_bm_pool *bm_pool,
2251 bm_pool->buf_size = buf_size;
2253 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2254 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2257 /* Free all buffers from the pool */
2258 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2259 struct mvpp2_bm_pool *bm_pool)
2261 bm_pool->buf_num = 0;
2265 static int mvpp2_bm_pool_destroy(struct udevice *dev,
2267 struct mvpp2_bm_pool *bm_pool)
2271 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2272 if (bm_pool->buf_num) {
2273 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2277 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2278 val |= MVPP2_BM_STOP_MASK;
2279 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2284 static int mvpp2_bm_pools_init(struct udevice *dev,
2288 struct mvpp2_bm_pool *bm_pool;
2290 /* Create all pools with maximum size */
2291 size = MVPP2_BM_POOL_SIZE_MAX;
2292 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2293 bm_pool = &priv->bm_pools[i];
2295 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2297 goto err_unroll_pools;
2298 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
2303 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2304 for (i = i - 1; i >= 0; i--)
2305 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2309 static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2313 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2314 /* Mask BM all interrupts */
2315 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2316 /* Clear BM cause register */
2317 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2320 /* Allocate and initialize BM pools */
2321 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2322 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2323 if (!priv->bm_pools)
2326 err = mvpp2_bm_pools_init(dev, priv);
2332 /* Attach long pool to rxq */
2333 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2334 int lrxq, int long_pool)
2339 /* Get queue physical ID */
2340 prxq = port->rxqs[lrxq]->id;
2342 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2343 val &= ~MVPP2_RXQ_POOL_LONG_MASK;
2344 val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) &
2345 MVPP2_RXQ_POOL_LONG_MASK);
2347 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2350 /* Set pool number in a BM cookie */
2351 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2355 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2356 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2361 /* Get pool number from a BM cookie */
2362 static inline int mvpp2_bm_cookie_pool_get(u32 cookie)
2364 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2367 /* Release buffer to BM */
2368 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
2369 u32 buf_phys_addr, u32 buf_virt_addr)
2371 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
2372 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr);
2375 /* Refill BM pool */
2376 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
2377 u32 phys_addr, u32 cookie)
2379 int pool = mvpp2_bm_cookie_pool_get(bm);
2381 mvpp2_bm_pool_put(port, pool, phys_addr, cookie);
2384 /* Allocate buffers for the pool */
2385 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2386 struct mvpp2_bm_pool *bm_pool, int buf_num)
2391 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2392 netdev_err(port->dev,
2393 "cannot allocate %d buffers for pool %d\n",
2394 buf_num, bm_pool->id);
2398 for (i = 0; i < buf_num; i++) {
2399 mvpp2_bm_pool_put(port, bm_pool->id,
2400 (u32)buffer_loc.rx_buffer[i],
2401 (u32)buffer_loc.rx_buffer[i]);
2405 /* Update BM driver with number of buffers added to pool */
2406 bm_pool->buf_num += i;
2407 bm_pool->in_use_thresh = bm_pool->buf_num / 4;
2412 /* Notify the driver that BM pool is being used as specific type and return the
2413 * pool pointer on success
2415 static struct mvpp2_bm_pool *
2416 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2419 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2422 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2423 netdev_err(port->dev, "mixing pool types is forbidden\n");
2427 if (new_pool->type == MVPP2_BM_FREE)
2428 new_pool->type = type;
2430 /* Allocate buffers in case BM pool is used as long pool, but packet
2431 * size doesn't match MTU or BM pool hasn't being used yet
2433 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2434 (new_pool->pkt_size == 0)) {
2437 /* Set default buffer number or free all the buffers in case
2438 * the pool is not empty
2440 pkts_num = new_pool->buf_num;
2442 pkts_num = type == MVPP2_BM_SWF_LONG ?
2443 MVPP2_BM_LONG_BUF_NUM :
2444 MVPP2_BM_SHORT_BUF_NUM;
2446 mvpp2_bm_bufs_free(NULL,
2447 port->priv, new_pool);
2449 new_pool->pkt_size = pkt_size;
2451 /* Allocate buffers for this pool */
2452 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2453 if (num != pkts_num) {
2454 dev_err(dev, "pool %d: %d of %d allocated\n",
2455 new_pool->id, num, pkts_num);
2460 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
2461 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
2466 /* Initialize pools for swf */
2467 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2471 if (!port->pool_long) {
2473 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2476 if (!port->pool_long)
2479 port->pool_long->port_map |= (1 << port->id);
2481 for (rxq = 0; rxq < rxq_number; rxq++)
2482 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2488 /* Port configuration routines */
2490 static void mvpp2_port_mii_set(struct mvpp2_port *port)
2494 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2496 switch (port->phy_interface) {
2497 case PHY_INTERFACE_MODE_SGMII:
2498 val |= MVPP2_GMAC_INBAND_AN_MASK;
2500 case PHY_INTERFACE_MODE_RGMII:
2501 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2503 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2506 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2509 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2513 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2514 val |= MVPP2_GMAC_FC_ADV_EN;
2515 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2518 static void mvpp2_port_enable(struct mvpp2_port *port)
2522 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2523 val |= MVPP2_GMAC_PORT_EN_MASK;
2524 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2525 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2528 static void mvpp2_port_disable(struct mvpp2_port *port)
2532 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2533 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2534 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2537 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2538 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2542 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2543 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2544 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2547 /* Configure loopback port */
2548 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2552 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2554 if (port->speed == 1000)
2555 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2557 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2559 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2560 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2562 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2564 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2567 static void mvpp2_port_reset(struct mvpp2_port *port)
2571 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2572 ~MVPP2_GMAC_PORT_RESET_MASK;
2573 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2575 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2576 MVPP2_GMAC_PORT_RESET_MASK)
2580 /* Change maximum receive size of the port */
2581 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2585 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2586 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2587 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2588 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2589 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2592 /* Set defaults to the MVPP2 port */
2593 static void mvpp2_defaults_set(struct mvpp2_port *port)
2595 int tx_port_num, val, queue, ptxq, lrxq;
2597 /* Configure port to loopback if needed */
2598 if (port->flags & MVPP2_F_LOOPBACK)
2599 mvpp2_port_loopback_set(port);
2601 /* Update TX FIFO MIN Threshold */
2602 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2603 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
2604 /* Min. TX threshold must be less than minimal packet length */
2605 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2606 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2608 /* Disable Legacy WRR, Disable EJP, Release from reset */
2609 tx_port_num = mvpp2_egress_port(port);
2610 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
2612 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
2614 /* Close bandwidth for all queues */
2615 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
2616 ptxq = mvpp2_txq_phys(port->id, queue);
2617 mvpp2_write(port->priv,
2618 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
2621 /* Set refill period to 1 usec, refill tokens
2622 * and bucket size to maximum
2624 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
2625 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
2626 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
2627 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2628 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
2629 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
2630 val = MVPP2_TXP_TOKEN_SIZE_MAX;
2631 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2633 /* Set MaximumLowLatencyPacketSize value to 256 */
2634 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
2635 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
2636 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2638 /* Enable Rx cache snoop */
2639 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2640 queue = port->rxqs[lrxq]->id;
2641 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2642 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
2643 MVPP2_SNOOP_BUF_HDR_MASK;
2644 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2648 /* Enable/disable receiving packets */
2649 static void mvpp2_ingress_enable(struct mvpp2_port *port)
2654 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2655 queue = port->rxqs[lrxq]->id;
2656 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2657 val &= ~MVPP2_RXQ_DISABLE_MASK;
2658 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2662 static void mvpp2_ingress_disable(struct mvpp2_port *port)
2667 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2668 queue = port->rxqs[lrxq]->id;
2669 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2670 val |= MVPP2_RXQ_DISABLE_MASK;
2671 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2675 /* Enable transmit via physical egress queue
2676 * - HW starts take descriptors from DRAM
2678 static void mvpp2_egress_enable(struct mvpp2_port *port)
2682 int tx_port_num = mvpp2_egress_port(port);
2684 /* Enable all initialized TXs. */
2686 for (queue = 0; queue < txq_number; queue++) {
2687 struct mvpp2_tx_queue *txq = port->txqs[queue];
2689 if (txq->descs != NULL)
2690 qmap |= (1 << queue);
2693 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2694 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2697 /* Disable transmit via physical egress queue
2698 * - HW doesn't take descriptors from DRAM
2700 static void mvpp2_egress_disable(struct mvpp2_port *port)
2704 int tx_port_num = mvpp2_egress_port(port);
2706 /* Issue stop command for active channels only */
2707 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2708 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2709 MVPP2_TXP_SCHED_ENQ_MASK;
2711 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2712 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2714 /* Wait for all Tx activity to terminate. */
2717 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2718 netdev_warn(port->dev,
2719 "Tx stop timed out, status=0x%08x\n",
2726 /* Check port TX Command register that all
2727 * Tx queues are stopped
2729 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2730 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2733 /* Rx descriptors helper methods */
2735 /* Get number of Rx descriptors occupied by received packets */
2737 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2739 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2741 return val & MVPP2_RXQ_OCCUPIED_MASK;
2744 /* Update Rx queue status with the number of occupied and available
2745 * Rx descriptor slots.
2748 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2749 int used_count, int free_count)
2751 /* Decrement the number of used descriptors and increment count
2752 * increment the number of free descriptors.
2754 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2756 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2759 /* Get pointer to next RX descriptor to be processed by SW */
2760 static inline struct mvpp2_rx_desc *
2761 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
2763 int rx_desc = rxq->next_desc_to_proc;
2765 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
2766 prefetch(rxq->descs + rxq->next_desc_to_proc);
2767 return rxq->descs + rx_desc;
2770 /* Set rx queue offset */
2771 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
2772 int prxq, int offset)
2776 /* Convert offset from bytes to units of 32 bytes */
2777 offset = offset >> 5;
2779 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2780 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
2783 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
2784 MVPP2_RXQ_PACKET_OFFSET_MASK);
2786 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2789 /* Obtain BM cookie information from descriptor */
2790 static u32 mvpp2_bm_cookie_build(struct mvpp2_rx_desc *rx_desc)
2792 int pool = (rx_desc->status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2793 MVPP2_RXD_BM_POOL_ID_OFFS;
2794 int cpu = smp_processor_id();
2796 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
2797 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
2800 /* Tx descriptors helper methods */
2802 /* Get number of Tx descriptors waiting to be transmitted by HW */
2803 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
2804 struct mvpp2_tx_queue *txq)
2808 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
2809 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
2811 return val & MVPP2_TXQ_PENDING_MASK;
2814 /* Get pointer to next Tx descriptor to be processed (send) by HW */
2815 static struct mvpp2_tx_desc *
2816 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
2818 int tx_desc = txq->next_desc_to_proc;
2820 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
2821 return txq->descs + tx_desc;
2824 /* Update HW with number of aggregated Tx descriptors to be sent */
2825 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
2827 /* aggregated access - relevant TXQ number is written in TX desc */
2828 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
2831 /* Get number of sent descriptors and decrement counter.
2832 * The number of sent descriptors is returned.
2835 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
2836 struct mvpp2_tx_queue *txq)
2840 /* Reading status reg resets transmitted descriptor counter */
2841 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
2843 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
2844 MVPP2_TRANSMITTED_COUNT_OFFSET;
2847 static void mvpp2_txq_sent_counter_clear(void *arg)
2849 struct mvpp2_port *port = arg;
2852 for (queue = 0; queue < txq_number; queue++) {
2853 int id = port->txqs[queue]->id;
2855 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
2859 /* Set max sizes for Tx queues */
2860 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
2863 int txq, tx_port_num;
2865 mtu = port->pkt_size * 8;
2866 if (mtu > MVPP2_TXP_MTU_MAX)
2867 mtu = MVPP2_TXP_MTU_MAX;
2869 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
2872 /* Indirect access to registers */
2873 tx_port_num = mvpp2_egress_port(port);
2874 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2877 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
2878 val &= ~MVPP2_TXP_MTU_MAX;
2880 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
2882 /* TXP token size and all TXQs token size must be larger that MTU */
2883 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
2884 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
2887 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
2889 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2892 for (txq = 0; txq < txq_number; txq++) {
2893 val = mvpp2_read(port->priv,
2894 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
2895 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
2899 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
2901 mvpp2_write(port->priv,
2902 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
2908 /* Free Tx queue skbuffs */
2909 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
2910 struct mvpp2_tx_queue *txq,
2911 struct mvpp2_txq_pcpu *txq_pcpu, int num)
2915 for (i = 0; i < num; i++)
2916 mvpp2_txq_inc_get(txq_pcpu);
2919 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
2922 int queue = fls(cause) - 1;
2924 return port->rxqs[queue];
2927 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
2930 int queue = fls(cause) - 1;
2932 return port->txqs[queue];
2935 /* Rx/Tx queue initialization/cleanup methods */
2937 /* Allocate and initialize descriptors for aggr TXQ */
2938 static int mvpp2_aggr_txq_init(struct udevice *dev,
2939 struct mvpp2_tx_queue *aggr_txq,
2940 int desc_num, int cpu,
2943 /* Allocate memory for TX descriptors */
2944 aggr_txq->descs = buffer_loc.aggr_tx_descs;
2945 aggr_txq->descs_phys = (dma_addr_t)buffer_loc.aggr_tx_descs;
2946 if (!aggr_txq->descs)
2949 /* Make sure descriptor address is cache line size aligned */
2950 BUG_ON(aggr_txq->descs !=
2951 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
2953 aggr_txq->last_desc = aggr_txq->size - 1;
2955 /* Aggr TXQ no reset WA */
2956 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2957 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
2959 /* Set Tx descriptors queue starting address */
2960 /* indirect access */
2961 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu),
2962 aggr_txq->descs_phys);
2963 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
2968 /* Create a specified Rx queue */
2969 static int mvpp2_rxq_init(struct mvpp2_port *port,
2970 struct mvpp2_rx_queue *rxq)
2973 rxq->size = port->rx_ring_size;
2975 /* Allocate memory for RX descriptors */
2976 rxq->descs = buffer_loc.rx_descs;
2977 rxq->descs_phys = (dma_addr_t)buffer_loc.rx_descs;
2981 BUG_ON(rxq->descs !=
2982 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
2984 rxq->last_desc = rxq->size - 1;
2986 /* Zero occupied and non-occupied counters - direct access */
2987 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2989 /* Set Rx descriptors queue starting address - indirect access */
2990 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
2991 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_phys);
2992 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2993 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
2996 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
2998 /* Add number of descriptors ready for receiving packets */
2999 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
3004 /* Push packets received by the RXQ to BM pool */
3005 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
3006 struct mvpp2_rx_queue *rxq)
3010 rx_received = mvpp2_rxq_received(port, rxq->id);
3014 for (i = 0; i < rx_received; i++) {
3015 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3016 u32 bm = mvpp2_bm_cookie_build(rx_desc);
3018 mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
3019 rx_desc->buf_cookie);
3021 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
3024 /* Cleanup Rx queue */
3025 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
3026 struct mvpp2_rx_queue *rxq)
3028 mvpp2_rxq_drop_pkts(port, rxq);
3032 rxq->next_desc_to_proc = 0;
3033 rxq->descs_phys = 0;
3035 /* Clear Rx descriptors queue starting address and size;
3036 * free descriptor number
3038 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3039 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
3040 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
3041 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
3044 /* Create and initialize a Tx queue */
3045 static int mvpp2_txq_init(struct mvpp2_port *port,
3046 struct mvpp2_tx_queue *txq)
3049 int cpu, desc, desc_per_txq, tx_port_num;
3050 struct mvpp2_txq_pcpu *txq_pcpu;
3052 txq->size = port->tx_ring_size;
3054 /* Allocate memory for Tx descriptors */
3055 txq->descs = buffer_loc.tx_descs;
3056 txq->descs_phys = (dma_addr_t)buffer_loc.tx_descs;
3060 /* Make sure descriptor address is cache line size aligned */
3061 BUG_ON(txq->descs !=
3062 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3064 txq->last_desc = txq->size - 1;
3066 /* Set Tx descriptors queue starting address - indirect access */
3067 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3068 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_phys);
3069 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
3070 MVPP2_TXQ_DESC_SIZE_MASK);
3071 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
3072 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
3073 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
3074 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3075 val &= ~MVPP2_TXQ_PENDING_MASK;
3076 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
3078 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
3079 * for each existing TXQ.
3080 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3081 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
3084 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
3085 (txq->log_id * desc_per_txq);
3087 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
3088 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
3089 MVPP2_PREF_BUF_THRESH(desc_per_txq/2));
3091 /* WRR / EJP configuration - indirect access */
3092 tx_port_num = mvpp2_egress_port(port);
3093 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3095 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
3096 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
3097 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3098 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
3099 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
3101 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
3102 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
3105 for_each_present_cpu(cpu) {
3106 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3107 txq_pcpu->size = txq->size;
3113 /* Free allocated TXQ resources */
3114 static void mvpp2_txq_deinit(struct mvpp2_port *port,
3115 struct mvpp2_tx_queue *txq)
3119 txq->next_desc_to_proc = 0;
3120 txq->descs_phys = 0;
3122 /* Set minimum bandwidth for disabled TXQs */
3123 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
3125 /* Set Tx descriptors queue starting address and size */
3126 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3127 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
3128 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
3131 /* Cleanup Tx ports */
3132 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
3134 struct mvpp2_txq_pcpu *txq_pcpu;
3135 int delay, pending, cpu;
3138 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3139 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
3140 val |= MVPP2_TXQ_DRAIN_EN_MASK;
3141 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3143 /* The napi queue has been stopped so wait for all packets
3144 * to be transmitted.
3148 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
3149 netdev_warn(port->dev,
3150 "port %d: cleaning queue %d timed out\n",
3151 port->id, txq->log_id);
3157 pending = mvpp2_txq_pend_desc_num_get(port, txq);
3160 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
3161 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3163 for_each_present_cpu(cpu) {
3164 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3166 /* Release all packets */
3167 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
3170 txq_pcpu->count = 0;
3171 txq_pcpu->txq_put_index = 0;
3172 txq_pcpu->txq_get_index = 0;
3176 /* Cleanup all Tx queues */
3177 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
3179 struct mvpp2_tx_queue *txq;
3183 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
3185 /* Reset Tx ports and delete Tx queues */
3186 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
3187 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3189 for (queue = 0; queue < txq_number; queue++) {
3190 txq = port->txqs[queue];
3191 mvpp2_txq_clean(port, txq);
3192 mvpp2_txq_deinit(port, txq);
3195 mvpp2_txq_sent_counter_clear(port);
3197 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
3198 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3201 /* Cleanup all Rx queues */
3202 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
3206 for (queue = 0; queue < rxq_number; queue++)
3207 mvpp2_rxq_deinit(port, port->rxqs[queue]);
3210 /* Init all Rx queues for port */
3211 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
3215 for (queue = 0; queue < rxq_number; queue++) {
3216 err = mvpp2_rxq_init(port, port->rxqs[queue]);
3223 mvpp2_cleanup_rxqs(port);
3227 /* Init all tx queues for port */
3228 static int mvpp2_setup_txqs(struct mvpp2_port *port)
3230 struct mvpp2_tx_queue *txq;
3233 for (queue = 0; queue < txq_number; queue++) {
3234 txq = port->txqs[queue];
3235 err = mvpp2_txq_init(port, txq);
3240 mvpp2_txq_sent_counter_clear(port);
3244 mvpp2_cleanup_txqs(port);
3249 static void mvpp2_link_event(struct mvpp2_port *port)
3251 struct phy_device *phydev = port->phy_dev;
3252 int status_change = 0;
3256 if ((port->speed != phydev->speed) ||
3257 (port->duplex != phydev->duplex)) {
3260 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3261 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
3262 MVPP2_GMAC_CONFIG_GMII_SPEED |
3263 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3264 MVPP2_GMAC_AN_SPEED_EN |
3265 MVPP2_GMAC_AN_DUPLEX_EN);
3268 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
3270 if (phydev->speed == SPEED_1000)
3271 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
3272 else if (phydev->speed == SPEED_100)
3273 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
3275 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3277 port->duplex = phydev->duplex;
3278 port->speed = phydev->speed;
3282 if (phydev->link != port->link) {
3283 if (!phydev->link) {
3288 port->link = phydev->link;
3292 if (status_change) {
3294 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3295 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
3296 MVPP2_GMAC_FORCE_LINK_DOWN);
3297 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3298 mvpp2_egress_enable(port);
3299 mvpp2_ingress_enable(port);
3301 mvpp2_ingress_disable(port);
3302 mvpp2_egress_disable(port);
3307 /* Main RX/TX processing routines */
3309 /* Display more error info */
3310 static void mvpp2_rx_error(struct mvpp2_port *port,
3311 struct mvpp2_rx_desc *rx_desc)
3313 u32 status = rx_desc->status;
3315 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3316 case MVPP2_RXD_ERR_CRC:
3317 netdev_err(port->dev, "bad rx status %08x (crc error), size=%d\n",
3318 status, rx_desc->data_size);
3320 case MVPP2_RXD_ERR_OVERRUN:
3321 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%d\n",
3322 status, rx_desc->data_size);
3324 case MVPP2_RXD_ERR_RESOURCE:
3325 netdev_err(port->dev, "bad rx status %08x (resource error), size=%d\n",
3326 status, rx_desc->data_size);
3331 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
3332 static int mvpp2_rx_refill(struct mvpp2_port *port,
3333 struct mvpp2_bm_pool *bm_pool,
3334 u32 bm, u32 phys_addr)
3336 mvpp2_pool_refill(port, bm, phys_addr, phys_addr);
3340 /* Set hw internals when starting port */
3341 static void mvpp2_start_dev(struct mvpp2_port *port)
3343 mvpp2_gmac_max_rx_size_set(port);
3344 mvpp2_txp_max_tx_size_set(port);
3346 mvpp2_port_enable(port);
3349 /* Set hw internals when stopping port */
3350 static void mvpp2_stop_dev(struct mvpp2_port *port)
3352 /* Stop new packets from arriving to RXQs */
3353 mvpp2_ingress_disable(port);
3355 mvpp2_egress_disable(port);
3356 mvpp2_port_disable(port);
3359 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
3361 struct phy_device *phy_dev;
3363 if (!port->init || port->link == 0) {
3364 phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
3365 port->phy_interface);
3366 port->phy_dev = phy_dev;
3368 netdev_err(port->dev, "cannot connect to phy\n");
3371 phy_dev->supported &= PHY_GBIT_FEATURES;
3372 phy_dev->advertising = phy_dev->supported;
3374 port->phy_dev = phy_dev;
3379 phy_config(phy_dev);
3380 phy_startup(phy_dev);
3381 if (!phy_dev->link) {
3382 printf("%s: No link\n", phy_dev->dev->name);
3388 mvpp2_egress_enable(port);
3389 mvpp2_ingress_enable(port);
3395 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
3397 unsigned char mac_bcast[ETH_ALEN] = {
3398 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3401 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
3403 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3406 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
3407 port->dev_addr, true);
3409 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
3412 err = mvpp2_prs_def_flow(port);
3414 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3418 /* Allocate the Rx/Tx queues */
3419 err = mvpp2_setup_rxqs(port);
3421 netdev_err(port->dev, "cannot allocate Rx queues\n");
3425 err = mvpp2_setup_txqs(port);
3427 netdev_err(port->dev, "cannot allocate Tx queues\n");
3431 err = mvpp2_phy_connect(dev, port);
3435 mvpp2_link_event(port);
3437 mvpp2_start_dev(port);
3442 /* No Device ops here in U-Boot */
3444 /* Driver initialization */
3446 static void mvpp2_port_power_up(struct mvpp2_port *port)
3448 mvpp2_port_mii_set(port);
3449 mvpp2_port_periodic_xon_disable(port);
3450 mvpp2_port_fc_adv_enable(port);
3451 mvpp2_port_reset(port);
3454 /* Initialize port HW */
3455 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
3457 struct mvpp2 *priv = port->priv;
3458 struct mvpp2_txq_pcpu *txq_pcpu;
3459 int queue, cpu, err;
3461 if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM)
3465 mvpp2_egress_disable(port);
3466 mvpp2_port_disable(port);
3468 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
3473 /* Associate physical Tx queues to this port and initialize.
3474 * The mapping is predefined.
3476 for (queue = 0; queue < txq_number; queue++) {
3477 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
3478 struct mvpp2_tx_queue *txq;
3480 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
3484 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
3489 txq->id = queue_phy_id;
3490 txq->log_id = queue;
3491 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
3492 for_each_present_cpu(cpu) {
3493 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3494 txq_pcpu->cpu = cpu;
3497 port->txqs[queue] = txq;
3500 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
3505 /* Allocate and initialize Rx queue for this port */
3506 for (queue = 0; queue < rxq_number; queue++) {
3507 struct mvpp2_rx_queue *rxq;
3509 /* Map physical Rx queue to port's logical Rx queue */
3510 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
3513 /* Map this Rx queue to a physical queue */
3514 rxq->id = port->first_rxq + queue;
3515 rxq->port = port->id;
3516 rxq->logic_rxq = queue;
3518 port->rxqs[queue] = rxq;
3521 /* Configure Rx queue group interrupt for this port */
3522 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), CONFIG_MV_ETH_RXQ);
3524 /* Create Rx descriptor rings */
3525 for (queue = 0; queue < rxq_number; queue++) {
3526 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3528 rxq->size = port->rx_ring_size;
3529 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
3530 rxq->time_coal = MVPP2_RX_COAL_USEC;
3533 mvpp2_ingress_disable(port);
3535 /* Port default configuration */
3536 mvpp2_defaults_set(port);
3538 /* Port's classifier configuration */
3539 mvpp2_cls_oversize_rxq_set(port);
3540 mvpp2_cls_port_config(port);
3542 /* Provide an initial Rx packet size */
3543 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
3545 /* Initialize pools for swf */
3546 err = mvpp2_swf_bm_pool_init(port);
3553 /* Ports initialization */
3554 static int mvpp2_port_probe(struct udevice *dev,
3555 struct mvpp2_port *port,
3558 int *next_first_rxq)
3563 const char *phy_mode_str;
3565 int priv_common_regs_num = 2;
3568 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
3570 dev_err(&pdev->dev, "missing phy\n");
3574 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
3576 phy_mode = phy_get_interface_by_name(phy_mode_str);
3577 if (phy_mode == -1) {
3578 dev_err(&pdev->dev, "incorrect phy mode\n");
3582 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
3584 dev_err(&pdev->dev, "missing port-id value\n");
3588 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
3592 port->first_rxq = *next_first_rxq;
3593 port->phy_node = phy_node;
3594 port->phy_interface = phy_mode;
3595 port->phyaddr = phyaddr;
3597 port->base = (void __iomem *)dev_get_addr_index(dev->parent,
3598 priv_common_regs_num
3600 if (IS_ERR(port->base))
3601 return PTR_ERR(port->base);
3603 port->tx_ring_size = MVPP2_MAX_TXD;
3604 port->rx_ring_size = MVPP2_MAX_RXD;
3606 err = mvpp2_port_init(dev, port);
3608 dev_err(&pdev->dev, "failed to init port %d\n", id);
3611 mvpp2_port_power_up(port);
3613 /* Increment the first Rx queue number to be used by the next port */
3614 *next_first_rxq += CONFIG_MV_ETH_RXQ;
3615 priv->port_list[id] = port;
3619 /* Initialize decoding windows */
3620 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
3626 for (i = 0; i < 6; i++) {
3627 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
3628 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
3631 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
3636 for (i = 0; i < dram->num_cs; i++) {
3637 const struct mbus_dram_window *cs = dram->cs + i;
3639 mvpp2_write(priv, MVPP2_WIN_BASE(i),
3640 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
3641 dram->mbus_dram_target_id);
3643 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
3644 (cs->size - 1) & 0xffff0000);
3646 win_enable |= (1 << i);
3649 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
3652 /* Initialize Rx FIFO's */
3653 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
3657 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
3658 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
3659 MVPP2_RX_FIFO_PORT_DATA_SIZE);
3660 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
3661 MVPP2_RX_FIFO_PORT_ATTR_SIZE);
3664 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
3665 MVPP2_RX_FIFO_PORT_MIN_PKT);
3666 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
3669 /* Initialize network controller common part HW */
3670 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
3672 const struct mbus_dram_target_info *dram_target_info;
3676 /* Checks for hardware constraints (U-Boot uses only one rxq) */
3677 if ((rxq_number > MVPP2_MAX_RXQ) || (txq_number > MVPP2_MAX_TXQ)) {
3678 dev_err(&pdev->dev, "invalid queue size parameter\n");
3682 /* MBUS windows configuration */
3683 dram_target_info = mvebu_mbus_dram_info();
3684 if (dram_target_info)
3685 mvpp2_conf_mbus_windows(dram_target_info, priv);
3687 /* Disable HW PHY polling */
3688 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
3689 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
3690 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
3692 /* Allocate and initialize aggregated TXQs */
3693 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
3694 sizeof(struct mvpp2_tx_queue),
3696 if (!priv->aggr_txqs)
3699 for_each_present_cpu(i) {
3700 priv->aggr_txqs[i].id = i;
3701 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
3702 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
3703 MVPP2_AGGR_TXQ_SIZE, i, priv);
3709 mvpp2_rx_fifo_init(priv);
3711 /* Reset Rx queue group interrupt configuration */
3712 for (i = 0; i < MVPP2_MAX_PORTS; i++)
3713 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i),
3716 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
3717 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
3719 /* Allow cache snoop when transmiting packets */
3720 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
3722 /* Buffer Manager initialization */
3723 err = mvpp2_bm_init(dev, priv);
3727 /* Parser default initialization */
3728 err = mvpp2_prs_default_init(dev, priv);
3732 /* Classifier default initialization */
3733 mvpp2_cls_init(priv);
3738 /* SMI / MDIO functions */
3740 static int smi_wait_ready(struct mvpp2 *priv)
3742 u32 timeout = MVPP2_SMI_TIMEOUT;
3745 /* wait till the SMI is not busy */
3747 /* read smi register */
3748 smi_reg = readl(priv->lms_base + MVPP2_SMI);
3749 if (timeout-- == 0) {
3750 printf("Error: SMI busy timeout\n");
3753 } while (smi_reg & MVPP2_SMI_BUSY);
3759 * mpp2_mdio_read - miiphy_read callback function.
3761 * Returns 16bit phy register value, or 0xffff on error
3763 static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
3765 struct mvpp2 *priv = bus->priv;
3769 /* check parameters */
3770 if (addr > MVPP2_PHY_ADDR_MASK) {
3771 printf("Error: Invalid PHY address %d\n", addr);
3775 if (reg > MVPP2_PHY_REG_MASK) {
3776 printf("Err: Invalid register offset %d\n", reg);
3780 /* wait till the SMI is not busy */
3781 if (smi_wait_ready(priv) < 0)
3784 /* fill the phy address and regiser offset and read opcode */
3785 smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS)
3786 | (reg << MVPP2_SMI_REG_ADDR_OFFS)
3787 | MVPP2_SMI_OPCODE_READ;
3789 /* write the smi register */
3790 writel(smi_reg, priv->lms_base + MVPP2_SMI);
3792 /* wait till read value is ready */
3793 timeout = MVPP2_SMI_TIMEOUT;
3796 /* read smi register */
3797 smi_reg = readl(priv->lms_base + MVPP2_SMI);
3798 if (timeout-- == 0) {
3799 printf("Err: SMI read ready timeout\n");
3802 } while (!(smi_reg & MVPP2_SMI_READ_VALID));
3804 /* Wait for the data to update in the SMI register */
3805 for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
3808 return readl(priv->lms_base + MVPP2_SMI) & MVPP2_SMI_DATA_MASK;
3812 * mpp2_mdio_write - miiphy_write callback function.
3814 * Returns 0 if write succeed, -EINVAL on bad parameters
3817 static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
3820 struct mvpp2 *priv = bus->priv;
3823 /* check parameters */
3824 if (addr > MVPP2_PHY_ADDR_MASK) {
3825 printf("Error: Invalid PHY address %d\n", addr);
3829 if (reg > MVPP2_PHY_REG_MASK) {
3830 printf("Err: Invalid register offset %d\n", reg);
3834 /* wait till the SMI is not busy */
3835 if (smi_wait_ready(priv) < 0)
3838 /* fill the phy addr and reg offset and write opcode and data */
3839 smi_reg = value << MVPP2_SMI_DATA_OFFS;
3840 smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS)
3841 | (reg << MVPP2_SMI_REG_ADDR_OFFS);
3842 smi_reg &= ~MVPP2_SMI_OPCODE_READ;
3844 /* write the smi register */
3845 writel(smi_reg, priv->lms_base + MVPP2_SMI);
3850 static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
3852 struct mvpp2_port *port = dev_get_priv(dev);
3853 struct mvpp2_rx_desc *rx_desc;
3854 struct mvpp2_bm_pool *bm_pool;
3855 dma_addr_t phys_addr;
3857 int pool, rx_bytes, err;
3859 struct mvpp2_rx_queue *rxq;
3860 u32 cause_rx_tx, cause_rx, cause_misc;
3863 cause_rx_tx = mvpp2_read(port->priv,
3864 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
3865 cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3866 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
3867 if (!cause_rx_tx && !cause_misc)
3870 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
3872 /* Process RX packets */
3873 cause_rx |= port->pending_cause_rx;
3874 rxq = mvpp2_get_rx_queue(port, cause_rx);
3876 /* Get number of received packets and clamp the to-do */
3877 rx_received = mvpp2_rxq_received(port, rxq->id);
3879 /* Return if no packets are received */
3883 rx_desc = mvpp2_rxq_next_desc_get(rxq);
3884 rx_status = rx_desc->status;
3885 rx_bytes = rx_desc->data_size - MVPP2_MH_SIZE;
3886 phys_addr = rx_desc->buf_phys_addr;
3888 bm = mvpp2_bm_cookie_build(rx_desc);
3889 pool = mvpp2_bm_cookie_pool_get(bm);
3890 bm_pool = &port->priv->bm_pools[pool];
3892 /* Check if buffer header is used */
3893 if (rx_status & MVPP2_RXD_BUF_HDR)
3896 /* In case of an error, release the requested buffer pointer
3897 * to the Buffer Manager. This request process is controlled
3898 * by the hardware, and the information about the buffer is
3899 * comprised by the RX descriptor.
3901 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
3902 mvpp2_rx_error(port, rx_desc);
3903 /* Return the buffer to the pool */
3904 mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
3905 rx_desc->buf_cookie);
3909 err = mvpp2_rx_refill(port, bm_pool, bm, phys_addr);
3911 netdev_err(port->dev, "failed to refill BM pools\n");
3915 /* Update Rx queue management counters */
3917 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
3919 /* give packet to stack - skip on first n bytes */
3920 data = (u8 *)phys_addr + 2 + 32;
3926 * No cache invalidation needed here, since the rx_buffer's are
3927 * located in a uncached memory region
3935 static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
3940 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3941 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
3943 val |= MVPP2_TXQ_DRAIN_EN_MASK;
3945 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
3946 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3949 static int mvpp2_send(struct udevice *dev, void *packet, int length)
3951 struct mvpp2_port *port = dev_get_priv(dev);
3952 struct mvpp2_tx_queue *txq, *aggr_txq;
3953 struct mvpp2_tx_desc *tx_desc;
3957 txq = port->txqs[0];
3958 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
3960 /* Get a descriptor for the first part of the packet */
3961 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3962 tx_desc->phys_txq = txq->id;
3963 tx_desc->data_size = length;
3964 tx_desc->packet_offset = (u32)packet & MVPP2_TX_DESC_ALIGN;
3965 tx_desc->buf_phys_addr = (u32)packet & ~MVPP2_TX_DESC_ALIGN;
3966 /* First and Last descriptor */
3967 tx_desc->command = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
3968 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
3971 flush_dcache_range((unsigned long)packet,
3972 (unsigned long)packet + ALIGN(length, PKTALIGN));
3974 /* Enable transmit */
3976 mvpp2_aggr_txq_pend_desc_add(port, 1);
3978 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3982 if (timeout++ > 10000) {
3983 printf("timeout: packet not sent from aggregated to phys TXQ\n");
3986 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
3989 /* Enable TXQ drain */
3990 mvpp2_txq_drain(port, txq, 1);
3994 if (timeout++ > 10000) {
3995 printf("timeout: packet not sent\n");
3998 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
4001 /* Disable TXQ drain */
4002 mvpp2_txq_drain(port, txq, 0);
4007 static int mvpp2_start(struct udevice *dev)
4009 struct eth_pdata *pdata = dev_get_platdata(dev);
4010 struct mvpp2_port *port = dev_get_priv(dev);
4012 /* Load current MAC address */
4013 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
4015 /* Reconfigure parser accept the original MAC address */
4016 mvpp2_prs_update_mac_da(port, port->dev_addr);
4018 mvpp2_port_power_up(port);
4020 mvpp2_open(dev, port);
4025 static void mvpp2_stop(struct udevice *dev)
4027 struct mvpp2_port *port = dev_get_priv(dev);
4029 mvpp2_stop_dev(port);
4030 mvpp2_cleanup_rxqs(port);
4031 mvpp2_cleanup_txqs(port);
4034 static int mvpp2_probe(struct udevice *dev)
4036 struct mvpp2_port *port = dev_get_priv(dev);
4037 struct mvpp2 *priv = dev_get_priv(dev->parent);
4040 /* Initialize network controller */
4041 err = mvpp2_init(dev, priv);
4043 dev_err(&pdev->dev, "failed to initialize controller\n");
4047 return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv,
4048 &buffer_loc.first_rxq);
4051 static const struct eth_ops mvpp2_ops = {
4052 .start = mvpp2_start,
4058 static struct driver mvpp2_driver = {
4061 .probe = mvpp2_probe,
4063 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
4064 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
4068 * Use a MISC device to bind the n instances (child nodes) of the
4069 * network base controller in UCLASS_ETH.
4071 static int mvpp2_base_probe(struct udevice *dev)
4073 struct mvpp2 *priv = dev_get_priv(dev);
4074 struct mii_dev *bus;
4080 * U-Boot special buffer handling:
4082 * Allocate buffer area for descs and rx_buffers. This is only
4083 * done once for all interfaces. As only one interface can
4084 * be active. Make this area DMA-safe by disabling the D-cache
4087 /* Align buffer area for descs and rx_buffers to 1MiB */
4088 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
4089 mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
4091 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
4092 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
4094 buffer_loc.tx_descs = (struct mvpp2_tx_desc *)((u32)bd_space + size);
4095 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
4097 buffer_loc.rx_descs = (struct mvpp2_rx_desc *)((u32)bd_space + size);
4098 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
4100 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
4101 buffer_loc.bm_pool[i] = (u32 *)((u32)bd_space + size);
4102 size += MVPP2_BM_POOL_SIZE_MAX * sizeof(u32);
4105 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
4106 buffer_loc.rx_buffer[i] = (u32 *)((u32)bd_space + size);
4107 size += RX_BUFFER_SIZE;
4110 /* Save base addresses for later use */
4111 priv->base = (void *)dev_get_addr_index(dev, 0);
4112 if (IS_ERR(priv->base))
4113 return PTR_ERR(priv->base);
4115 priv->lms_base = (void *)dev_get_addr_index(dev, 1);
4116 if (IS_ERR(priv->lms_base))
4117 return PTR_ERR(priv->lms_base);
4119 /* Finally create and register the MDIO bus driver */
4122 printf("Failed to allocate MDIO bus\n");
4126 bus->read = mpp2_mdio_read;
4127 bus->write = mpp2_mdio_write;
4128 snprintf(bus->name, sizeof(bus->name), dev->name);
4129 bus->priv = (void *)priv;
4132 return mdio_register(bus);
4135 static int mvpp2_base_bind(struct udevice *parent)
4137 const void *blob = gd->fdt_blob;
4138 int node = dev_of_offset(parent);
4139 struct uclass_driver *drv;
4140 struct udevice *dev;
4141 struct eth_pdata *plat;
4146 /* Lookup eth driver */
4147 drv = lists_uclass_lookup(UCLASS_ETH);
4149 puts("Cannot find eth driver\n");
4153 fdt_for_each_subnode(subnode, blob, node) {
4154 /* Skip disabled ports */
4155 if (!fdtdec_get_is_enabled(blob, subnode))
4158 plat = calloc(1, sizeof(*plat));
4162 id = fdtdec_get_int(blob, subnode, "port-id", -1);
4164 name = calloc(1, 16);
4165 sprintf(name, "mvpp2-%d", id);
4167 /* Create child device UCLASS_ETH and bind it */
4168 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
4169 dev_set_of_offset(dev, subnode);
4175 static const struct udevice_id mvpp2_ids[] = {
4176 { .compatible = "marvell,armada-375-pp2" },
4180 U_BOOT_DRIVER(mvpp2_base) = {
4181 .name = "mvpp2_base",
4183 .of_match = mvpp2_ids,
4184 .bind = mvpp2_base_bind,
4185 .probe = mvpp2_base_probe,
4186 .priv_auto_alloc_size = sizeof(struct mvpp2),