2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
18 #include <dm/device-internal.h>
25 #include <linux/errno.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/soc.h>
31 #include <linux/compat.h>
32 #include <linux/mbus.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 /* Some linux -> U-Boot compatibility stuff */
37 #define netdev_err(dev, fmt, args...) \
39 #define netdev_warn(dev, fmt, args...) \
41 #define netdev_info(dev, fmt, args...) \
43 #define netdev_dbg(dev, fmt, args...) \
46 #define ETH_ALEN 6 /* Octets in one ethernet addr */
48 #define __verify_pcpu_ptr(ptr) \
50 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
54 #define VERIFY_PERCPU_PTR(__p) \
56 __verify_pcpu_ptr(__p); \
57 (typeof(*(__p)) __kernel __force *)(__p); \
60 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
61 #define smp_processor_id() 0
62 #define num_present_cpus() 1
63 #define for_each_present_cpu(cpu) \
64 for ((cpu) = 0; (cpu) < 1; (cpu)++)
66 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
68 #define CONFIG_NR_CPUS 1
69 #define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
71 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
72 #define WRAP (2 + ETH_HLEN + 4 + 32)
74 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
76 #define MVPP2_SMI_TIMEOUT 10000
78 /* RX Fifo Registers */
79 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
80 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
81 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
82 #define MVPP2_RX_FIFO_INIT_REG 0x64
84 /* RX DMA Top Registers */
85 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
86 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
87 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
88 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
89 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
90 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
91 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
92 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
93 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
94 #define MVPP2_RXQ_POOL_SHORT_MASK 0x700000
95 #define MVPP2_RXQ_POOL_LONG_OFFS 24
96 #define MVPP2_RXQ_POOL_LONG_MASK 0x7000000
97 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
98 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
99 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
101 /* Parser Registers */
102 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
103 #define MVPP2_PRS_PORT_LU_MAX 0xf
104 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
105 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
106 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
107 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
108 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
109 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
110 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
111 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
112 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
113 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
114 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
115 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
117 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
118 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
120 /* Classifier Registers */
121 #define MVPP2_CLS_MODE_REG 0x1800
122 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
123 #define MVPP2_CLS_PORT_WAY_REG 0x1810
124 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
125 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
126 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
127 #define MVPP2_CLS_LKP_TBL_REG 0x1818
128 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
129 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
130 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
131 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
132 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
133 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
134 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
135 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
136 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
137 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
139 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
141 /* Descriptor Manager Top Registers */
142 #define MVPP2_RXQ_NUM_REG 0x2040
143 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
144 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
145 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
146 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
147 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
148 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
149 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
150 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
151 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
152 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
153 #define MVPP2_RXQ_THRESH_REG 0x204c
154 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
155 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
156 #define MVPP2_RXQ_INDEX_REG 0x2050
157 #define MVPP2_TXQ_NUM_REG 0x2080
158 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
159 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
160 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
161 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
162 #define MVPP2_TXQ_THRESH_REG 0x2094
163 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
164 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
165 #define MVPP2_TXQ_INDEX_REG 0x2098
166 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
167 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
168 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
169 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
170 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
171 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
172 #define MVPP2_TXQ_PENDING_REG 0x20a0
173 #define MVPP2_TXQ_PENDING_MASK 0x3fff
174 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
175 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
176 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
177 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
178 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
179 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
180 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
181 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
182 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
183 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
184 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
185 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
186 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
187 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
188 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
189 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
191 /* MBUS bridge registers */
192 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
193 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
194 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
195 #define MVPP2_BASE_ADDR_ENABLE 0x4060
197 /* Interrupt Cause and Mask registers */
198 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
199 #define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
200 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
201 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
202 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
203 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
204 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
205 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
206 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
207 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
208 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
209 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
210 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
211 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
212 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
213 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
214 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
215 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
216 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
217 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
219 /* Buffer Manager registers */
220 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
221 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
222 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
223 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
224 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
225 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
226 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
227 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
228 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
229 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
230 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
231 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
232 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
233 #define MVPP2_BM_START_MASK BIT(0)
234 #define MVPP2_BM_STOP_MASK BIT(1)
235 #define MVPP2_BM_STATE_MASK BIT(4)
236 #define MVPP2_BM_LOW_THRESH_OFFS 8
237 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
238 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
239 MVPP2_BM_LOW_THRESH_OFFS)
240 #define MVPP2_BM_HIGH_THRESH_OFFS 16
241 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
242 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
243 MVPP2_BM_HIGH_THRESH_OFFS)
244 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
245 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
246 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
247 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
248 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
249 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
250 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
251 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
252 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
253 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
254 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
255 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
256 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
257 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
258 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
259 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
260 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
261 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
262 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
263 #define MVPP21_BM_MC_RLS_REG 0x64c4
264 #define MVPP2_BM_MC_ID_MASK 0xfff
265 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
266 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
267 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
268 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
269 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
270 #define MVPP22_BM_MC_RLS_REG 0x64d4
272 /* TX Scheduler registers */
273 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
274 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
275 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
276 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
277 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
278 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
279 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
280 #define MVPP2_TXP_MTU_MAX 0x7FFFF
281 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
282 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
283 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
284 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
285 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
286 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
287 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
288 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
289 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
290 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
291 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
292 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
293 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
294 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
296 /* TX general registers */
297 #define MVPP2_TX_SNOOP_REG 0x8800
298 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
299 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
302 #define MVPP2_SRC_ADDR_MIDDLE 0x24
303 #define MVPP2_SRC_ADDR_HIGH 0x28
304 #define MVPP2_PHY_AN_CFG0_REG 0x34
305 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
306 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
307 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
309 /* Per-port registers */
310 #define MVPP2_GMAC_CTRL_0_REG 0x0
311 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
312 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
313 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
314 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
315 #define MVPP2_GMAC_CTRL_1_REG 0x4
316 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
317 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
318 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
319 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
320 #define MVPP2_GMAC_SA_LOW_OFFS 7
321 #define MVPP2_GMAC_CTRL_2_REG 0x8
322 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
323 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
324 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
325 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
326 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
327 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
328 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
329 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
330 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
331 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
332 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
333 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
334 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
335 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
336 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
337 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
338 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
339 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
341 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
343 /* Descriptor ring Macros */
344 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
345 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
347 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
348 #define MVPP2_SMI 0x0054
349 #define MVPP2_PHY_REG_MASK 0x1f
350 /* SMI register fields */
351 #define MVPP2_SMI_DATA_OFFS 0 /* Data */
352 #define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
353 #define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
354 #define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
355 #define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
356 #define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
357 #define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
358 #define MVPP2_SMI_BUSY (1 << 28) /* Busy */
360 #define MVPP2_PHY_ADDR_MASK 0x1f
361 #define MVPP2_PHY_REG_MASK 0x1f
363 /* Various constants */
366 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
367 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
368 #define MVPP2_RX_COAL_PKTS 32
369 #define MVPP2_RX_COAL_USEC 100
371 /* The two bytes Marvell header. Either contains a special value used
372 * by Marvell switches when a specific hardware mode is enabled (not
373 * supported by this driver) or is filled automatically by zeroes on
374 * the RX side. Those two bytes being at the front of the Ethernet
375 * header, they allow to have the IP header aligned on a 4 bytes
376 * boundary automatically: the hardware skips those two bytes on its
379 #define MVPP2_MH_SIZE 2
380 #define MVPP2_ETH_TYPE_LEN 2
381 #define MVPP2_PPPOE_HDR_SIZE 8
382 #define MVPP2_VLAN_TAG_LEN 4
384 /* Lbtd 802.3 type */
385 #define MVPP2_IP_LBDT_TYPE 0xfffa
387 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
388 #define MVPP2_TX_CSUM_MAX_SIZE 9800
390 /* Timeout constants */
391 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
392 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
394 #define MVPP2_TX_MTU_MAX 0x7ffff
396 /* Maximum number of T-CONTs of PON port */
397 #define MVPP2_MAX_TCONT 16
399 /* Maximum number of supported ports */
400 #define MVPP2_MAX_PORTS 4
402 /* Maximum number of TXQs used by single port */
403 #define MVPP2_MAX_TXQ 8
405 /* Maximum number of RXQs used by single port */
406 #define MVPP2_MAX_RXQ 8
408 /* Default number of TXQs in use */
409 #define MVPP2_DEFAULT_TXQ 1
411 /* Dfault number of RXQs in use */
412 #define MVPP2_DEFAULT_RXQ 1
413 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
415 /* Total number of RXQs available to all ports */
416 #define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
418 /* Max number of Rx descriptors */
419 #define MVPP2_MAX_RXD 16
421 /* Max number of Tx descriptors */
422 #define MVPP2_MAX_TXD 16
424 /* Amount of Tx descriptors that can be reserved at once by CPU */
425 #define MVPP2_CPU_DESC_CHUNK 64
427 /* Max number of Tx descriptors in each aggregated queue */
428 #define MVPP2_AGGR_TXQ_SIZE 256
430 /* Descriptor aligned size */
431 #define MVPP2_DESC_ALIGNED_SIZE 32
433 /* Descriptor alignment mask */
434 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
436 /* RX FIFO constants */
437 #define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
438 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
439 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
441 /* RX buffer constants */
442 #define MVPP2_SKB_SHINFO_SIZE \
445 #define MVPP2_RX_PKT_SIZE(mtu) \
446 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
447 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
449 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
450 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
451 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
452 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
454 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
456 /* IPv6 max L3 address size */
457 #define MVPP2_MAX_L3_ADDR_SIZE 16
460 #define MVPP2_F_LOOPBACK BIT(0)
462 /* Marvell tag types */
463 enum mvpp2_tag_type {
464 MVPP2_TAG_TYPE_NONE = 0,
465 MVPP2_TAG_TYPE_MH = 1,
466 MVPP2_TAG_TYPE_DSA = 2,
467 MVPP2_TAG_TYPE_EDSA = 3,
468 MVPP2_TAG_TYPE_VLAN = 4,
469 MVPP2_TAG_TYPE_LAST = 5
472 /* Parser constants */
473 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
474 #define MVPP2_PRS_TCAM_WORDS 6
475 #define MVPP2_PRS_SRAM_WORDS 4
476 #define MVPP2_PRS_FLOW_ID_SIZE 64
477 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
478 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
479 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
480 #define MVPP2_PRS_IPV4_HEAD 0x40
481 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
482 #define MVPP2_PRS_IPV4_MC 0xe0
483 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
484 #define MVPP2_PRS_IPV4_BC_MASK 0xff
485 #define MVPP2_PRS_IPV4_IHL 0x5
486 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
487 #define MVPP2_PRS_IPV6_MC 0xff
488 #define MVPP2_PRS_IPV6_MC_MASK 0xff
489 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
490 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
491 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
492 #define MVPP2_PRS_DBL_VLANS_MAX 100
495 * - lookup ID - 4 bits
497 * - additional information - 1 byte
498 * - header data - 8 bytes
499 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
501 #define MVPP2_PRS_AI_BITS 8
502 #define MVPP2_PRS_PORT_MASK 0xff
503 #define MVPP2_PRS_LU_MASK 0xf
504 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
505 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
506 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
507 (((offs) * 2) - ((offs) % 2) + 2)
508 #define MVPP2_PRS_TCAM_AI_BYTE 16
509 #define MVPP2_PRS_TCAM_PORT_BYTE 17
510 #define MVPP2_PRS_TCAM_LU_BYTE 20
511 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
512 #define MVPP2_PRS_TCAM_INV_WORD 5
513 /* Tcam entries ID */
514 #define MVPP2_PE_DROP_ALL 0
515 #define MVPP2_PE_FIRST_FREE_TID 1
516 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
517 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
518 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
519 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
520 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
521 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
522 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
523 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
524 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
525 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
526 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
527 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
528 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
529 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
530 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
531 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
532 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
533 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
534 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
535 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
536 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
537 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
538 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
539 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
540 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
543 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
545 #define MVPP2_PRS_SRAM_RI_OFFS 0
546 #define MVPP2_PRS_SRAM_RI_WORD 0
547 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
548 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
549 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
550 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
551 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
552 #define MVPP2_PRS_SRAM_UDF_OFFS 73
553 #define MVPP2_PRS_SRAM_UDF_BITS 8
554 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
555 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
556 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
557 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
558 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
559 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
560 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
561 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
562 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
563 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
564 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
565 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
566 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
567 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
568 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
569 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
570 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
571 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
572 #define MVPP2_PRS_SRAM_AI_OFFS 90
573 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
574 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
575 #define MVPP2_PRS_SRAM_AI_MASK 0xff
576 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
577 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
578 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
579 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
581 /* Sram result info bits assignment */
582 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
583 #define MVPP2_PRS_RI_DSA_MASK 0x2
584 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
585 #define MVPP2_PRS_RI_VLAN_NONE 0x0
586 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
587 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
588 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
589 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
590 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
591 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
592 #define MVPP2_PRS_RI_L2_UCAST 0x0
593 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
594 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
595 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
596 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
597 #define MVPP2_PRS_RI_L3_UN 0x0
598 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
599 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
600 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
601 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
602 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
603 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
604 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
605 #define MVPP2_PRS_RI_L3_UCAST 0x0
606 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
607 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
608 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
609 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
610 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
611 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
612 #define MVPP2_PRS_RI_L4_TCP BIT(22)
613 #define MVPP2_PRS_RI_L4_UDP BIT(23)
614 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
615 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
616 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
617 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
619 /* Sram additional info bits assignment */
620 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
621 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
622 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
623 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
624 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
625 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
626 #define MVPP2_PRS_SINGLE_VLAN_AI 0
627 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
630 #define MVPP2_PRS_TAGGED true
631 #define MVPP2_PRS_UNTAGGED false
632 #define MVPP2_PRS_EDSA true
633 #define MVPP2_PRS_DSA false
635 /* MAC entries, shadow udf */
637 MVPP2_PRS_UDF_MAC_DEF,
638 MVPP2_PRS_UDF_MAC_RANGE,
639 MVPP2_PRS_UDF_L2_DEF,
640 MVPP2_PRS_UDF_L2_DEF_COPY,
641 MVPP2_PRS_UDF_L2_USER,
645 enum mvpp2_prs_lookup {
659 enum mvpp2_prs_l3_cast {
660 MVPP2_PRS_L3_UNI_CAST,
661 MVPP2_PRS_L3_MULTI_CAST,
662 MVPP2_PRS_L3_BROAD_CAST
665 /* Classifier constants */
666 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
667 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
668 #define MVPP2_CLS_LKP_TBL_SIZE 64
671 #define MVPP2_BM_POOLS_NUM 1
672 #define MVPP2_BM_LONG_BUF_NUM 16
673 #define MVPP2_BM_SHORT_BUF_NUM 16
674 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
675 #define MVPP2_BM_POOL_PTR_ALIGN 128
676 #define MVPP2_BM_SWF_LONG_POOL(port) 0
678 /* BM cookie (32 bits) definition */
679 #define MVPP2_BM_COOKIE_POOL_OFFS 8
680 #define MVPP2_BM_COOKIE_CPU_OFFS 24
682 /* BM short pool packet size
683 * These value assure that for SWF the total number
684 * of bytes allocated for each buffer will be 512
686 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
696 /* Shared Packet Processor resources */
698 /* Shared registers' base addresses */
700 void __iomem *lms_base;
702 /* List of pointers to port structures */
703 struct mvpp2_port **port_list;
705 /* Aggregated TXQs */
706 struct mvpp2_tx_queue *aggr_txqs;
709 struct mvpp2_bm_pool *bm_pools;
711 /* PRS shadow table */
712 struct mvpp2_prs_shadow *prs_shadow;
713 /* PRS auxiliary table for double vlan entries control */
714 bool *prs_double_vlans;
720 enum { MVPP21, MVPP22 } hw_version;
725 struct mvpp2_pcpu_stats {
739 /* Per-port registers' base address */
742 struct mvpp2_rx_queue **rxqs;
743 struct mvpp2_tx_queue **txqs;
747 u32 pending_cause_rx;
749 /* Per-CPU port control */
750 struct mvpp2_port_pcpu __percpu *pcpu;
757 struct mvpp2_pcpu_stats __percpu *stats;
759 struct phy_device *phy_dev;
760 phy_interface_t phy_interface;
768 struct mvpp2_bm_pool *pool_long;
769 struct mvpp2_bm_pool *pool_short;
771 /* Index of first port's physical RXQ */
774 u8 dev_addr[ETH_ALEN];
777 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
778 * layout of the transmit and reception DMA descriptors, and their
779 * layout is therefore defined by the hardware design
782 #define MVPP2_TXD_L3_OFF_SHIFT 0
783 #define MVPP2_TXD_IP_HLEN_SHIFT 8
784 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
785 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
786 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
787 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
788 #define MVPP2_TXD_L4_UDP BIT(24)
789 #define MVPP2_TXD_L3_IP6 BIT(26)
790 #define MVPP2_TXD_L_DESC BIT(28)
791 #define MVPP2_TXD_F_DESC BIT(29)
793 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
794 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
795 #define MVPP2_RXD_ERR_CRC 0x0
796 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
797 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
798 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
799 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
800 #define MVPP2_RXD_HWF_SYNC BIT(21)
801 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
802 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
803 #define MVPP2_RXD_L4_TCP BIT(25)
804 #define MVPP2_RXD_L4_UDP BIT(26)
805 #define MVPP2_RXD_L3_IP4 BIT(28)
806 #define MVPP2_RXD_L3_IP6 BIT(30)
807 #define MVPP2_RXD_BUF_HDR BIT(31)
809 /* HW TX descriptor for PPv2.1 */
810 struct mvpp21_tx_desc {
811 u32 command; /* Options used by HW for packet transmitting.*/
812 u8 packet_offset; /* the offset from the buffer beginning */
813 u8 phys_txq; /* destination queue ID */
814 u16 data_size; /* data size of transmitted packet in bytes */
815 u32 buf_dma_addr; /* physical addr of transmitted buffer */
816 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
817 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
818 u32 reserved2; /* reserved (for future use) */
821 /* HW RX descriptor for PPv2.1 */
822 struct mvpp21_rx_desc {
823 u32 status; /* info about received packet */
824 u16 reserved1; /* parser_info (for future use, PnC) */
825 u16 data_size; /* size of received packet in bytes */
826 u32 buf_dma_addr; /* physical address of the buffer */
827 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
828 u16 reserved2; /* gem_port_id (for future use, PON) */
829 u16 reserved3; /* csum_l4 (for future use, PnC) */
830 u8 reserved4; /* bm_qset (for future use, BM) */
832 u16 reserved6; /* classify_info (for future use, PnC) */
833 u32 reserved7; /* flow_id (for future use, PnC) */
837 /* HW TX descriptor for PPv2.2 */
838 struct mvpp22_tx_desc {
844 u64 buf_dma_addr_ptp;
848 /* HW RX descriptor for PPv2.2 */
849 struct mvpp22_rx_desc {
855 u64 buf_dma_addr_key_hash;
859 /* Opaque type used by the driver to manipulate the HW TX and RX
862 struct mvpp2_tx_desc {
864 struct mvpp21_tx_desc pp21;
865 struct mvpp22_tx_desc pp22;
869 struct mvpp2_rx_desc {
871 struct mvpp21_rx_desc pp21;
872 struct mvpp22_rx_desc pp22;
876 /* Per-CPU Tx queue control */
877 struct mvpp2_txq_pcpu {
880 /* Number of Tx DMA descriptors in the descriptor ring */
883 /* Number of currently used Tx DMA descriptor in the
888 /* Number of Tx DMA descriptors reserved for each CPU */
891 /* Index of last TX DMA descriptor that was inserted */
894 /* Index of the TX DMA descriptor to be cleaned up */
898 struct mvpp2_tx_queue {
899 /* Physical number of this Tx queue */
902 /* Logical number of this Tx queue */
905 /* Number of Tx DMA descriptors in the descriptor ring */
908 /* Number of currently used Tx DMA descriptor in the descriptor ring */
911 /* Per-CPU control of physical Tx queues */
912 struct mvpp2_txq_pcpu __percpu *pcpu;
916 /* Virtual address of thex Tx DMA descriptors array */
917 struct mvpp2_tx_desc *descs;
919 /* DMA address of the Tx DMA descriptors array */
920 dma_addr_t descs_dma;
922 /* Index of the last Tx DMA descriptor */
925 /* Index of the next Tx DMA descriptor to process */
926 int next_desc_to_proc;
929 struct mvpp2_rx_queue {
930 /* RX queue number, in the range 0-31 for physical RXQs */
933 /* Num of rx descriptors in the rx descriptor ring */
939 /* Virtual address of the RX DMA descriptors array */
940 struct mvpp2_rx_desc *descs;
942 /* DMA address of the RX DMA descriptors array */
943 dma_addr_t descs_dma;
945 /* Index of the last RX DMA descriptor */
948 /* Index of the next RX DMA descriptor to process */
949 int next_desc_to_proc;
951 /* ID of port to which physical RXQ is mapped */
954 /* Port's logic RXQ number to which physical RXQ is mapped */
958 union mvpp2_prs_tcam_entry {
959 u32 word[MVPP2_PRS_TCAM_WORDS];
960 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
963 union mvpp2_prs_sram_entry {
964 u32 word[MVPP2_PRS_SRAM_WORDS];
965 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
968 struct mvpp2_prs_entry {
970 union mvpp2_prs_tcam_entry tcam;
971 union mvpp2_prs_sram_entry sram;
974 struct mvpp2_prs_shadow {
981 /* User defined offset */
989 struct mvpp2_cls_flow_entry {
991 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
994 struct mvpp2_cls_lookup_entry {
1000 struct mvpp2_bm_pool {
1001 /* Pool number in the range 0-7 */
1003 enum mvpp2_bm_type type;
1005 /* Buffer Pointers Pool External (BPPE) size */
1007 /* Number of buffers for this pool */
1009 /* Pool buffer size */
1014 /* BPPE virtual base address */
1015 unsigned long *virt_addr;
1016 /* BPPE DMA base address */
1017 dma_addr_t dma_addr;
1019 /* Ports using BM pool */
1022 /* Occupied buffers indicator */
1026 /* Static declaractions */
1028 /* Number of RXQs used by single port */
1029 static int rxq_number = MVPP2_DEFAULT_RXQ;
1030 /* Number of TXQs used by single port */
1031 static int txq_number = MVPP2_DEFAULT_TXQ;
1033 #define MVPP2_DRIVER_NAME "mvpp2"
1034 #define MVPP2_DRIVER_VERSION "1.0"
1037 * U-Boot internal data, mostly uncached buffers for descriptors and data
1039 struct buffer_location {
1040 struct mvpp2_tx_desc *aggr_tx_descs;
1041 struct mvpp2_tx_desc *tx_descs;
1042 struct mvpp2_rx_desc *rx_descs;
1043 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1044 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
1049 * All 4 interfaces use the same global buffer, since only one interface
1050 * can be enabled at once
1052 static struct buffer_location buffer_loc;
1055 * Page table entries are set to 1MB, or multiples of 1MB
1056 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1058 #define BD_SPACE (1 << 20)
1060 /* Utility/helper methods */
1062 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1064 writel(data, priv->base + offset);
1067 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1069 return readl(priv->base + offset);
1072 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1073 struct mvpp2_tx_desc *tx_desc,
1074 dma_addr_t dma_addr)
1076 if (port->priv->hw_version == MVPP21) {
1077 tx_desc->pp21.buf_dma_addr = dma_addr;
1079 u64 val = (u64)dma_addr;
1081 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1082 tx_desc->pp22.buf_dma_addr_ptp |= val;
1086 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1087 struct mvpp2_tx_desc *tx_desc,
1090 if (port->priv->hw_version == MVPP21)
1091 tx_desc->pp21.data_size = size;
1093 tx_desc->pp22.data_size = size;
1096 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1097 struct mvpp2_tx_desc *tx_desc,
1100 if (port->priv->hw_version == MVPP21)
1101 tx_desc->pp21.phys_txq = txq;
1103 tx_desc->pp22.phys_txq = txq;
1106 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1107 struct mvpp2_tx_desc *tx_desc,
1108 unsigned int command)
1110 if (port->priv->hw_version == MVPP21)
1111 tx_desc->pp21.command = command;
1113 tx_desc->pp22.command = command;
1116 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1117 struct mvpp2_tx_desc *tx_desc,
1118 unsigned int offset)
1120 if (port->priv->hw_version == MVPP21)
1121 tx_desc->pp21.packet_offset = offset;
1123 tx_desc->pp22.packet_offset = offset;
1126 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1127 struct mvpp2_rx_desc *rx_desc)
1129 if (port->priv->hw_version == MVPP21)
1130 return rx_desc->pp21.buf_dma_addr;
1132 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
1135 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1136 struct mvpp2_rx_desc *rx_desc)
1138 if (port->priv->hw_version == MVPP21)
1139 return rx_desc->pp21.buf_cookie;
1141 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
1144 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1145 struct mvpp2_rx_desc *rx_desc)
1147 if (port->priv->hw_version == MVPP21)
1148 return rx_desc->pp21.data_size;
1150 return rx_desc->pp22.data_size;
1153 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1154 struct mvpp2_rx_desc *rx_desc)
1156 if (port->priv->hw_version == MVPP21)
1157 return rx_desc->pp21.status;
1159 return rx_desc->pp22.status;
1162 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1164 txq_pcpu->txq_get_index++;
1165 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1166 txq_pcpu->txq_get_index = 0;
1169 /* Get number of physical egress port */
1170 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1172 return MVPP2_MAX_TCONT + port->id;
1175 /* Get number of physical TXQ */
1176 static inline int mvpp2_txq_phys(int port, int txq)
1178 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1181 /* Parser configuration routines */
1183 /* Update parser tcam and sram hw entries */
1184 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1188 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1191 /* Clear entry invalidation bit */
1192 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1194 /* Write tcam index - indirect access */
1195 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1196 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1197 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1199 /* Write sram index - indirect access */
1200 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1201 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1202 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1207 /* Read tcam entry from hw */
1208 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1212 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1215 /* Write tcam index - indirect access */
1216 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1218 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1219 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1220 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1221 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1223 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1224 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1226 /* Write sram index - indirect access */
1227 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1228 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1229 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1234 /* Invalidate tcam hw entry */
1235 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1237 /* Write index - indirect access */
1238 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1239 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1240 MVPP2_PRS_TCAM_INV_MASK);
1243 /* Enable shadow table entry and set its lookup ID */
1244 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1246 priv->prs_shadow[index].valid = true;
1247 priv->prs_shadow[index].lu = lu;
1250 /* Update ri fields in shadow table entry */
1251 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1252 unsigned int ri, unsigned int ri_mask)
1254 priv->prs_shadow[index].ri_mask = ri_mask;
1255 priv->prs_shadow[index].ri = ri;
1258 /* Update lookup field in tcam sw entry */
1259 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1261 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1263 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1264 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1267 /* Update mask for single port in tcam sw entry */
1268 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1269 unsigned int port, bool add)
1271 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1274 pe->tcam.byte[enable_off] &= ~(1 << port);
1276 pe->tcam.byte[enable_off] |= 1 << port;
1279 /* Update port map in tcam sw entry */
1280 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1283 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1284 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1286 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1287 pe->tcam.byte[enable_off] &= ~port_mask;
1288 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1291 /* Obtain port map from tcam sw entry */
1292 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1294 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1296 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1299 /* Set byte of data and its enable bits in tcam sw entry */
1300 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1301 unsigned int offs, unsigned char byte,
1302 unsigned char enable)
1304 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1305 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1308 /* Get byte of data and its enable bits from tcam sw entry */
1309 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1310 unsigned int offs, unsigned char *byte,
1311 unsigned char *enable)
1313 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1314 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1317 /* Set ethertype in tcam sw entry */
1318 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1319 unsigned short ethertype)
1321 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1322 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1325 /* Set bits in sram sw entry */
1326 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1329 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1332 /* Clear bits in sram sw entry */
1333 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1336 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1339 /* Update ri bits in sram sw entry */
1340 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1341 unsigned int bits, unsigned int mask)
1345 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1346 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1348 if (!(mask & BIT(i)))
1352 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1354 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1356 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1360 /* Update ai bits in sram sw entry */
1361 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1362 unsigned int bits, unsigned int mask)
1365 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1367 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1369 if (!(mask & BIT(i)))
1373 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1375 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1377 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1381 /* Read ai bits from sram sw entry */
1382 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1385 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1386 int ai_en_off = ai_off + 1;
1387 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1389 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1390 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1395 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1398 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1401 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1403 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1404 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1405 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1408 /* In the sram sw entry set sign and value of the next lookup offset
1409 * and the offset value generated to the classifier
1411 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1416 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1419 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1423 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1424 (unsigned char)shift;
1426 /* Reset and set operation */
1427 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1428 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1429 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1431 /* Set base offset as current */
1432 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1435 /* In the sram sw entry set sign and value of the user defined offset
1436 * generated to the classifier
1438 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1439 unsigned int type, int offset,
1444 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1445 offset = 0 - offset;
1447 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1451 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1452 MVPP2_PRS_SRAM_UDF_MASK);
1453 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1454 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1455 MVPP2_PRS_SRAM_UDF_BITS)] &=
1456 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1457 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1458 MVPP2_PRS_SRAM_UDF_BITS)] |=
1459 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1461 /* Set offset type */
1462 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1463 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1464 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1466 /* Set offset operation */
1467 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1468 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1469 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1471 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1472 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1473 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1474 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1476 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1477 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1478 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1480 /* Set base offset as current */
1481 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1484 /* Find parser flow entry */
1485 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1487 struct mvpp2_prs_entry *pe;
1490 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1493 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1495 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1496 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1499 if (!priv->prs_shadow[tid].valid ||
1500 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1504 mvpp2_prs_hw_read(priv, pe);
1505 bits = mvpp2_prs_sram_ai_get(pe);
1507 /* Sram store classification lookup ID in AI bits [5:0] */
1508 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1516 /* Return first free tcam index, seeking from start to end */
1517 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1525 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1526 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1528 for (tid = start; tid <= end; tid++) {
1529 if (!priv->prs_shadow[tid].valid)
1536 /* Enable/disable dropping all mac da's */
1537 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1539 struct mvpp2_prs_entry pe;
1541 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1542 /* Entry exist - update port only */
1543 pe.index = MVPP2_PE_DROP_ALL;
1544 mvpp2_prs_hw_read(priv, &pe);
1546 /* Entry doesn't exist - create new */
1547 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1548 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1549 pe.index = MVPP2_PE_DROP_ALL;
1551 /* Non-promiscuous mode for all ports - DROP unknown packets */
1552 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1553 MVPP2_PRS_RI_DROP_MASK);
1555 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1556 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1558 /* Update shadow table */
1559 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1561 /* Mask all ports */
1562 mvpp2_prs_tcam_port_map_set(&pe, 0);
1565 /* Update port mask */
1566 mvpp2_prs_tcam_port_set(&pe, port, add);
1568 mvpp2_prs_hw_write(priv, &pe);
1571 /* Set port to promiscuous mode */
1572 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1574 struct mvpp2_prs_entry pe;
1576 /* Promiscuous mode - Accept unknown packets */
1578 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1579 /* Entry exist - update port only */
1580 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1581 mvpp2_prs_hw_read(priv, &pe);
1583 /* Entry doesn't exist - create new */
1584 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1585 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1586 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1588 /* Continue - set next lookup */
1589 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1591 /* Set result info bits */
1592 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1593 MVPP2_PRS_RI_L2_CAST_MASK);
1595 /* Shift to ethertype */
1596 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1597 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1599 /* Mask all ports */
1600 mvpp2_prs_tcam_port_map_set(&pe, 0);
1602 /* Update shadow table */
1603 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1606 /* Update port mask */
1607 mvpp2_prs_tcam_port_set(&pe, port, add);
1609 mvpp2_prs_hw_write(priv, &pe);
1612 /* Accept multicast */
1613 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1616 struct mvpp2_prs_entry pe;
1617 unsigned char da_mc;
1619 /* Ethernet multicast address first byte is
1620 * 0x01 for IPv4 and 0x33 for IPv6
1622 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1624 if (priv->prs_shadow[index].valid) {
1625 /* Entry exist - update port only */
1627 mvpp2_prs_hw_read(priv, &pe);
1629 /* Entry doesn't exist - create new */
1630 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1631 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1634 /* Continue - set next lookup */
1635 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1637 /* Set result info bits */
1638 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1639 MVPP2_PRS_RI_L2_CAST_MASK);
1641 /* Update tcam entry data first byte */
1642 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1644 /* Shift to ethertype */
1645 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1646 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1648 /* Mask all ports */
1649 mvpp2_prs_tcam_port_map_set(&pe, 0);
1651 /* Update shadow table */
1652 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1655 /* Update port mask */
1656 mvpp2_prs_tcam_port_set(&pe, port, add);
1658 mvpp2_prs_hw_write(priv, &pe);
1661 /* Parser per-port initialization */
1662 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1663 int lu_max, int offset)
1668 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1669 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1670 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1671 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1673 /* Set maximum number of loops for packet received from port */
1674 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1675 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1676 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1677 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1679 /* Set initial offset for packet header extraction for the first
1682 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1683 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1684 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1685 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1688 /* Default flow entries initialization for all ports */
1689 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1691 struct mvpp2_prs_entry pe;
1694 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1695 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1696 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1697 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1699 /* Mask all ports */
1700 mvpp2_prs_tcam_port_map_set(&pe, 0);
1703 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1704 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1706 /* Update shadow table and hw entry */
1707 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1708 mvpp2_prs_hw_write(priv, &pe);
1712 /* Set default entry for Marvell Header field */
1713 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1715 struct mvpp2_prs_entry pe;
1717 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1719 pe.index = MVPP2_PE_MH_DEFAULT;
1720 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1721 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1722 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1723 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1725 /* Unmask all ports */
1726 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1728 /* Update shadow table and hw entry */
1729 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1730 mvpp2_prs_hw_write(priv, &pe);
1733 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1734 * multicast MAC addresses
1736 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1738 struct mvpp2_prs_entry pe;
1740 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1742 /* Non-promiscuous mode for all ports - DROP unknown packets */
1743 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1744 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1746 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1747 MVPP2_PRS_RI_DROP_MASK);
1748 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1749 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1751 /* Unmask all ports */
1752 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1754 /* Update shadow table and hw entry */
1755 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1756 mvpp2_prs_hw_write(priv, &pe);
1758 /* place holders only - no ports */
1759 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1760 mvpp2_prs_mac_promisc_set(priv, 0, false);
1761 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1762 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1765 /* Match basic ethertypes */
1766 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1768 struct mvpp2_prs_entry pe;
1771 /* Ethertype: PPPoE */
1772 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1773 MVPP2_PE_LAST_FREE_TID);
1777 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1778 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1781 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
1783 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1784 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1785 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1786 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1787 MVPP2_PRS_RI_PPPOE_MASK);
1789 /* Update shadow table and hw entry */
1790 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1791 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1792 priv->prs_shadow[pe.index].finish = false;
1793 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
1794 MVPP2_PRS_RI_PPPOE_MASK);
1795 mvpp2_prs_hw_write(priv, &pe);
1797 /* Ethertype: ARP */
1798 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1799 MVPP2_PE_LAST_FREE_TID);
1803 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1804 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1807 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
1809 /* Generate flow in the next iteration*/
1810 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1811 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1812 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
1813 MVPP2_PRS_RI_L3_PROTO_MASK);
1815 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1817 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1819 /* Update shadow table and hw entry */
1820 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1821 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1822 priv->prs_shadow[pe.index].finish = true;
1823 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
1824 MVPP2_PRS_RI_L3_PROTO_MASK);
1825 mvpp2_prs_hw_write(priv, &pe);
1827 /* Ethertype: LBTD */
1828 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1829 MVPP2_PE_LAST_FREE_TID);
1833 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1834 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1837 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
1839 /* Generate flow in the next iteration*/
1840 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1841 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1842 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1843 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1844 MVPP2_PRS_RI_CPU_CODE_MASK |
1845 MVPP2_PRS_RI_UDF3_MASK);
1847 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1849 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1851 /* Update shadow table and hw entry */
1852 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1853 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1854 priv->prs_shadow[pe.index].finish = true;
1855 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1856 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1857 MVPP2_PRS_RI_CPU_CODE_MASK |
1858 MVPP2_PRS_RI_UDF3_MASK);
1859 mvpp2_prs_hw_write(priv, &pe);
1861 /* Ethertype: IPv4 without options */
1862 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1863 MVPP2_PE_LAST_FREE_TID);
1867 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1868 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1871 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
1872 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1873 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
1874 MVPP2_PRS_IPV4_HEAD_MASK |
1875 MVPP2_PRS_IPV4_IHL_MASK);
1877 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1878 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
1879 MVPP2_PRS_RI_L3_PROTO_MASK);
1880 /* Skip eth_type + 4 bytes of IP header */
1881 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
1882 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1884 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1886 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1888 /* Update shadow table and hw entry */
1889 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1890 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1891 priv->prs_shadow[pe.index].finish = false;
1892 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
1893 MVPP2_PRS_RI_L3_PROTO_MASK);
1894 mvpp2_prs_hw_write(priv, &pe);
1896 /* Ethertype: IPv4 with options */
1897 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1898 MVPP2_PE_LAST_FREE_TID);
1904 /* Clear tcam data before updating */
1905 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
1906 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
1908 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1909 MVPP2_PRS_IPV4_HEAD,
1910 MVPP2_PRS_IPV4_HEAD_MASK);
1912 /* Clear ri before updating */
1913 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
1914 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
1915 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
1916 MVPP2_PRS_RI_L3_PROTO_MASK);
1918 /* Update shadow table and hw entry */
1919 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1920 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1921 priv->prs_shadow[pe.index].finish = false;
1922 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
1923 MVPP2_PRS_RI_L3_PROTO_MASK);
1924 mvpp2_prs_hw_write(priv, &pe);
1926 /* Ethertype: IPv6 without options */
1927 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1928 MVPP2_PE_LAST_FREE_TID);
1932 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1933 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1936 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
1938 /* Skip DIP of IPV6 header */
1939 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
1940 MVPP2_MAX_L3_ADDR_SIZE,
1941 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1942 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
1943 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
1944 MVPP2_PRS_RI_L3_PROTO_MASK);
1946 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1948 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1950 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1951 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1952 priv->prs_shadow[pe.index].finish = false;
1953 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
1954 MVPP2_PRS_RI_L3_PROTO_MASK);
1955 mvpp2_prs_hw_write(priv, &pe);
1957 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
1958 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1959 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1960 pe.index = MVPP2_PE_ETH_TYPE_UN;
1962 /* Unmask all ports */
1963 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1965 /* Generate flow in the next iteration*/
1966 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1967 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1968 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
1969 MVPP2_PRS_RI_L3_PROTO_MASK);
1970 /* Set L3 offset even it's unknown L3 */
1971 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1973 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1975 /* Update shadow table and hw entry */
1976 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1977 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1978 priv->prs_shadow[pe.index].finish = true;
1979 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
1980 MVPP2_PRS_RI_L3_PROTO_MASK);
1981 mvpp2_prs_hw_write(priv, &pe);
1986 /* Parser default initialization */
1987 static int mvpp2_prs_default_init(struct udevice *dev,
1992 /* Enable tcam table */
1993 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
1995 /* Clear all tcam and sram entries */
1996 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
1997 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1998 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1999 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2001 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2002 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2003 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2006 /* Invalidate all tcam entries */
2007 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2008 mvpp2_prs_hw_inv(priv, index);
2010 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2011 sizeof(struct mvpp2_prs_shadow),
2013 if (!priv->prs_shadow)
2016 /* Always start from lookup = 0 */
2017 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2018 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2019 MVPP2_PRS_PORT_LU_MAX, 0);
2021 mvpp2_prs_def_flow_init(priv);
2023 mvpp2_prs_mh_init(priv);
2025 mvpp2_prs_mac_init(priv);
2027 err = mvpp2_prs_etype_init(priv);
2034 /* Compare MAC DA with tcam entry data */
2035 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2036 const u8 *da, unsigned char *mask)
2038 unsigned char tcam_byte, tcam_mask;
2041 for (index = 0; index < ETH_ALEN; index++) {
2042 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2043 if (tcam_mask != mask[index])
2046 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2053 /* Find tcam entry with matched pair <MAC DA, port> */
2054 static struct mvpp2_prs_entry *
2055 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2056 unsigned char *mask, int udf_type)
2058 struct mvpp2_prs_entry *pe;
2061 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2064 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2066 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2067 for (tid = MVPP2_PE_FIRST_FREE_TID;
2068 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2069 unsigned int entry_pmap;
2071 if (!priv->prs_shadow[tid].valid ||
2072 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2073 (priv->prs_shadow[tid].udf != udf_type))
2077 mvpp2_prs_hw_read(priv, pe);
2078 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2080 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2089 /* Update parser's mac da entry */
2090 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2091 const u8 *da, bool add)
2093 struct mvpp2_prs_entry *pe;
2094 unsigned int pmap, len, ri;
2095 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2098 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2099 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2100 MVPP2_PRS_UDF_MAC_DEF);
2107 /* Create new TCAM entry */
2108 /* Find first range mac entry*/
2109 for (tid = MVPP2_PE_FIRST_FREE_TID;
2110 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2111 if (priv->prs_shadow[tid].valid &&
2112 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2113 (priv->prs_shadow[tid].udf ==
2114 MVPP2_PRS_UDF_MAC_RANGE))
2117 /* Go through the all entries from first to last */
2118 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2123 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2126 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2129 /* Mask all ports */
2130 mvpp2_prs_tcam_port_map_set(pe, 0);
2133 /* Update port mask */
2134 mvpp2_prs_tcam_port_set(pe, port, add);
2136 /* Invalidate the entry if no ports are left enabled */
2137 pmap = mvpp2_prs_tcam_port_map_get(pe);
2143 mvpp2_prs_hw_inv(priv, pe->index);
2144 priv->prs_shadow[pe->index].valid = false;
2149 /* Continue - set next lookup */
2150 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2152 /* Set match on DA */
2155 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2157 /* Set result info bits */
2158 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2160 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2161 MVPP2_PRS_RI_MAC_ME_MASK);
2162 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2163 MVPP2_PRS_RI_MAC_ME_MASK);
2165 /* Shift to ethertype */
2166 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2167 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2169 /* Update shadow table and hw entry */
2170 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2171 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2172 mvpp2_prs_hw_write(priv, pe);
2179 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2183 /* Remove old parser entry */
2184 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2189 /* Add new parser entry */
2190 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2194 /* Set addr in the device */
2195 memcpy(port->dev_addr, da, ETH_ALEN);
2200 /* Set prs flow for the port */
2201 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2203 struct mvpp2_prs_entry *pe;
2206 pe = mvpp2_prs_flow_find(port->priv, port->id);
2208 /* Such entry not exist */
2210 /* Go through the all entires from last to first */
2211 tid = mvpp2_prs_tcam_first_free(port->priv,
2212 MVPP2_PE_LAST_FREE_TID,
2213 MVPP2_PE_FIRST_FREE_TID);
2217 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2221 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2225 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2226 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2228 /* Update shadow table */
2229 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2232 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2233 mvpp2_prs_hw_write(port->priv, pe);
2239 /* Classifier configuration routines */
2241 /* Update classification flow table registers */
2242 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2243 struct mvpp2_cls_flow_entry *fe)
2245 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2246 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2247 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2248 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2251 /* Update classification lookup table register */
2252 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2253 struct mvpp2_cls_lookup_entry *le)
2257 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2258 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2259 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2262 /* Classifier default initialization */
2263 static void mvpp2_cls_init(struct mvpp2 *priv)
2265 struct mvpp2_cls_lookup_entry le;
2266 struct mvpp2_cls_flow_entry fe;
2269 /* Enable classifier */
2270 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2272 /* Clear classifier flow table */
2273 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2274 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2276 mvpp2_cls_flow_write(priv, &fe);
2279 /* Clear classifier lookup table */
2281 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2284 mvpp2_cls_lookup_write(priv, &le);
2287 mvpp2_cls_lookup_write(priv, &le);
2291 static void mvpp2_cls_port_config(struct mvpp2_port *port)
2293 struct mvpp2_cls_lookup_entry le;
2296 /* Set way for the port */
2297 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2298 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2299 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2301 /* Pick the entry to be accessed in lookup ID decoding table
2302 * according to the way and lkpid.
2304 le.lkpid = port->id;
2308 /* Set initial CPU queue for receiving packets */
2309 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2310 le.data |= port->first_rxq;
2312 /* Disable classification engines */
2313 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2315 /* Update lookup ID table entry */
2316 mvpp2_cls_lookup_write(port->priv, &le);
2319 /* Set CPU queue number for oversize packets */
2320 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2324 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2325 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2327 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2328 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2330 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2331 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2332 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2335 /* Buffer Manager configuration routines */
2338 static int mvpp2_bm_pool_create(struct udevice *dev,
2340 struct mvpp2_bm_pool *bm_pool, int size)
2344 /* Number of buffer pointers must be a multiple of 16, as per
2345 * hardware constraints
2347 if (!IS_ALIGNED(size, 16))
2350 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
2351 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
2352 if (!bm_pool->virt_addr)
2355 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2356 MVPP2_BM_POOL_PTR_ALIGN)) {
2357 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2358 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2362 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
2363 lower_32_bits(bm_pool->dma_addr));
2364 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2366 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2367 val |= MVPP2_BM_START_MASK;
2368 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2370 bm_pool->type = MVPP2_BM_FREE;
2371 bm_pool->size = size;
2372 bm_pool->pkt_size = 0;
2373 bm_pool->buf_num = 0;
2378 /* Set pool buffer size */
2379 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2380 struct mvpp2_bm_pool *bm_pool,
2385 bm_pool->buf_size = buf_size;
2387 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2388 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2391 /* Free all buffers from the pool */
2392 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2393 struct mvpp2_bm_pool *bm_pool)
2395 bm_pool->buf_num = 0;
2399 static int mvpp2_bm_pool_destroy(struct udevice *dev,
2401 struct mvpp2_bm_pool *bm_pool)
2405 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2406 if (bm_pool->buf_num) {
2407 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2411 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2412 val |= MVPP2_BM_STOP_MASK;
2413 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2418 static int mvpp2_bm_pools_init(struct udevice *dev,
2422 struct mvpp2_bm_pool *bm_pool;
2424 /* Create all pools with maximum size */
2425 size = MVPP2_BM_POOL_SIZE_MAX;
2426 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2427 bm_pool = &priv->bm_pools[i];
2429 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2431 goto err_unroll_pools;
2432 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
2437 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2438 for (i = i - 1; i >= 0; i--)
2439 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2443 static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2447 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2448 /* Mask BM all interrupts */
2449 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2450 /* Clear BM cause register */
2451 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2454 /* Allocate and initialize BM pools */
2455 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2456 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2457 if (!priv->bm_pools)
2460 err = mvpp2_bm_pools_init(dev, priv);
2466 /* Attach long pool to rxq */
2467 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2468 int lrxq, int long_pool)
2473 /* Get queue physical ID */
2474 prxq = port->rxqs[lrxq]->id;
2476 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2477 val &= ~MVPP2_RXQ_POOL_LONG_MASK;
2478 val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) &
2479 MVPP2_RXQ_POOL_LONG_MASK);
2481 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2484 /* Set pool number in a BM cookie */
2485 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2489 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2490 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2495 /* Get pool number from a BM cookie */
2496 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
2498 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2501 /* Release buffer to BM */
2502 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
2503 dma_addr_t buf_dma_addr,
2504 unsigned long buf_phys_addr)
2506 if (port->priv->hw_version == MVPP22) {
2509 if (sizeof(dma_addr_t) == 8)
2510 val |= upper_32_bits(buf_dma_addr) &
2511 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2513 if (sizeof(phys_addr_t) == 8)
2514 val |= (upper_32_bits(buf_phys_addr)
2515 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2516 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2518 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2521 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2522 * returned in the "cookie" field of the RX
2523 * descriptor. Instead of storing the virtual address, we
2524 * store the physical address
2526 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
2527 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
2530 /* Refill BM pool */
2531 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
2532 dma_addr_t dma_addr,
2533 phys_addr_t phys_addr)
2535 int pool = mvpp2_bm_cookie_pool_get(bm);
2537 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2540 /* Allocate buffers for the pool */
2541 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2542 struct mvpp2_bm_pool *bm_pool, int buf_num)
2547 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2548 netdev_err(port->dev,
2549 "cannot allocate %d buffers for pool %d\n",
2550 buf_num, bm_pool->id);
2554 for (i = 0; i < buf_num; i++) {
2555 mvpp2_bm_pool_put(port, bm_pool->id,
2556 (dma_addr_t)buffer_loc.rx_buffer[i],
2557 (unsigned long)buffer_loc.rx_buffer[i]);
2561 /* Update BM driver with number of buffers added to pool */
2562 bm_pool->buf_num += i;
2563 bm_pool->in_use_thresh = bm_pool->buf_num / 4;
2568 /* Notify the driver that BM pool is being used as specific type and return the
2569 * pool pointer on success
2571 static struct mvpp2_bm_pool *
2572 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2575 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2578 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2579 netdev_err(port->dev, "mixing pool types is forbidden\n");
2583 if (new_pool->type == MVPP2_BM_FREE)
2584 new_pool->type = type;
2586 /* Allocate buffers in case BM pool is used as long pool, but packet
2587 * size doesn't match MTU or BM pool hasn't being used yet
2589 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2590 (new_pool->pkt_size == 0)) {
2593 /* Set default buffer number or free all the buffers in case
2594 * the pool is not empty
2596 pkts_num = new_pool->buf_num;
2598 pkts_num = type == MVPP2_BM_SWF_LONG ?
2599 MVPP2_BM_LONG_BUF_NUM :
2600 MVPP2_BM_SHORT_BUF_NUM;
2602 mvpp2_bm_bufs_free(NULL,
2603 port->priv, new_pool);
2605 new_pool->pkt_size = pkt_size;
2607 /* Allocate buffers for this pool */
2608 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2609 if (num != pkts_num) {
2610 dev_err(dev, "pool %d: %d of %d allocated\n",
2611 new_pool->id, num, pkts_num);
2616 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
2617 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
2622 /* Initialize pools for swf */
2623 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2627 if (!port->pool_long) {
2629 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2632 if (!port->pool_long)
2635 port->pool_long->port_map |= (1 << port->id);
2637 for (rxq = 0; rxq < rxq_number; rxq++)
2638 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2644 /* Port configuration routines */
2646 static void mvpp2_port_mii_set(struct mvpp2_port *port)
2650 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2652 switch (port->phy_interface) {
2653 case PHY_INTERFACE_MODE_SGMII:
2654 val |= MVPP2_GMAC_INBAND_AN_MASK;
2656 case PHY_INTERFACE_MODE_RGMII:
2657 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2659 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2662 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2665 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2669 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2670 val |= MVPP2_GMAC_FC_ADV_EN;
2671 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2674 static void mvpp2_port_enable(struct mvpp2_port *port)
2678 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2679 val |= MVPP2_GMAC_PORT_EN_MASK;
2680 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2681 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2684 static void mvpp2_port_disable(struct mvpp2_port *port)
2688 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2689 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2690 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2693 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2694 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2698 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2699 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2700 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2703 /* Configure loopback port */
2704 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2708 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2710 if (port->speed == 1000)
2711 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2713 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2715 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2716 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2718 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2720 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2723 static void mvpp2_port_reset(struct mvpp2_port *port)
2727 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2728 ~MVPP2_GMAC_PORT_RESET_MASK;
2729 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2731 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2732 MVPP2_GMAC_PORT_RESET_MASK)
2736 /* Change maximum receive size of the port */
2737 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2741 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2742 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2743 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2744 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2745 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2748 /* Set defaults to the MVPP2 port */
2749 static void mvpp2_defaults_set(struct mvpp2_port *port)
2751 int tx_port_num, val, queue, ptxq, lrxq;
2753 /* Configure port to loopback if needed */
2754 if (port->flags & MVPP2_F_LOOPBACK)
2755 mvpp2_port_loopback_set(port);
2757 /* Update TX FIFO MIN Threshold */
2758 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2759 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
2760 /* Min. TX threshold must be less than minimal packet length */
2761 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2762 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2764 /* Disable Legacy WRR, Disable EJP, Release from reset */
2765 tx_port_num = mvpp2_egress_port(port);
2766 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
2768 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
2770 /* Close bandwidth for all queues */
2771 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
2772 ptxq = mvpp2_txq_phys(port->id, queue);
2773 mvpp2_write(port->priv,
2774 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
2777 /* Set refill period to 1 usec, refill tokens
2778 * and bucket size to maximum
2780 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
2781 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
2782 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
2783 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2784 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
2785 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
2786 val = MVPP2_TXP_TOKEN_SIZE_MAX;
2787 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2789 /* Set MaximumLowLatencyPacketSize value to 256 */
2790 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
2791 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
2792 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2794 /* Enable Rx cache snoop */
2795 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2796 queue = port->rxqs[lrxq]->id;
2797 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2798 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
2799 MVPP2_SNOOP_BUF_HDR_MASK;
2800 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2804 /* Enable/disable receiving packets */
2805 static void mvpp2_ingress_enable(struct mvpp2_port *port)
2810 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2811 queue = port->rxqs[lrxq]->id;
2812 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2813 val &= ~MVPP2_RXQ_DISABLE_MASK;
2814 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2818 static void mvpp2_ingress_disable(struct mvpp2_port *port)
2823 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2824 queue = port->rxqs[lrxq]->id;
2825 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2826 val |= MVPP2_RXQ_DISABLE_MASK;
2827 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2831 /* Enable transmit via physical egress queue
2832 * - HW starts take descriptors from DRAM
2834 static void mvpp2_egress_enable(struct mvpp2_port *port)
2838 int tx_port_num = mvpp2_egress_port(port);
2840 /* Enable all initialized TXs. */
2842 for (queue = 0; queue < txq_number; queue++) {
2843 struct mvpp2_tx_queue *txq = port->txqs[queue];
2845 if (txq->descs != NULL)
2846 qmap |= (1 << queue);
2849 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2850 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2853 /* Disable transmit via physical egress queue
2854 * - HW doesn't take descriptors from DRAM
2856 static void mvpp2_egress_disable(struct mvpp2_port *port)
2860 int tx_port_num = mvpp2_egress_port(port);
2862 /* Issue stop command for active channels only */
2863 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2864 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2865 MVPP2_TXP_SCHED_ENQ_MASK;
2867 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2868 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2870 /* Wait for all Tx activity to terminate. */
2873 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2874 netdev_warn(port->dev,
2875 "Tx stop timed out, status=0x%08x\n",
2882 /* Check port TX Command register that all
2883 * Tx queues are stopped
2885 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2886 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2889 /* Rx descriptors helper methods */
2891 /* Get number of Rx descriptors occupied by received packets */
2893 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2895 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2897 return val & MVPP2_RXQ_OCCUPIED_MASK;
2900 /* Update Rx queue status with the number of occupied and available
2901 * Rx descriptor slots.
2904 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2905 int used_count, int free_count)
2907 /* Decrement the number of used descriptors and increment count
2908 * increment the number of free descriptors.
2910 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2912 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2915 /* Get pointer to next RX descriptor to be processed by SW */
2916 static inline struct mvpp2_rx_desc *
2917 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
2919 int rx_desc = rxq->next_desc_to_proc;
2921 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
2922 prefetch(rxq->descs + rxq->next_desc_to_proc);
2923 return rxq->descs + rx_desc;
2926 /* Set rx queue offset */
2927 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
2928 int prxq, int offset)
2932 /* Convert offset from bytes to units of 32 bytes */
2933 offset = offset >> 5;
2935 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2936 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
2939 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
2940 MVPP2_RXQ_PACKET_OFFSET_MASK);
2942 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2945 /* Obtain BM cookie information from descriptor */
2946 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
2947 struct mvpp2_rx_desc *rx_desc)
2949 int cpu = smp_processor_id();
2952 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
2953 MVPP2_RXD_BM_POOL_ID_MASK) >>
2954 MVPP2_RXD_BM_POOL_ID_OFFS;
2956 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
2957 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
2960 /* Tx descriptors helper methods */
2962 /* Get number of Tx descriptors waiting to be transmitted by HW */
2963 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
2964 struct mvpp2_tx_queue *txq)
2968 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
2969 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
2971 return val & MVPP2_TXQ_PENDING_MASK;
2974 /* Get pointer to next Tx descriptor to be processed (send) by HW */
2975 static struct mvpp2_tx_desc *
2976 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
2978 int tx_desc = txq->next_desc_to_proc;
2980 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
2981 return txq->descs + tx_desc;
2984 /* Update HW with number of aggregated Tx descriptors to be sent */
2985 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
2987 /* aggregated access - relevant TXQ number is written in TX desc */
2988 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
2991 /* Get number of sent descriptors and decrement counter.
2992 * The number of sent descriptors is returned.
2995 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
2996 struct mvpp2_tx_queue *txq)
3000 /* Reading status reg resets transmitted descriptor counter */
3001 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
3003 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
3004 MVPP2_TRANSMITTED_COUNT_OFFSET;
3007 static void mvpp2_txq_sent_counter_clear(void *arg)
3009 struct mvpp2_port *port = arg;
3012 for (queue = 0; queue < txq_number; queue++) {
3013 int id = port->txqs[queue]->id;
3015 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
3019 /* Set max sizes for Tx queues */
3020 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
3023 int txq, tx_port_num;
3025 mtu = port->pkt_size * 8;
3026 if (mtu > MVPP2_TXP_MTU_MAX)
3027 mtu = MVPP2_TXP_MTU_MAX;
3029 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3032 /* Indirect access to registers */
3033 tx_port_num = mvpp2_egress_port(port);
3034 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3037 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
3038 val &= ~MVPP2_TXP_MTU_MAX;
3040 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
3042 /* TXP token size and all TXQs token size must be larger that MTU */
3043 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
3044 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
3047 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
3049 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3052 for (txq = 0; txq < txq_number; txq++) {
3053 val = mvpp2_read(port->priv,
3054 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
3055 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
3059 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
3061 mvpp2_write(port->priv,
3062 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
3068 /* Free Tx queue skbuffs */
3069 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
3070 struct mvpp2_tx_queue *txq,
3071 struct mvpp2_txq_pcpu *txq_pcpu, int num)
3075 for (i = 0; i < num; i++)
3076 mvpp2_txq_inc_get(txq_pcpu);
3079 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
3082 int queue = fls(cause) - 1;
3084 return port->rxqs[queue];
3087 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
3090 int queue = fls(cause) - 1;
3092 return port->txqs[queue];
3095 /* Rx/Tx queue initialization/cleanup methods */
3097 /* Allocate and initialize descriptors for aggr TXQ */
3098 static int mvpp2_aggr_txq_init(struct udevice *dev,
3099 struct mvpp2_tx_queue *aggr_txq,
3100 int desc_num, int cpu,
3103 /* Allocate memory for TX descriptors */
3104 aggr_txq->descs = buffer_loc.aggr_tx_descs;
3105 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
3106 if (!aggr_txq->descs)
3109 /* Make sure descriptor address is cache line size aligned */
3110 BUG_ON(aggr_txq->descs !=
3111 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3113 aggr_txq->last_desc = aggr_txq->size - 1;
3115 /* Aggr TXQ no reset WA */
3116 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
3117 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
3119 /* Set Tx descriptors queue starting address */
3120 /* indirect access */
3121 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu),
3122 aggr_txq->descs_dma);
3123 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
3128 /* Create a specified Rx queue */
3129 static int mvpp2_rxq_init(struct mvpp2_port *port,
3130 struct mvpp2_rx_queue *rxq)
3133 rxq->size = port->rx_ring_size;
3135 /* Allocate memory for RX descriptors */
3136 rxq->descs = buffer_loc.rx_descs;
3137 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
3141 BUG_ON(rxq->descs !=
3142 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3144 rxq->last_desc = rxq->size - 1;
3146 /* Zero occupied and non-occupied counters - direct access */
3147 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3149 /* Set Rx descriptors queue starting address - indirect access */
3150 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
3151 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_dma);
3152 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
3153 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
3156 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
3158 /* Add number of descriptors ready for receiving packets */
3159 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
3164 /* Push packets received by the RXQ to BM pool */
3165 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
3166 struct mvpp2_rx_queue *rxq)
3170 rx_received = mvpp2_rxq_received(port, rxq->id);
3174 for (i = 0; i < rx_received; i++) {
3175 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3176 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
3178 mvpp2_pool_refill(port, bm,
3179 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
3180 mvpp2_rxdesc_cookie_get(port, rx_desc));
3182 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
3185 /* Cleanup Rx queue */
3186 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
3187 struct mvpp2_rx_queue *rxq)
3189 mvpp2_rxq_drop_pkts(port, rxq);
3193 rxq->next_desc_to_proc = 0;
3196 /* Clear Rx descriptors queue starting address and size;
3197 * free descriptor number
3199 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3200 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
3201 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
3202 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
3205 /* Create and initialize a Tx queue */
3206 static int mvpp2_txq_init(struct mvpp2_port *port,
3207 struct mvpp2_tx_queue *txq)
3210 int cpu, desc, desc_per_txq, tx_port_num;
3211 struct mvpp2_txq_pcpu *txq_pcpu;
3213 txq->size = port->tx_ring_size;
3215 /* Allocate memory for Tx descriptors */
3216 txq->descs = buffer_loc.tx_descs;
3217 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
3221 /* Make sure descriptor address is cache line size aligned */
3222 BUG_ON(txq->descs !=
3223 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3225 txq->last_desc = txq->size - 1;
3227 /* Set Tx descriptors queue starting address - indirect access */
3228 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3229 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
3230 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
3231 MVPP2_TXQ_DESC_SIZE_MASK);
3232 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
3233 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
3234 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
3235 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3236 val &= ~MVPP2_TXQ_PENDING_MASK;
3237 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
3239 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
3240 * for each existing TXQ.
3241 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3242 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
3245 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
3246 (txq->log_id * desc_per_txq);
3248 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
3249 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
3250 MVPP2_PREF_BUF_THRESH(desc_per_txq/2));
3252 /* WRR / EJP configuration - indirect access */
3253 tx_port_num = mvpp2_egress_port(port);
3254 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3256 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
3257 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
3258 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3259 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
3260 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
3262 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
3263 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
3266 for_each_present_cpu(cpu) {
3267 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3268 txq_pcpu->size = txq->size;
3274 /* Free allocated TXQ resources */
3275 static void mvpp2_txq_deinit(struct mvpp2_port *port,
3276 struct mvpp2_tx_queue *txq)
3280 txq->next_desc_to_proc = 0;
3283 /* Set minimum bandwidth for disabled TXQs */
3284 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
3286 /* Set Tx descriptors queue starting address and size */
3287 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3288 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
3289 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
3292 /* Cleanup Tx ports */
3293 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
3295 struct mvpp2_txq_pcpu *txq_pcpu;
3296 int delay, pending, cpu;
3299 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3300 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
3301 val |= MVPP2_TXQ_DRAIN_EN_MASK;
3302 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3304 /* The napi queue has been stopped so wait for all packets
3305 * to be transmitted.
3309 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
3310 netdev_warn(port->dev,
3311 "port %d: cleaning queue %d timed out\n",
3312 port->id, txq->log_id);
3318 pending = mvpp2_txq_pend_desc_num_get(port, txq);
3321 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
3322 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3324 for_each_present_cpu(cpu) {
3325 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3327 /* Release all packets */
3328 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
3331 txq_pcpu->count = 0;
3332 txq_pcpu->txq_put_index = 0;
3333 txq_pcpu->txq_get_index = 0;
3337 /* Cleanup all Tx queues */
3338 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
3340 struct mvpp2_tx_queue *txq;
3344 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
3346 /* Reset Tx ports and delete Tx queues */
3347 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
3348 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3350 for (queue = 0; queue < txq_number; queue++) {
3351 txq = port->txqs[queue];
3352 mvpp2_txq_clean(port, txq);
3353 mvpp2_txq_deinit(port, txq);
3356 mvpp2_txq_sent_counter_clear(port);
3358 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
3359 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3362 /* Cleanup all Rx queues */
3363 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
3367 for (queue = 0; queue < rxq_number; queue++)
3368 mvpp2_rxq_deinit(port, port->rxqs[queue]);
3371 /* Init all Rx queues for port */
3372 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
3376 for (queue = 0; queue < rxq_number; queue++) {
3377 err = mvpp2_rxq_init(port, port->rxqs[queue]);
3384 mvpp2_cleanup_rxqs(port);
3388 /* Init all tx queues for port */
3389 static int mvpp2_setup_txqs(struct mvpp2_port *port)
3391 struct mvpp2_tx_queue *txq;
3394 for (queue = 0; queue < txq_number; queue++) {
3395 txq = port->txqs[queue];
3396 err = mvpp2_txq_init(port, txq);
3401 mvpp2_txq_sent_counter_clear(port);
3405 mvpp2_cleanup_txqs(port);
3410 static void mvpp2_link_event(struct mvpp2_port *port)
3412 struct phy_device *phydev = port->phy_dev;
3413 int status_change = 0;
3417 if ((port->speed != phydev->speed) ||
3418 (port->duplex != phydev->duplex)) {
3421 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3422 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
3423 MVPP2_GMAC_CONFIG_GMII_SPEED |
3424 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3425 MVPP2_GMAC_AN_SPEED_EN |
3426 MVPP2_GMAC_AN_DUPLEX_EN);
3429 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
3431 if (phydev->speed == SPEED_1000)
3432 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
3433 else if (phydev->speed == SPEED_100)
3434 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
3436 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3438 port->duplex = phydev->duplex;
3439 port->speed = phydev->speed;
3443 if (phydev->link != port->link) {
3444 if (!phydev->link) {
3449 port->link = phydev->link;
3453 if (status_change) {
3455 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3456 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
3457 MVPP2_GMAC_FORCE_LINK_DOWN);
3458 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3459 mvpp2_egress_enable(port);
3460 mvpp2_ingress_enable(port);
3462 mvpp2_ingress_disable(port);
3463 mvpp2_egress_disable(port);
3468 /* Main RX/TX processing routines */
3470 /* Display more error info */
3471 static void mvpp2_rx_error(struct mvpp2_port *port,
3472 struct mvpp2_rx_desc *rx_desc)
3474 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3475 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
3477 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3478 case MVPP2_RXD_ERR_CRC:
3479 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
3482 case MVPP2_RXD_ERR_OVERRUN:
3483 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
3486 case MVPP2_RXD_ERR_RESOURCE:
3487 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
3493 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
3494 static int mvpp2_rx_refill(struct mvpp2_port *port,
3495 struct mvpp2_bm_pool *bm_pool,
3496 u32 bm, dma_addr_t dma_addr)
3498 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
3502 /* Set hw internals when starting port */
3503 static void mvpp2_start_dev(struct mvpp2_port *port)
3505 mvpp2_gmac_max_rx_size_set(port);
3506 mvpp2_txp_max_tx_size_set(port);
3508 mvpp2_port_enable(port);
3511 /* Set hw internals when stopping port */
3512 static void mvpp2_stop_dev(struct mvpp2_port *port)
3514 /* Stop new packets from arriving to RXQs */
3515 mvpp2_ingress_disable(port);
3517 mvpp2_egress_disable(port);
3518 mvpp2_port_disable(port);
3521 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
3523 struct phy_device *phy_dev;
3525 if (!port->init || port->link == 0) {
3526 phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
3527 port->phy_interface);
3528 port->phy_dev = phy_dev;
3530 netdev_err(port->dev, "cannot connect to phy\n");
3533 phy_dev->supported &= PHY_GBIT_FEATURES;
3534 phy_dev->advertising = phy_dev->supported;
3536 port->phy_dev = phy_dev;
3541 phy_config(phy_dev);
3542 phy_startup(phy_dev);
3543 if (!phy_dev->link) {
3544 printf("%s: No link\n", phy_dev->dev->name);
3550 mvpp2_egress_enable(port);
3551 mvpp2_ingress_enable(port);
3557 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
3559 unsigned char mac_bcast[ETH_ALEN] = {
3560 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3563 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
3565 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3568 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
3569 port->dev_addr, true);
3571 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
3574 err = mvpp2_prs_def_flow(port);
3576 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3580 /* Allocate the Rx/Tx queues */
3581 err = mvpp2_setup_rxqs(port);
3583 netdev_err(port->dev, "cannot allocate Rx queues\n");
3587 err = mvpp2_setup_txqs(port);
3589 netdev_err(port->dev, "cannot allocate Tx queues\n");
3593 err = mvpp2_phy_connect(dev, port);
3597 mvpp2_link_event(port);
3599 mvpp2_start_dev(port);
3604 /* No Device ops here in U-Boot */
3606 /* Driver initialization */
3608 static void mvpp2_port_power_up(struct mvpp2_port *port)
3610 mvpp2_port_mii_set(port);
3611 mvpp2_port_periodic_xon_disable(port);
3612 mvpp2_port_fc_adv_enable(port);
3613 mvpp2_port_reset(port);
3616 /* Initialize port HW */
3617 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
3619 struct mvpp2 *priv = port->priv;
3620 struct mvpp2_txq_pcpu *txq_pcpu;
3621 int queue, cpu, err;
3623 if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM)
3627 mvpp2_egress_disable(port);
3628 mvpp2_port_disable(port);
3630 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
3635 /* Associate physical Tx queues to this port and initialize.
3636 * The mapping is predefined.
3638 for (queue = 0; queue < txq_number; queue++) {
3639 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
3640 struct mvpp2_tx_queue *txq;
3642 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
3646 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
3651 txq->id = queue_phy_id;
3652 txq->log_id = queue;
3653 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
3654 for_each_present_cpu(cpu) {
3655 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3656 txq_pcpu->cpu = cpu;
3659 port->txqs[queue] = txq;
3662 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
3667 /* Allocate and initialize Rx queue for this port */
3668 for (queue = 0; queue < rxq_number; queue++) {
3669 struct mvpp2_rx_queue *rxq;
3671 /* Map physical Rx queue to port's logical Rx queue */
3672 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
3675 /* Map this Rx queue to a physical queue */
3676 rxq->id = port->first_rxq + queue;
3677 rxq->port = port->id;
3678 rxq->logic_rxq = queue;
3680 port->rxqs[queue] = rxq;
3683 /* Configure Rx queue group interrupt for this port */
3684 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), CONFIG_MV_ETH_RXQ);
3686 /* Create Rx descriptor rings */
3687 for (queue = 0; queue < rxq_number; queue++) {
3688 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3690 rxq->size = port->rx_ring_size;
3691 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
3692 rxq->time_coal = MVPP2_RX_COAL_USEC;
3695 mvpp2_ingress_disable(port);
3697 /* Port default configuration */
3698 mvpp2_defaults_set(port);
3700 /* Port's classifier configuration */
3701 mvpp2_cls_oversize_rxq_set(port);
3702 mvpp2_cls_port_config(port);
3704 /* Provide an initial Rx packet size */
3705 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
3707 /* Initialize pools for swf */
3708 err = mvpp2_swf_bm_pool_init(port);
3715 /* Ports initialization */
3716 static int mvpp2_port_probe(struct udevice *dev,
3717 struct mvpp2_port *port,
3720 int *next_first_rxq)
3725 const char *phy_mode_str;
3727 int priv_common_regs_num = 2;
3730 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
3732 dev_err(&pdev->dev, "missing phy\n");
3736 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
3738 phy_mode = phy_get_interface_by_name(phy_mode_str);
3739 if (phy_mode == -1) {
3740 dev_err(&pdev->dev, "incorrect phy mode\n");
3744 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
3746 dev_err(&pdev->dev, "missing port-id value\n");
3750 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
3754 port->first_rxq = *next_first_rxq;
3755 port->phy_node = phy_node;
3756 port->phy_interface = phy_mode;
3757 port->phyaddr = phyaddr;
3759 port->base = (void __iomem *)dev_get_addr_index(dev->parent,
3760 priv_common_regs_num
3762 if (IS_ERR(port->base))
3763 return PTR_ERR(port->base);
3765 port->tx_ring_size = MVPP2_MAX_TXD;
3766 port->rx_ring_size = MVPP2_MAX_RXD;
3768 err = mvpp2_port_init(dev, port);
3770 dev_err(&pdev->dev, "failed to init port %d\n", id);
3773 mvpp2_port_power_up(port);
3775 /* Increment the first Rx queue number to be used by the next port */
3776 *next_first_rxq += CONFIG_MV_ETH_RXQ;
3777 priv->port_list[id] = port;
3781 /* Initialize decoding windows */
3782 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
3788 for (i = 0; i < 6; i++) {
3789 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
3790 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
3793 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
3798 for (i = 0; i < dram->num_cs; i++) {
3799 const struct mbus_dram_window *cs = dram->cs + i;
3801 mvpp2_write(priv, MVPP2_WIN_BASE(i),
3802 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
3803 dram->mbus_dram_target_id);
3805 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
3806 (cs->size - 1) & 0xffff0000);
3808 win_enable |= (1 << i);
3811 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
3814 /* Initialize Rx FIFO's */
3815 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
3819 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
3820 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
3821 MVPP2_RX_FIFO_PORT_DATA_SIZE);
3822 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
3823 MVPP2_RX_FIFO_PORT_ATTR_SIZE);
3826 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
3827 MVPP2_RX_FIFO_PORT_MIN_PKT);
3828 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
3831 /* Initialize network controller common part HW */
3832 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
3834 const struct mbus_dram_target_info *dram_target_info;
3838 /* Checks for hardware constraints (U-Boot uses only one rxq) */
3839 if ((rxq_number > MVPP2_MAX_RXQ) || (txq_number > MVPP2_MAX_TXQ)) {
3840 dev_err(&pdev->dev, "invalid queue size parameter\n");
3844 /* MBUS windows configuration */
3845 dram_target_info = mvebu_mbus_dram_info();
3846 if (dram_target_info)
3847 mvpp2_conf_mbus_windows(dram_target_info, priv);
3849 /* Disable HW PHY polling */
3850 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
3851 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
3852 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
3854 /* Allocate and initialize aggregated TXQs */
3855 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
3856 sizeof(struct mvpp2_tx_queue),
3858 if (!priv->aggr_txqs)
3861 for_each_present_cpu(i) {
3862 priv->aggr_txqs[i].id = i;
3863 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
3864 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
3865 MVPP2_AGGR_TXQ_SIZE, i, priv);
3871 mvpp2_rx_fifo_init(priv);
3873 /* Reset Rx queue group interrupt configuration */
3874 for (i = 0; i < MVPP2_MAX_PORTS; i++)
3875 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i),
3878 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
3879 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
3881 /* Allow cache snoop when transmiting packets */
3882 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
3884 /* Buffer Manager initialization */
3885 err = mvpp2_bm_init(dev, priv);
3889 /* Parser default initialization */
3890 err = mvpp2_prs_default_init(dev, priv);
3894 /* Classifier default initialization */
3895 mvpp2_cls_init(priv);
3900 /* SMI / MDIO functions */
3902 static int smi_wait_ready(struct mvpp2 *priv)
3904 u32 timeout = MVPP2_SMI_TIMEOUT;
3907 /* wait till the SMI is not busy */
3909 /* read smi register */
3910 smi_reg = readl(priv->lms_base + MVPP2_SMI);
3911 if (timeout-- == 0) {
3912 printf("Error: SMI busy timeout\n");
3915 } while (smi_reg & MVPP2_SMI_BUSY);
3921 * mpp2_mdio_read - miiphy_read callback function.
3923 * Returns 16bit phy register value, or 0xffff on error
3925 static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
3927 struct mvpp2 *priv = bus->priv;
3931 /* check parameters */
3932 if (addr > MVPP2_PHY_ADDR_MASK) {
3933 printf("Error: Invalid PHY address %d\n", addr);
3937 if (reg > MVPP2_PHY_REG_MASK) {
3938 printf("Err: Invalid register offset %d\n", reg);
3942 /* wait till the SMI is not busy */
3943 if (smi_wait_ready(priv) < 0)
3946 /* fill the phy address and regiser offset and read opcode */
3947 smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS)
3948 | (reg << MVPP2_SMI_REG_ADDR_OFFS)
3949 | MVPP2_SMI_OPCODE_READ;
3951 /* write the smi register */
3952 writel(smi_reg, priv->lms_base + MVPP2_SMI);
3954 /* wait till read value is ready */
3955 timeout = MVPP2_SMI_TIMEOUT;
3958 /* read smi register */
3959 smi_reg = readl(priv->lms_base + MVPP2_SMI);
3960 if (timeout-- == 0) {
3961 printf("Err: SMI read ready timeout\n");
3964 } while (!(smi_reg & MVPP2_SMI_READ_VALID));
3966 /* Wait for the data to update in the SMI register */
3967 for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
3970 return readl(priv->lms_base + MVPP2_SMI) & MVPP2_SMI_DATA_MASK;
3974 * mpp2_mdio_write - miiphy_write callback function.
3976 * Returns 0 if write succeed, -EINVAL on bad parameters
3979 static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
3982 struct mvpp2 *priv = bus->priv;
3985 /* check parameters */
3986 if (addr > MVPP2_PHY_ADDR_MASK) {
3987 printf("Error: Invalid PHY address %d\n", addr);
3991 if (reg > MVPP2_PHY_REG_MASK) {
3992 printf("Err: Invalid register offset %d\n", reg);
3996 /* wait till the SMI is not busy */
3997 if (smi_wait_ready(priv) < 0)
4000 /* fill the phy addr and reg offset and write opcode and data */
4001 smi_reg = value << MVPP2_SMI_DATA_OFFS;
4002 smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS)
4003 | (reg << MVPP2_SMI_REG_ADDR_OFFS);
4004 smi_reg &= ~MVPP2_SMI_OPCODE_READ;
4006 /* write the smi register */
4007 writel(smi_reg, priv->lms_base + MVPP2_SMI);
4012 static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
4014 struct mvpp2_port *port = dev_get_priv(dev);
4015 struct mvpp2_rx_desc *rx_desc;
4016 struct mvpp2_bm_pool *bm_pool;
4017 dma_addr_t dma_addr;
4019 int pool, rx_bytes, err;
4021 struct mvpp2_rx_queue *rxq;
4022 u32 cause_rx_tx, cause_rx, cause_misc;
4025 cause_rx_tx = mvpp2_read(port->priv,
4026 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
4027 cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
4028 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
4029 if (!cause_rx_tx && !cause_misc)
4032 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
4034 /* Process RX packets */
4035 cause_rx |= port->pending_cause_rx;
4036 rxq = mvpp2_get_rx_queue(port, cause_rx);
4038 /* Get number of received packets and clamp the to-do */
4039 rx_received = mvpp2_rxq_received(port, rxq->id);
4041 /* Return if no packets are received */
4045 rx_desc = mvpp2_rxq_next_desc_get(rxq);
4046 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
4047 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
4048 rx_bytes -= MVPP2_MH_SIZE;
4049 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
4051 bm = mvpp2_bm_cookie_build(port, rx_desc);
4052 pool = mvpp2_bm_cookie_pool_get(bm);
4053 bm_pool = &port->priv->bm_pools[pool];
4055 /* In case of an error, release the requested buffer pointer
4056 * to the Buffer Manager. This request process is controlled
4057 * by the hardware, and the information about the buffer is
4058 * comprised by the RX descriptor.
4060 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
4061 mvpp2_rx_error(port, rx_desc);
4062 /* Return the buffer to the pool */
4063 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
4067 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
4069 netdev_err(port->dev, "failed to refill BM pools\n");
4073 /* Update Rx queue management counters */
4075 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
4077 /* give packet to stack - skip on first n bytes */
4078 data = (u8 *)dma_addr + 2 + 32;
4084 * No cache invalidation needed here, since the rx_buffer's are
4085 * located in a uncached memory region
4093 static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4098 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4099 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4101 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4103 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4104 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4107 static int mvpp2_send(struct udevice *dev, void *packet, int length)
4109 struct mvpp2_port *port = dev_get_priv(dev);
4110 struct mvpp2_tx_queue *txq, *aggr_txq;
4111 struct mvpp2_tx_desc *tx_desc;
4115 txq = port->txqs[0];
4116 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
4118 /* Get a descriptor for the first part of the packet */
4119 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4120 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4121 mvpp2_txdesc_size_set(port, tx_desc, length);
4122 mvpp2_txdesc_offset_set(port, tx_desc,
4123 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
4124 mvpp2_txdesc_dma_addr_set(port, tx_desc,
4125 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
4126 /* First and Last descriptor */
4127 mvpp2_txdesc_cmd_set(port, tx_desc,
4128 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
4129 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
4132 flush_dcache_range((unsigned long)packet,
4133 (unsigned long)packet + ALIGN(length, PKTALIGN));
4135 /* Enable transmit */
4137 mvpp2_aggr_txq_pend_desc_add(port, 1);
4139 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4143 if (timeout++ > 10000) {
4144 printf("timeout: packet not sent from aggregated to phys TXQ\n");
4147 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
4150 /* Enable TXQ drain */
4151 mvpp2_txq_drain(port, txq, 1);
4155 if (timeout++ > 10000) {
4156 printf("timeout: packet not sent\n");
4159 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
4162 /* Disable TXQ drain */
4163 mvpp2_txq_drain(port, txq, 0);
4168 static int mvpp2_start(struct udevice *dev)
4170 struct eth_pdata *pdata = dev_get_platdata(dev);
4171 struct mvpp2_port *port = dev_get_priv(dev);
4173 /* Load current MAC address */
4174 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
4176 /* Reconfigure parser accept the original MAC address */
4177 mvpp2_prs_update_mac_da(port, port->dev_addr);
4179 mvpp2_port_power_up(port);
4181 mvpp2_open(dev, port);
4186 static void mvpp2_stop(struct udevice *dev)
4188 struct mvpp2_port *port = dev_get_priv(dev);
4190 mvpp2_stop_dev(port);
4191 mvpp2_cleanup_rxqs(port);
4192 mvpp2_cleanup_txqs(port);
4195 static int mvpp2_probe(struct udevice *dev)
4197 struct mvpp2_port *port = dev_get_priv(dev);
4198 struct mvpp2 *priv = dev_get_priv(dev->parent);
4201 /* Initialize network controller */
4202 err = mvpp2_init(dev, priv);
4204 dev_err(&pdev->dev, "failed to initialize controller\n");
4208 return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv,
4209 &buffer_loc.first_rxq);
4212 static const struct eth_ops mvpp2_ops = {
4213 .start = mvpp2_start,
4219 static struct driver mvpp2_driver = {
4222 .probe = mvpp2_probe,
4224 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
4225 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
4229 * Use a MISC device to bind the n instances (child nodes) of the
4230 * network base controller in UCLASS_ETH.
4232 static int mvpp2_base_probe(struct udevice *dev)
4234 struct mvpp2 *priv = dev_get_priv(dev);
4235 struct mii_dev *bus;
4240 /* Save hw-version */
4241 priv->hw_version = dev_get_driver_data(dev);
4244 * U-Boot special buffer handling:
4246 * Allocate buffer area for descs and rx_buffers. This is only
4247 * done once for all interfaces. As only one interface can
4248 * be active. Make this area DMA-safe by disabling the D-cache
4251 /* Align buffer area for descs and rx_buffers to 1MiB */
4252 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
4253 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
4254 BD_SPACE, DCACHE_OFF);
4256 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
4257 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
4259 buffer_loc.tx_descs =
4260 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
4261 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
4263 buffer_loc.rx_descs =
4264 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
4265 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
4267 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
4268 buffer_loc.bm_pool[i] =
4269 (unsigned long *)((unsigned long)bd_space + size);
4270 if (priv->hw_version == MVPP21)
4271 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
4273 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
4276 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
4277 buffer_loc.rx_buffer[i] =
4278 (unsigned long *)((unsigned long)bd_space + size);
4279 size += RX_BUFFER_SIZE;
4282 /* Save base addresses for later use */
4283 priv->base = (void *)dev_get_addr_index(dev, 0);
4284 if (IS_ERR(priv->base))
4285 return PTR_ERR(priv->base);
4287 priv->lms_base = (void *)dev_get_addr_index(dev, 1);
4288 if (IS_ERR(priv->lms_base))
4289 return PTR_ERR(priv->lms_base);
4291 /* Finally create and register the MDIO bus driver */
4294 printf("Failed to allocate MDIO bus\n");
4298 bus->read = mpp2_mdio_read;
4299 bus->write = mpp2_mdio_write;
4300 snprintf(bus->name, sizeof(bus->name), dev->name);
4301 bus->priv = (void *)priv;
4304 return mdio_register(bus);
4307 static int mvpp2_base_bind(struct udevice *parent)
4309 const void *blob = gd->fdt_blob;
4310 int node = dev_of_offset(parent);
4311 struct uclass_driver *drv;
4312 struct udevice *dev;
4313 struct eth_pdata *plat;
4318 /* Lookup eth driver */
4319 drv = lists_uclass_lookup(UCLASS_ETH);
4321 puts("Cannot find eth driver\n");
4325 fdt_for_each_subnode(subnode, blob, node) {
4326 /* Skip disabled ports */
4327 if (!fdtdec_get_is_enabled(blob, subnode))
4330 plat = calloc(1, sizeof(*plat));
4334 id = fdtdec_get_int(blob, subnode, "port-id", -1);
4336 name = calloc(1, 16);
4337 sprintf(name, "mvpp2-%d", id);
4339 /* Create child device UCLASS_ETH and bind it */
4340 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
4341 dev_set_of_offset(dev, subnode);
4347 static const struct udevice_id mvpp2_ids[] = {
4349 .compatible = "marvell,armada-375-pp2",
4355 U_BOOT_DRIVER(mvpp2_base) = {
4356 .name = "mvpp2_base",
4358 .of_match = mvpp2_ids,
4359 .bind = mvpp2_base_bind,
4360 .probe = mvpp2_base_probe,
4361 .priv_auto_alloc_size = sizeof(struct mvpp2),