2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
18 #include <dm/device-internal.h>
25 #include <linux/errno.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/soc.h>
31 #include <linux/compat.h>
32 #include <linux/mbus.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 /* Some linux -> U-Boot compatibility stuff */
37 #define netdev_err(dev, fmt, args...) \
39 #define netdev_warn(dev, fmt, args...) \
41 #define netdev_info(dev, fmt, args...) \
43 #define netdev_dbg(dev, fmt, args...) \
46 #define ETH_ALEN 6 /* Octets in one ethernet addr */
48 #define __verify_pcpu_ptr(ptr) \
50 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
54 #define VERIFY_PERCPU_PTR(__p) \
56 __verify_pcpu_ptr(__p); \
57 (typeof(*(__p)) __kernel __force *)(__p); \
60 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
61 #define smp_processor_id() 0
62 #define num_present_cpus() 1
63 #define for_each_present_cpu(cpu) \
64 for ((cpu) = 0; (cpu) < 1; (cpu)++)
66 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
68 #define CONFIG_NR_CPUS 1
69 #define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
71 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
72 #define WRAP (2 + ETH_HLEN + 4 + 32)
74 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
76 #define MVPP2_SMI_TIMEOUT 10000
78 /* RX Fifo Registers */
79 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
80 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
81 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
82 #define MVPP2_RX_FIFO_INIT_REG 0x64
84 /* RX DMA Top Registers */
85 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
86 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
87 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
88 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
89 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
90 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
91 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
92 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
93 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
94 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
95 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
96 #define MVPP2_RXQ_POOL_LONG_OFFS 24
97 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
98 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
99 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
100 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
101 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
103 /* Parser Registers */
104 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
105 #define MVPP2_PRS_PORT_LU_MAX 0xf
106 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
107 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
108 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
109 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
110 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
111 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
112 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
113 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
114 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
115 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
116 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
117 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
118 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
119 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
120 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
122 /* Classifier Registers */
123 #define MVPP2_CLS_MODE_REG 0x1800
124 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
125 #define MVPP2_CLS_PORT_WAY_REG 0x1810
126 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
127 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
128 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
129 #define MVPP2_CLS_LKP_TBL_REG 0x1818
130 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
131 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
132 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
133 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
134 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
135 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
136 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
137 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
138 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
139 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
140 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
141 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
143 /* Descriptor Manager Top Registers */
144 #define MVPP2_RXQ_NUM_REG 0x2040
145 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
146 #define MVPP22_DESC_ADDR_OFFS 8
147 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
148 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
149 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
150 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
151 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
152 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
153 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
154 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
155 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
156 #define MVPP2_RXQ_THRESH_REG 0x204c
157 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
158 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
159 #define MVPP2_RXQ_INDEX_REG 0x2050
160 #define MVPP2_TXQ_NUM_REG 0x2080
161 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
162 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
163 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
164 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
165 #define MVPP2_TXQ_THRESH_REG 0x2094
166 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
167 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
168 #define MVPP2_TXQ_INDEX_REG 0x2098
169 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
170 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
171 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
172 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
173 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
174 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
175 #define MVPP2_TXQ_PENDING_REG 0x20a0
176 #define MVPP2_TXQ_PENDING_MASK 0x3fff
177 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
178 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
179 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
180 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
181 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
182 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
183 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
184 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
185 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
186 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
187 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
188 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
189 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
190 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
191 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
192 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
193 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
195 /* MBUS bridge registers */
196 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
197 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
198 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
199 #define MVPP2_BASE_ADDR_ENABLE 0x4060
201 /* AXI Bridge Registers */
202 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
203 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
204 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
205 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
206 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
207 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
208 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
209 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
210 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
211 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
212 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
213 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
215 /* Values for AXI Bridge registers */
216 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
217 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
219 #define MVPP22_AXI_CODE_CACHE_OFFS 0
220 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
222 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
223 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
224 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
226 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
227 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
229 /* Interrupt Cause and Mask registers */
230 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
231 #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
233 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
234 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
235 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
236 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
238 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
239 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
241 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
242 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
243 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
244 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
246 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
247 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
248 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
249 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
250 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
251 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
252 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
253 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
254 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
255 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
256 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
257 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
258 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
259 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
260 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
261 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
262 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
263 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
265 /* Buffer Manager registers */
266 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
267 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
268 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
269 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
270 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
271 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
272 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
273 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
274 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
275 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
276 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
277 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
278 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
279 #define MVPP2_BM_START_MASK BIT(0)
280 #define MVPP2_BM_STOP_MASK BIT(1)
281 #define MVPP2_BM_STATE_MASK BIT(4)
282 #define MVPP2_BM_LOW_THRESH_OFFS 8
283 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
284 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
285 MVPP2_BM_LOW_THRESH_OFFS)
286 #define MVPP2_BM_HIGH_THRESH_OFFS 16
287 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
288 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
289 MVPP2_BM_HIGH_THRESH_OFFS)
290 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
291 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
292 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
293 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
294 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
295 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
296 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
297 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
298 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
299 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
300 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
301 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
302 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
303 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
304 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
305 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
306 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
307 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
308 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
309 #define MVPP21_BM_MC_RLS_REG 0x64c4
310 #define MVPP2_BM_MC_ID_MASK 0xfff
311 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
312 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
313 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
314 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
315 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
316 #define MVPP22_BM_MC_RLS_REG 0x64d4
318 /* TX Scheduler registers */
319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
320 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
322 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
323 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
324 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
325 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
326 #define MVPP2_TXP_MTU_MAX 0x7FFFF
327 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
328 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
329 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
330 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
331 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
332 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
333 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
334 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
335 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
336 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
337 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
338 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
339 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
340 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
342 /* TX general registers */
343 #define MVPP2_TX_SNOOP_REG 0x8800
344 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
345 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
348 #define MVPP2_SRC_ADDR_MIDDLE 0x24
349 #define MVPP2_SRC_ADDR_HIGH 0x28
350 #define MVPP2_PHY_AN_CFG0_REG 0x34
351 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
352 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
353 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
355 /* Per-port registers */
356 #define MVPP2_GMAC_CTRL_0_REG 0x0
357 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
358 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
359 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
360 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
361 #define MVPP2_GMAC_CTRL_1_REG 0x4
362 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
363 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
364 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
365 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
366 #define MVPP2_GMAC_SA_LOW_OFFS 7
367 #define MVPP2_GMAC_CTRL_2_REG 0x8
368 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
369 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
370 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
371 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
372 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
373 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
374 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
375 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
376 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
377 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
378 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
379 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
380 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
381 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
382 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
383 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
384 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
385 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
387 #define MVPP22_SMI_MISC_CFG_REG 0x1204
388 #define MVPP22_SMI_POLLING_EN BIT(10)
390 #define MVPP22_PORT_BASE 0x30e00
391 #define MVPP22_PORT_OFFSET 0x1000
393 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
395 /* Descriptor ring Macros */
396 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
397 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
399 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
400 #define MVPP2_SMI 0x0054
401 #define MVPP2_PHY_REG_MASK 0x1f
402 /* SMI register fields */
403 #define MVPP2_SMI_DATA_OFFS 0 /* Data */
404 #define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
405 #define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
406 #define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
407 #define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
408 #define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
409 #define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
410 #define MVPP2_SMI_BUSY (1 << 28) /* Busy */
412 #define MVPP2_PHY_ADDR_MASK 0x1f
413 #define MVPP2_PHY_REG_MASK 0x1f
415 /* Various constants */
418 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
419 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
420 #define MVPP2_RX_COAL_PKTS 32
421 #define MVPP2_RX_COAL_USEC 100
423 /* The two bytes Marvell header. Either contains a special value used
424 * by Marvell switches when a specific hardware mode is enabled (not
425 * supported by this driver) or is filled automatically by zeroes on
426 * the RX side. Those two bytes being at the front of the Ethernet
427 * header, they allow to have the IP header aligned on a 4 bytes
428 * boundary automatically: the hardware skips those two bytes on its
431 #define MVPP2_MH_SIZE 2
432 #define MVPP2_ETH_TYPE_LEN 2
433 #define MVPP2_PPPOE_HDR_SIZE 8
434 #define MVPP2_VLAN_TAG_LEN 4
436 /* Lbtd 802.3 type */
437 #define MVPP2_IP_LBDT_TYPE 0xfffa
439 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
440 #define MVPP2_TX_CSUM_MAX_SIZE 9800
442 /* Timeout constants */
443 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
444 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
446 #define MVPP2_TX_MTU_MAX 0x7ffff
448 /* Maximum number of T-CONTs of PON port */
449 #define MVPP2_MAX_TCONT 16
451 /* Maximum number of supported ports */
452 #define MVPP2_MAX_PORTS 4
454 /* Maximum number of TXQs used by single port */
455 #define MVPP2_MAX_TXQ 8
457 /* Maximum number of RXQs used by single port */
458 #define MVPP2_MAX_RXQ 8
460 /* Default number of TXQs in use */
461 #define MVPP2_DEFAULT_TXQ 1
463 /* Dfault number of RXQs in use */
464 #define MVPP2_DEFAULT_RXQ 1
465 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
467 /* Total number of RXQs available to all ports */
468 #define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
470 /* Max number of Rx descriptors */
471 #define MVPP2_MAX_RXD 16
473 /* Max number of Tx descriptors */
474 #define MVPP2_MAX_TXD 16
476 /* Amount of Tx descriptors that can be reserved at once by CPU */
477 #define MVPP2_CPU_DESC_CHUNK 64
479 /* Max number of Tx descriptors in each aggregated queue */
480 #define MVPP2_AGGR_TXQ_SIZE 256
482 /* Descriptor aligned size */
483 #define MVPP2_DESC_ALIGNED_SIZE 32
485 /* Descriptor alignment mask */
486 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
488 /* RX FIFO constants */
489 #define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
490 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
491 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
493 /* RX buffer constants */
494 #define MVPP2_SKB_SHINFO_SIZE \
497 #define MVPP2_RX_PKT_SIZE(mtu) \
498 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
499 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
501 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
502 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
503 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
504 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
506 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
508 /* IPv6 max L3 address size */
509 #define MVPP2_MAX_L3_ADDR_SIZE 16
512 #define MVPP2_F_LOOPBACK BIT(0)
514 /* Marvell tag types */
515 enum mvpp2_tag_type {
516 MVPP2_TAG_TYPE_NONE = 0,
517 MVPP2_TAG_TYPE_MH = 1,
518 MVPP2_TAG_TYPE_DSA = 2,
519 MVPP2_TAG_TYPE_EDSA = 3,
520 MVPP2_TAG_TYPE_VLAN = 4,
521 MVPP2_TAG_TYPE_LAST = 5
524 /* Parser constants */
525 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
526 #define MVPP2_PRS_TCAM_WORDS 6
527 #define MVPP2_PRS_SRAM_WORDS 4
528 #define MVPP2_PRS_FLOW_ID_SIZE 64
529 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
530 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
531 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
532 #define MVPP2_PRS_IPV4_HEAD 0x40
533 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
534 #define MVPP2_PRS_IPV4_MC 0xe0
535 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
536 #define MVPP2_PRS_IPV4_BC_MASK 0xff
537 #define MVPP2_PRS_IPV4_IHL 0x5
538 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
539 #define MVPP2_PRS_IPV6_MC 0xff
540 #define MVPP2_PRS_IPV6_MC_MASK 0xff
541 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
542 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
543 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
544 #define MVPP2_PRS_DBL_VLANS_MAX 100
547 * - lookup ID - 4 bits
549 * - additional information - 1 byte
550 * - header data - 8 bytes
551 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
553 #define MVPP2_PRS_AI_BITS 8
554 #define MVPP2_PRS_PORT_MASK 0xff
555 #define MVPP2_PRS_LU_MASK 0xf
556 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
557 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
558 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
559 (((offs) * 2) - ((offs) % 2) + 2)
560 #define MVPP2_PRS_TCAM_AI_BYTE 16
561 #define MVPP2_PRS_TCAM_PORT_BYTE 17
562 #define MVPP2_PRS_TCAM_LU_BYTE 20
563 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
564 #define MVPP2_PRS_TCAM_INV_WORD 5
565 /* Tcam entries ID */
566 #define MVPP2_PE_DROP_ALL 0
567 #define MVPP2_PE_FIRST_FREE_TID 1
568 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
569 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
570 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
571 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
572 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
573 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
574 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
575 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
576 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
577 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
578 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
579 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
580 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
581 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
582 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
583 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
584 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
585 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
586 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
587 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
588 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
589 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
590 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
591 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
592 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
595 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
597 #define MVPP2_PRS_SRAM_RI_OFFS 0
598 #define MVPP2_PRS_SRAM_RI_WORD 0
599 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
600 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
601 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
602 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
603 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
604 #define MVPP2_PRS_SRAM_UDF_OFFS 73
605 #define MVPP2_PRS_SRAM_UDF_BITS 8
606 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
607 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
608 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
609 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
610 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
611 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
612 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
613 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
614 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
615 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
616 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
617 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
618 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
619 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
620 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
621 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
622 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
623 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
624 #define MVPP2_PRS_SRAM_AI_OFFS 90
625 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
626 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
627 #define MVPP2_PRS_SRAM_AI_MASK 0xff
628 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
629 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
630 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
631 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
633 /* Sram result info bits assignment */
634 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
635 #define MVPP2_PRS_RI_DSA_MASK 0x2
636 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
637 #define MVPP2_PRS_RI_VLAN_NONE 0x0
638 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
639 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
640 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
641 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
642 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
643 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
644 #define MVPP2_PRS_RI_L2_UCAST 0x0
645 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
646 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
647 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
648 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
649 #define MVPP2_PRS_RI_L3_UN 0x0
650 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
651 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
652 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
653 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
654 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
655 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
656 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
657 #define MVPP2_PRS_RI_L3_UCAST 0x0
658 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
659 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
660 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
661 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
662 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
663 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
664 #define MVPP2_PRS_RI_L4_TCP BIT(22)
665 #define MVPP2_PRS_RI_L4_UDP BIT(23)
666 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
667 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
668 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
669 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
671 /* Sram additional info bits assignment */
672 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
673 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
674 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
675 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
676 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
677 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
678 #define MVPP2_PRS_SINGLE_VLAN_AI 0
679 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
682 #define MVPP2_PRS_TAGGED true
683 #define MVPP2_PRS_UNTAGGED false
684 #define MVPP2_PRS_EDSA true
685 #define MVPP2_PRS_DSA false
687 /* MAC entries, shadow udf */
689 MVPP2_PRS_UDF_MAC_DEF,
690 MVPP2_PRS_UDF_MAC_RANGE,
691 MVPP2_PRS_UDF_L2_DEF,
692 MVPP2_PRS_UDF_L2_DEF_COPY,
693 MVPP2_PRS_UDF_L2_USER,
697 enum mvpp2_prs_lookup {
711 enum mvpp2_prs_l3_cast {
712 MVPP2_PRS_L3_UNI_CAST,
713 MVPP2_PRS_L3_MULTI_CAST,
714 MVPP2_PRS_L3_BROAD_CAST
717 /* Classifier constants */
718 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
719 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
720 #define MVPP2_CLS_LKP_TBL_SIZE 64
723 #define MVPP2_BM_POOLS_NUM 1
724 #define MVPP2_BM_LONG_BUF_NUM 16
725 #define MVPP2_BM_SHORT_BUF_NUM 16
726 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
727 #define MVPP2_BM_POOL_PTR_ALIGN 128
728 #define MVPP2_BM_SWF_LONG_POOL(port) 0
730 /* BM cookie (32 bits) definition */
731 #define MVPP2_BM_COOKIE_POOL_OFFS 8
732 #define MVPP2_BM_COOKIE_CPU_OFFS 24
734 /* BM short pool packet size
735 * These value assure that for SWF the total number
736 * of bytes allocated for each buffer will be 512
738 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
748 /* Shared Packet Processor resources */
750 /* Shared registers' base addresses */
752 void __iomem *lms_base;
753 void __iomem *iface_base;
755 /* List of pointers to port structures */
756 struct mvpp2_port **port_list;
758 /* Aggregated TXQs */
759 struct mvpp2_tx_queue *aggr_txqs;
762 struct mvpp2_bm_pool *bm_pools;
764 /* PRS shadow table */
765 struct mvpp2_prs_shadow *prs_shadow;
766 /* PRS auxiliary table for double vlan entries control */
767 bool *prs_double_vlans;
773 enum { MVPP21, MVPP22 } hw_version;
778 struct mvpp2_pcpu_stats {
788 /* Index of the port from the "group of ports" complex point
797 /* Per-port registers' base address */
800 struct mvpp2_rx_queue **rxqs;
801 struct mvpp2_tx_queue **txqs;
805 u32 pending_cause_rx;
807 /* Per-CPU port control */
808 struct mvpp2_port_pcpu __percpu *pcpu;
815 struct mvpp2_pcpu_stats __percpu *stats;
817 struct phy_device *phy_dev;
818 phy_interface_t phy_interface;
826 struct mvpp2_bm_pool *pool_long;
827 struct mvpp2_bm_pool *pool_short;
829 /* Index of first port's physical RXQ */
832 u8 dev_addr[ETH_ALEN];
835 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
836 * layout of the transmit and reception DMA descriptors, and their
837 * layout is therefore defined by the hardware design
840 #define MVPP2_TXD_L3_OFF_SHIFT 0
841 #define MVPP2_TXD_IP_HLEN_SHIFT 8
842 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
843 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
844 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
845 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
846 #define MVPP2_TXD_L4_UDP BIT(24)
847 #define MVPP2_TXD_L3_IP6 BIT(26)
848 #define MVPP2_TXD_L_DESC BIT(28)
849 #define MVPP2_TXD_F_DESC BIT(29)
851 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
852 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
853 #define MVPP2_RXD_ERR_CRC 0x0
854 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
855 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
856 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
857 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
858 #define MVPP2_RXD_HWF_SYNC BIT(21)
859 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
860 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
861 #define MVPP2_RXD_L4_TCP BIT(25)
862 #define MVPP2_RXD_L4_UDP BIT(26)
863 #define MVPP2_RXD_L3_IP4 BIT(28)
864 #define MVPP2_RXD_L3_IP6 BIT(30)
865 #define MVPP2_RXD_BUF_HDR BIT(31)
867 /* HW TX descriptor for PPv2.1 */
868 struct mvpp21_tx_desc {
869 u32 command; /* Options used by HW for packet transmitting.*/
870 u8 packet_offset; /* the offset from the buffer beginning */
871 u8 phys_txq; /* destination queue ID */
872 u16 data_size; /* data size of transmitted packet in bytes */
873 u32 buf_dma_addr; /* physical addr of transmitted buffer */
874 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
875 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
876 u32 reserved2; /* reserved (for future use) */
879 /* HW RX descriptor for PPv2.1 */
880 struct mvpp21_rx_desc {
881 u32 status; /* info about received packet */
882 u16 reserved1; /* parser_info (for future use, PnC) */
883 u16 data_size; /* size of received packet in bytes */
884 u32 buf_dma_addr; /* physical address of the buffer */
885 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
886 u16 reserved2; /* gem_port_id (for future use, PON) */
887 u16 reserved3; /* csum_l4 (for future use, PnC) */
888 u8 reserved4; /* bm_qset (for future use, BM) */
890 u16 reserved6; /* classify_info (for future use, PnC) */
891 u32 reserved7; /* flow_id (for future use, PnC) */
895 /* HW TX descriptor for PPv2.2 */
896 struct mvpp22_tx_desc {
902 u64 buf_dma_addr_ptp;
906 /* HW RX descriptor for PPv2.2 */
907 struct mvpp22_rx_desc {
913 u64 buf_dma_addr_key_hash;
917 /* Opaque type used by the driver to manipulate the HW TX and RX
920 struct mvpp2_tx_desc {
922 struct mvpp21_tx_desc pp21;
923 struct mvpp22_tx_desc pp22;
927 struct mvpp2_rx_desc {
929 struct mvpp21_rx_desc pp21;
930 struct mvpp22_rx_desc pp22;
934 /* Per-CPU Tx queue control */
935 struct mvpp2_txq_pcpu {
938 /* Number of Tx DMA descriptors in the descriptor ring */
941 /* Number of currently used Tx DMA descriptor in the
946 /* Number of Tx DMA descriptors reserved for each CPU */
949 /* Index of last TX DMA descriptor that was inserted */
952 /* Index of the TX DMA descriptor to be cleaned up */
956 struct mvpp2_tx_queue {
957 /* Physical number of this Tx queue */
960 /* Logical number of this Tx queue */
963 /* Number of Tx DMA descriptors in the descriptor ring */
966 /* Number of currently used Tx DMA descriptor in the descriptor ring */
969 /* Per-CPU control of physical Tx queues */
970 struct mvpp2_txq_pcpu __percpu *pcpu;
974 /* Virtual address of thex Tx DMA descriptors array */
975 struct mvpp2_tx_desc *descs;
977 /* DMA address of the Tx DMA descriptors array */
978 dma_addr_t descs_dma;
980 /* Index of the last Tx DMA descriptor */
983 /* Index of the next Tx DMA descriptor to process */
984 int next_desc_to_proc;
987 struct mvpp2_rx_queue {
988 /* RX queue number, in the range 0-31 for physical RXQs */
991 /* Num of rx descriptors in the rx descriptor ring */
997 /* Virtual address of the RX DMA descriptors array */
998 struct mvpp2_rx_desc *descs;
1000 /* DMA address of the RX DMA descriptors array */
1001 dma_addr_t descs_dma;
1003 /* Index of the last RX DMA descriptor */
1006 /* Index of the next RX DMA descriptor to process */
1007 int next_desc_to_proc;
1009 /* ID of port to which physical RXQ is mapped */
1012 /* Port's logic RXQ number to which physical RXQ is mapped */
1016 union mvpp2_prs_tcam_entry {
1017 u32 word[MVPP2_PRS_TCAM_WORDS];
1018 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
1021 union mvpp2_prs_sram_entry {
1022 u32 word[MVPP2_PRS_SRAM_WORDS];
1023 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
1026 struct mvpp2_prs_entry {
1028 union mvpp2_prs_tcam_entry tcam;
1029 union mvpp2_prs_sram_entry sram;
1032 struct mvpp2_prs_shadow {
1039 /* User defined offset */
1047 struct mvpp2_cls_flow_entry {
1049 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
1052 struct mvpp2_cls_lookup_entry {
1058 struct mvpp2_bm_pool {
1059 /* Pool number in the range 0-7 */
1061 enum mvpp2_bm_type type;
1063 /* Buffer Pointers Pool External (BPPE) size */
1065 /* Number of buffers for this pool */
1067 /* Pool buffer size */
1072 /* BPPE virtual base address */
1073 unsigned long *virt_addr;
1074 /* BPPE DMA base address */
1075 dma_addr_t dma_addr;
1077 /* Ports using BM pool */
1080 /* Occupied buffers indicator */
1084 /* Static declaractions */
1086 /* Number of RXQs used by single port */
1087 static int rxq_number = MVPP2_DEFAULT_RXQ;
1088 /* Number of TXQs used by single port */
1089 static int txq_number = MVPP2_DEFAULT_TXQ;
1091 #define MVPP2_DRIVER_NAME "mvpp2"
1092 #define MVPP2_DRIVER_VERSION "1.0"
1095 * U-Boot internal data, mostly uncached buffers for descriptors and data
1097 struct buffer_location {
1098 struct mvpp2_tx_desc *aggr_tx_descs;
1099 struct mvpp2_tx_desc *tx_descs;
1100 struct mvpp2_rx_desc *rx_descs;
1101 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1102 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
1107 * All 4 interfaces use the same global buffer, since only one interface
1108 * can be enabled at once
1110 static struct buffer_location buffer_loc;
1113 * Page table entries are set to 1MB, or multiples of 1MB
1114 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1116 #define BD_SPACE (1 << 20)
1118 /* Utility/helper methods */
1120 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1122 writel(data, priv->base + offset);
1125 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1127 return readl(priv->base + offset);
1130 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1131 struct mvpp2_tx_desc *tx_desc,
1132 dma_addr_t dma_addr)
1134 if (port->priv->hw_version == MVPP21) {
1135 tx_desc->pp21.buf_dma_addr = dma_addr;
1137 u64 val = (u64)dma_addr;
1139 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1140 tx_desc->pp22.buf_dma_addr_ptp |= val;
1144 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1145 struct mvpp2_tx_desc *tx_desc,
1148 if (port->priv->hw_version == MVPP21)
1149 tx_desc->pp21.data_size = size;
1151 tx_desc->pp22.data_size = size;
1154 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1155 struct mvpp2_tx_desc *tx_desc,
1158 if (port->priv->hw_version == MVPP21)
1159 tx_desc->pp21.phys_txq = txq;
1161 tx_desc->pp22.phys_txq = txq;
1164 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1165 struct mvpp2_tx_desc *tx_desc,
1166 unsigned int command)
1168 if (port->priv->hw_version == MVPP21)
1169 tx_desc->pp21.command = command;
1171 tx_desc->pp22.command = command;
1174 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1175 struct mvpp2_tx_desc *tx_desc,
1176 unsigned int offset)
1178 if (port->priv->hw_version == MVPP21)
1179 tx_desc->pp21.packet_offset = offset;
1181 tx_desc->pp22.packet_offset = offset;
1184 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1185 struct mvpp2_rx_desc *rx_desc)
1187 if (port->priv->hw_version == MVPP21)
1188 return rx_desc->pp21.buf_dma_addr;
1190 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
1193 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1194 struct mvpp2_rx_desc *rx_desc)
1196 if (port->priv->hw_version == MVPP21)
1197 return rx_desc->pp21.buf_cookie;
1199 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
1202 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1203 struct mvpp2_rx_desc *rx_desc)
1205 if (port->priv->hw_version == MVPP21)
1206 return rx_desc->pp21.data_size;
1208 return rx_desc->pp22.data_size;
1211 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1212 struct mvpp2_rx_desc *rx_desc)
1214 if (port->priv->hw_version == MVPP21)
1215 return rx_desc->pp21.status;
1217 return rx_desc->pp22.status;
1220 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1222 txq_pcpu->txq_get_index++;
1223 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1224 txq_pcpu->txq_get_index = 0;
1227 /* Get number of physical egress port */
1228 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1230 return MVPP2_MAX_TCONT + port->id;
1233 /* Get number of physical TXQ */
1234 static inline int mvpp2_txq_phys(int port, int txq)
1236 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1239 /* Parser configuration routines */
1241 /* Update parser tcam and sram hw entries */
1242 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1246 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1249 /* Clear entry invalidation bit */
1250 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1252 /* Write tcam index - indirect access */
1253 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1254 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1255 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1257 /* Write sram index - indirect access */
1258 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1259 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1260 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1265 /* Read tcam entry from hw */
1266 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1270 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1273 /* Write tcam index - indirect access */
1274 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1276 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1277 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1278 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1279 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1281 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1282 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1284 /* Write sram index - indirect access */
1285 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1286 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1287 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1292 /* Invalidate tcam hw entry */
1293 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1295 /* Write index - indirect access */
1296 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1297 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1298 MVPP2_PRS_TCAM_INV_MASK);
1301 /* Enable shadow table entry and set its lookup ID */
1302 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1304 priv->prs_shadow[index].valid = true;
1305 priv->prs_shadow[index].lu = lu;
1308 /* Update ri fields in shadow table entry */
1309 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1310 unsigned int ri, unsigned int ri_mask)
1312 priv->prs_shadow[index].ri_mask = ri_mask;
1313 priv->prs_shadow[index].ri = ri;
1316 /* Update lookup field in tcam sw entry */
1317 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1319 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1321 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1322 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1325 /* Update mask for single port in tcam sw entry */
1326 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1327 unsigned int port, bool add)
1329 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1332 pe->tcam.byte[enable_off] &= ~(1 << port);
1334 pe->tcam.byte[enable_off] |= 1 << port;
1337 /* Update port map in tcam sw entry */
1338 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1341 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1342 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1344 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1345 pe->tcam.byte[enable_off] &= ~port_mask;
1346 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1349 /* Obtain port map from tcam sw entry */
1350 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1352 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1354 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1357 /* Set byte of data and its enable bits in tcam sw entry */
1358 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1359 unsigned int offs, unsigned char byte,
1360 unsigned char enable)
1362 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1363 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1366 /* Get byte of data and its enable bits from tcam sw entry */
1367 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1368 unsigned int offs, unsigned char *byte,
1369 unsigned char *enable)
1371 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1372 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1375 /* Set ethertype in tcam sw entry */
1376 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1377 unsigned short ethertype)
1379 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1380 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1383 /* Set bits in sram sw entry */
1384 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1387 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1390 /* Clear bits in sram sw entry */
1391 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1394 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1397 /* Update ri bits in sram sw entry */
1398 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1399 unsigned int bits, unsigned int mask)
1403 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1404 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1406 if (!(mask & BIT(i)))
1410 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1412 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1414 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1418 /* Update ai bits in sram sw entry */
1419 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1420 unsigned int bits, unsigned int mask)
1423 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1425 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1427 if (!(mask & BIT(i)))
1431 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1433 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1435 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1439 /* Read ai bits from sram sw entry */
1440 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1443 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1444 int ai_en_off = ai_off + 1;
1445 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1447 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1448 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1453 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1456 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1459 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1461 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1462 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1463 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1466 /* In the sram sw entry set sign and value of the next lookup offset
1467 * and the offset value generated to the classifier
1469 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1474 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1477 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1481 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1482 (unsigned char)shift;
1484 /* Reset and set operation */
1485 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1486 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1487 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1489 /* Set base offset as current */
1490 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1493 /* In the sram sw entry set sign and value of the user defined offset
1494 * generated to the classifier
1496 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1497 unsigned int type, int offset,
1502 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1503 offset = 0 - offset;
1505 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1509 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1510 MVPP2_PRS_SRAM_UDF_MASK);
1511 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1512 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1513 MVPP2_PRS_SRAM_UDF_BITS)] &=
1514 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1515 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1516 MVPP2_PRS_SRAM_UDF_BITS)] |=
1517 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1519 /* Set offset type */
1520 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1521 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1522 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1524 /* Set offset operation */
1525 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1526 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1527 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1529 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1530 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1531 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1532 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1534 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1535 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1536 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1538 /* Set base offset as current */
1539 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1542 /* Find parser flow entry */
1543 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1545 struct mvpp2_prs_entry *pe;
1548 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1551 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1553 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1554 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1557 if (!priv->prs_shadow[tid].valid ||
1558 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1562 mvpp2_prs_hw_read(priv, pe);
1563 bits = mvpp2_prs_sram_ai_get(pe);
1565 /* Sram store classification lookup ID in AI bits [5:0] */
1566 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1574 /* Return first free tcam index, seeking from start to end */
1575 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1583 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1584 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1586 for (tid = start; tid <= end; tid++) {
1587 if (!priv->prs_shadow[tid].valid)
1594 /* Enable/disable dropping all mac da's */
1595 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1597 struct mvpp2_prs_entry pe;
1599 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1600 /* Entry exist - update port only */
1601 pe.index = MVPP2_PE_DROP_ALL;
1602 mvpp2_prs_hw_read(priv, &pe);
1604 /* Entry doesn't exist - create new */
1605 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1606 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1607 pe.index = MVPP2_PE_DROP_ALL;
1609 /* Non-promiscuous mode for all ports - DROP unknown packets */
1610 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1611 MVPP2_PRS_RI_DROP_MASK);
1613 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1614 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1616 /* Update shadow table */
1617 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1619 /* Mask all ports */
1620 mvpp2_prs_tcam_port_map_set(&pe, 0);
1623 /* Update port mask */
1624 mvpp2_prs_tcam_port_set(&pe, port, add);
1626 mvpp2_prs_hw_write(priv, &pe);
1629 /* Set port to promiscuous mode */
1630 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1632 struct mvpp2_prs_entry pe;
1634 /* Promiscuous mode - Accept unknown packets */
1636 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1637 /* Entry exist - update port only */
1638 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1639 mvpp2_prs_hw_read(priv, &pe);
1641 /* Entry doesn't exist - create new */
1642 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1643 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1644 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1646 /* Continue - set next lookup */
1647 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1649 /* Set result info bits */
1650 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1651 MVPP2_PRS_RI_L2_CAST_MASK);
1653 /* Shift to ethertype */
1654 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1655 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1657 /* Mask all ports */
1658 mvpp2_prs_tcam_port_map_set(&pe, 0);
1660 /* Update shadow table */
1661 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1664 /* Update port mask */
1665 mvpp2_prs_tcam_port_set(&pe, port, add);
1667 mvpp2_prs_hw_write(priv, &pe);
1670 /* Accept multicast */
1671 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1674 struct mvpp2_prs_entry pe;
1675 unsigned char da_mc;
1677 /* Ethernet multicast address first byte is
1678 * 0x01 for IPv4 and 0x33 for IPv6
1680 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1682 if (priv->prs_shadow[index].valid) {
1683 /* Entry exist - update port only */
1685 mvpp2_prs_hw_read(priv, &pe);
1687 /* Entry doesn't exist - create new */
1688 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1689 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1692 /* Continue - set next lookup */
1693 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1695 /* Set result info bits */
1696 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1697 MVPP2_PRS_RI_L2_CAST_MASK);
1699 /* Update tcam entry data first byte */
1700 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1702 /* Shift to ethertype */
1703 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1704 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1706 /* Mask all ports */
1707 mvpp2_prs_tcam_port_map_set(&pe, 0);
1709 /* Update shadow table */
1710 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1713 /* Update port mask */
1714 mvpp2_prs_tcam_port_set(&pe, port, add);
1716 mvpp2_prs_hw_write(priv, &pe);
1719 /* Parser per-port initialization */
1720 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1721 int lu_max, int offset)
1726 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1727 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1728 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1729 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1731 /* Set maximum number of loops for packet received from port */
1732 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1733 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1734 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1735 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1737 /* Set initial offset for packet header extraction for the first
1740 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1741 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1742 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1743 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1746 /* Default flow entries initialization for all ports */
1747 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1749 struct mvpp2_prs_entry pe;
1752 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1753 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1754 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1755 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1757 /* Mask all ports */
1758 mvpp2_prs_tcam_port_map_set(&pe, 0);
1761 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1762 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1764 /* Update shadow table and hw entry */
1765 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1766 mvpp2_prs_hw_write(priv, &pe);
1770 /* Set default entry for Marvell Header field */
1771 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1773 struct mvpp2_prs_entry pe;
1775 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1777 pe.index = MVPP2_PE_MH_DEFAULT;
1778 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1779 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1780 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1781 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1783 /* Unmask all ports */
1784 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1786 /* Update shadow table and hw entry */
1787 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1788 mvpp2_prs_hw_write(priv, &pe);
1791 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1792 * multicast MAC addresses
1794 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1796 struct mvpp2_prs_entry pe;
1798 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1800 /* Non-promiscuous mode for all ports - DROP unknown packets */
1801 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1802 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1804 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1805 MVPP2_PRS_RI_DROP_MASK);
1806 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1807 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1809 /* Unmask all ports */
1810 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1812 /* Update shadow table and hw entry */
1813 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1814 mvpp2_prs_hw_write(priv, &pe);
1816 /* place holders only - no ports */
1817 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1818 mvpp2_prs_mac_promisc_set(priv, 0, false);
1819 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1820 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1823 /* Match basic ethertypes */
1824 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1826 struct mvpp2_prs_entry pe;
1829 /* Ethertype: PPPoE */
1830 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1831 MVPP2_PE_LAST_FREE_TID);
1835 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1836 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1839 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
1841 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1842 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1843 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1844 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1845 MVPP2_PRS_RI_PPPOE_MASK);
1847 /* Update shadow table and hw entry */
1848 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1849 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1850 priv->prs_shadow[pe.index].finish = false;
1851 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
1852 MVPP2_PRS_RI_PPPOE_MASK);
1853 mvpp2_prs_hw_write(priv, &pe);
1855 /* Ethertype: ARP */
1856 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1857 MVPP2_PE_LAST_FREE_TID);
1861 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1862 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1865 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
1867 /* Generate flow in the next iteration*/
1868 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1869 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1870 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
1871 MVPP2_PRS_RI_L3_PROTO_MASK);
1873 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1875 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1877 /* Update shadow table and hw entry */
1878 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1879 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1880 priv->prs_shadow[pe.index].finish = true;
1881 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
1882 MVPP2_PRS_RI_L3_PROTO_MASK);
1883 mvpp2_prs_hw_write(priv, &pe);
1885 /* Ethertype: LBTD */
1886 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1887 MVPP2_PE_LAST_FREE_TID);
1891 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1892 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1895 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
1897 /* Generate flow in the next iteration*/
1898 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1899 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1900 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1901 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1902 MVPP2_PRS_RI_CPU_CODE_MASK |
1903 MVPP2_PRS_RI_UDF3_MASK);
1905 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1907 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1909 /* Update shadow table and hw entry */
1910 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1911 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1912 priv->prs_shadow[pe.index].finish = true;
1913 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1914 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1915 MVPP2_PRS_RI_CPU_CODE_MASK |
1916 MVPP2_PRS_RI_UDF3_MASK);
1917 mvpp2_prs_hw_write(priv, &pe);
1919 /* Ethertype: IPv4 without options */
1920 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1921 MVPP2_PE_LAST_FREE_TID);
1925 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1926 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1929 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
1930 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1931 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
1932 MVPP2_PRS_IPV4_HEAD_MASK |
1933 MVPP2_PRS_IPV4_IHL_MASK);
1935 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1936 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
1937 MVPP2_PRS_RI_L3_PROTO_MASK);
1938 /* Skip eth_type + 4 bytes of IP header */
1939 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
1940 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1942 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1944 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1946 /* Update shadow table and hw entry */
1947 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1948 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1949 priv->prs_shadow[pe.index].finish = false;
1950 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
1951 MVPP2_PRS_RI_L3_PROTO_MASK);
1952 mvpp2_prs_hw_write(priv, &pe);
1954 /* Ethertype: IPv4 with options */
1955 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1956 MVPP2_PE_LAST_FREE_TID);
1962 /* Clear tcam data before updating */
1963 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
1964 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
1966 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1967 MVPP2_PRS_IPV4_HEAD,
1968 MVPP2_PRS_IPV4_HEAD_MASK);
1970 /* Clear ri before updating */
1971 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
1972 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
1973 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
1974 MVPP2_PRS_RI_L3_PROTO_MASK);
1976 /* Update shadow table and hw entry */
1977 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1978 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1979 priv->prs_shadow[pe.index].finish = false;
1980 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
1981 MVPP2_PRS_RI_L3_PROTO_MASK);
1982 mvpp2_prs_hw_write(priv, &pe);
1984 /* Ethertype: IPv6 without options */
1985 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1986 MVPP2_PE_LAST_FREE_TID);
1990 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1991 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1994 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
1996 /* Skip DIP of IPV6 header */
1997 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
1998 MVPP2_MAX_L3_ADDR_SIZE,
1999 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2000 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2001 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2002 MVPP2_PRS_RI_L3_PROTO_MASK);
2004 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2006 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2008 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2009 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2010 priv->prs_shadow[pe.index].finish = false;
2011 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2012 MVPP2_PRS_RI_L3_PROTO_MASK);
2013 mvpp2_prs_hw_write(priv, &pe);
2015 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2016 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2017 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2018 pe.index = MVPP2_PE_ETH_TYPE_UN;
2020 /* Unmask all ports */
2021 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2023 /* Generate flow in the next iteration*/
2024 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2025 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2026 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2027 MVPP2_PRS_RI_L3_PROTO_MASK);
2028 /* Set L3 offset even it's unknown L3 */
2029 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2031 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2033 /* Update shadow table and hw entry */
2034 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2035 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2036 priv->prs_shadow[pe.index].finish = true;
2037 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2038 MVPP2_PRS_RI_L3_PROTO_MASK);
2039 mvpp2_prs_hw_write(priv, &pe);
2044 /* Parser default initialization */
2045 static int mvpp2_prs_default_init(struct udevice *dev,
2050 /* Enable tcam table */
2051 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2053 /* Clear all tcam and sram entries */
2054 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2055 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2056 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2057 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2059 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2060 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2061 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2064 /* Invalidate all tcam entries */
2065 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2066 mvpp2_prs_hw_inv(priv, index);
2068 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2069 sizeof(struct mvpp2_prs_shadow),
2071 if (!priv->prs_shadow)
2074 /* Always start from lookup = 0 */
2075 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2076 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2077 MVPP2_PRS_PORT_LU_MAX, 0);
2079 mvpp2_prs_def_flow_init(priv);
2081 mvpp2_prs_mh_init(priv);
2083 mvpp2_prs_mac_init(priv);
2085 err = mvpp2_prs_etype_init(priv);
2092 /* Compare MAC DA with tcam entry data */
2093 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2094 const u8 *da, unsigned char *mask)
2096 unsigned char tcam_byte, tcam_mask;
2099 for (index = 0; index < ETH_ALEN; index++) {
2100 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2101 if (tcam_mask != mask[index])
2104 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2111 /* Find tcam entry with matched pair <MAC DA, port> */
2112 static struct mvpp2_prs_entry *
2113 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2114 unsigned char *mask, int udf_type)
2116 struct mvpp2_prs_entry *pe;
2119 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2122 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2124 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2125 for (tid = MVPP2_PE_FIRST_FREE_TID;
2126 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2127 unsigned int entry_pmap;
2129 if (!priv->prs_shadow[tid].valid ||
2130 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2131 (priv->prs_shadow[tid].udf != udf_type))
2135 mvpp2_prs_hw_read(priv, pe);
2136 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2138 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2147 /* Update parser's mac da entry */
2148 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2149 const u8 *da, bool add)
2151 struct mvpp2_prs_entry *pe;
2152 unsigned int pmap, len, ri;
2153 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2156 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2157 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2158 MVPP2_PRS_UDF_MAC_DEF);
2165 /* Create new TCAM entry */
2166 /* Find first range mac entry*/
2167 for (tid = MVPP2_PE_FIRST_FREE_TID;
2168 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2169 if (priv->prs_shadow[tid].valid &&
2170 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2171 (priv->prs_shadow[tid].udf ==
2172 MVPP2_PRS_UDF_MAC_RANGE))
2175 /* Go through the all entries from first to last */
2176 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2181 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2184 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2187 /* Mask all ports */
2188 mvpp2_prs_tcam_port_map_set(pe, 0);
2191 /* Update port mask */
2192 mvpp2_prs_tcam_port_set(pe, port, add);
2194 /* Invalidate the entry if no ports are left enabled */
2195 pmap = mvpp2_prs_tcam_port_map_get(pe);
2201 mvpp2_prs_hw_inv(priv, pe->index);
2202 priv->prs_shadow[pe->index].valid = false;
2207 /* Continue - set next lookup */
2208 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2210 /* Set match on DA */
2213 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2215 /* Set result info bits */
2216 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2218 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2219 MVPP2_PRS_RI_MAC_ME_MASK);
2220 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2221 MVPP2_PRS_RI_MAC_ME_MASK);
2223 /* Shift to ethertype */
2224 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2225 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2227 /* Update shadow table and hw entry */
2228 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2229 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2230 mvpp2_prs_hw_write(priv, pe);
2237 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2241 /* Remove old parser entry */
2242 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2247 /* Add new parser entry */
2248 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2252 /* Set addr in the device */
2253 memcpy(port->dev_addr, da, ETH_ALEN);
2258 /* Set prs flow for the port */
2259 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2261 struct mvpp2_prs_entry *pe;
2264 pe = mvpp2_prs_flow_find(port->priv, port->id);
2266 /* Such entry not exist */
2268 /* Go through the all entires from last to first */
2269 tid = mvpp2_prs_tcam_first_free(port->priv,
2270 MVPP2_PE_LAST_FREE_TID,
2271 MVPP2_PE_FIRST_FREE_TID);
2275 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2279 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2283 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2284 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2286 /* Update shadow table */
2287 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2290 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2291 mvpp2_prs_hw_write(port->priv, pe);
2297 /* Classifier configuration routines */
2299 /* Update classification flow table registers */
2300 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2301 struct mvpp2_cls_flow_entry *fe)
2303 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2304 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2305 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2306 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2309 /* Update classification lookup table register */
2310 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2311 struct mvpp2_cls_lookup_entry *le)
2315 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2316 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2317 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2320 /* Classifier default initialization */
2321 static void mvpp2_cls_init(struct mvpp2 *priv)
2323 struct mvpp2_cls_lookup_entry le;
2324 struct mvpp2_cls_flow_entry fe;
2327 /* Enable classifier */
2328 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2330 /* Clear classifier flow table */
2331 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2332 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2334 mvpp2_cls_flow_write(priv, &fe);
2337 /* Clear classifier lookup table */
2339 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2342 mvpp2_cls_lookup_write(priv, &le);
2345 mvpp2_cls_lookup_write(priv, &le);
2349 static void mvpp2_cls_port_config(struct mvpp2_port *port)
2351 struct mvpp2_cls_lookup_entry le;
2354 /* Set way for the port */
2355 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2356 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2357 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2359 /* Pick the entry to be accessed in lookup ID decoding table
2360 * according to the way and lkpid.
2362 le.lkpid = port->id;
2366 /* Set initial CPU queue for receiving packets */
2367 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2368 le.data |= port->first_rxq;
2370 /* Disable classification engines */
2371 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2373 /* Update lookup ID table entry */
2374 mvpp2_cls_lookup_write(port->priv, &le);
2377 /* Set CPU queue number for oversize packets */
2378 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2382 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2383 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2385 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2386 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2388 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2389 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2390 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2393 /* Buffer Manager configuration routines */
2396 static int mvpp2_bm_pool_create(struct udevice *dev,
2398 struct mvpp2_bm_pool *bm_pool, int size)
2402 /* Number of buffer pointers must be a multiple of 16, as per
2403 * hardware constraints
2405 if (!IS_ALIGNED(size, 16))
2408 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
2409 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
2410 if (!bm_pool->virt_addr)
2413 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2414 MVPP2_BM_POOL_PTR_ALIGN)) {
2415 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2416 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2420 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
2421 lower_32_bits(bm_pool->dma_addr));
2422 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2424 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2425 val |= MVPP2_BM_START_MASK;
2426 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2428 bm_pool->type = MVPP2_BM_FREE;
2429 bm_pool->size = size;
2430 bm_pool->pkt_size = 0;
2431 bm_pool->buf_num = 0;
2436 /* Set pool buffer size */
2437 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2438 struct mvpp2_bm_pool *bm_pool,
2443 bm_pool->buf_size = buf_size;
2445 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2446 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2449 /* Free all buffers from the pool */
2450 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2451 struct mvpp2_bm_pool *bm_pool)
2453 bm_pool->buf_num = 0;
2457 static int mvpp2_bm_pool_destroy(struct udevice *dev,
2459 struct mvpp2_bm_pool *bm_pool)
2463 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2464 if (bm_pool->buf_num) {
2465 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2469 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2470 val |= MVPP2_BM_STOP_MASK;
2471 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2476 static int mvpp2_bm_pools_init(struct udevice *dev,
2480 struct mvpp2_bm_pool *bm_pool;
2482 /* Create all pools with maximum size */
2483 size = MVPP2_BM_POOL_SIZE_MAX;
2484 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2485 bm_pool = &priv->bm_pools[i];
2487 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2489 goto err_unroll_pools;
2490 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
2495 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2496 for (i = i - 1; i >= 0; i--)
2497 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2501 static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2505 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2506 /* Mask BM all interrupts */
2507 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2508 /* Clear BM cause register */
2509 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2512 /* Allocate and initialize BM pools */
2513 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2514 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2515 if (!priv->bm_pools)
2518 err = mvpp2_bm_pools_init(dev, priv);
2524 /* Attach long pool to rxq */
2525 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2526 int lrxq, int long_pool)
2531 /* Get queue physical ID */
2532 prxq = port->rxqs[lrxq]->id;
2534 if (port->priv->hw_version == MVPP21)
2535 mask = MVPP21_RXQ_POOL_LONG_MASK;
2537 mask = MVPP22_RXQ_POOL_LONG_MASK;
2539 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2541 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
2542 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2545 /* Set pool number in a BM cookie */
2546 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2550 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2551 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2556 /* Get pool number from a BM cookie */
2557 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
2559 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2562 /* Release buffer to BM */
2563 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
2564 dma_addr_t buf_dma_addr,
2565 unsigned long buf_phys_addr)
2567 if (port->priv->hw_version == MVPP22) {
2570 if (sizeof(dma_addr_t) == 8)
2571 val |= upper_32_bits(buf_dma_addr) &
2572 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2574 if (sizeof(phys_addr_t) == 8)
2575 val |= (upper_32_bits(buf_phys_addr)
2576 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2577 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2579 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2582 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2583 * returned in the "cookie" field of the RX
2584 * descriptor. Instead of storing the virtual address, we
2585 * store the physical address
2587 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
2588 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
2591 /* Refill BM pool */
2592 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
2593 dma_addr_t dma_addr,
2594 phys_addr_t phys_addr)
2596 int pool = mvpp2_bm_cookie_pool_get(bm);
2598 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2601 /* Allocate buffers for the pool */
2602 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2603 struct mvpp2_bm_pool *bm_pool, int buf_num)
2608 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2609 netdev_err(port->dev,
2610 "cannot allocate %d buffers for pool %d\n",
2611 buf_num, bm_pool->id);
2615 for (i = 0; i < buf_num; i++) {
2616 mvpp2_bm_pool_put(port, bm_pool->id,
2617 (dma_addr_t)buffer_loc.rx_buffer[i],
2618 (unsigned long)buffer_loc.rx_buffer[i]);
2622 /* Update BM driver with number of buffers added to pool */
2623 bm_pool->buf_num += i;
2624 bm_pool->in_use_thresh = bm_pool->buf_num / 4;
2629 /* Notify the driver that BM pool is being used as specific type and return the
2630 * pool pointer on success
2632 static struct mvpp2_bm_pool *
2633 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2636 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2639 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2640 netdev_err(port->dev, "mixing pool types is forbidden\n");
2644 if (new_pool->type == MVPP2_BM_FREE)
2645 new_pool->type = type;
2647 /* Allocate buffers in case BM pool is used as long pool, but packet
2648 * size doesn't match MTU or BM pool hasn't being used yet
2650 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2651 (new_pool->pkt_size == 0)) {
2654 /* Set default buffer number or free all the buffers in case
2655 * the pool is not empty
2657 pkts_num = new_pool->buf_num;
2659 pkts_num = type == MVPP2_BM_SWF_LONG ?
2660 MVPP2_BM_LONG_BUF_NUM :
2661 MVPP2_BM_SHORT_BUF_NUM;
2663 mvpp2_bm_bufs_free(NULL,
2664 port->priv, new_pool);
2666 new_pool->pkt_size = pkt_size;
2668 /* Allocate buffers for this pool */
2669 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2670 if (num != pkts_num) {
2671 dev_err(dev, "pool %d: %d of %d allocated\n",
2672 new_pool->id, num, pkts_num);
2677 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
2678 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
2683 /* Initialize pools for swf */
2684 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2688 if (!port->pool_long) {
2690 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2693 if (!port->pool_long)
2696 port->pool_long->port_map |= (1 << port->id);
2698 for (rxq = 0; rxq < rxq_number; rxq++)
2699 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2705 /* Port configuration routines */
2707 static void mvpp2_port_mii_set(struct mvpp2_port *port)
2711 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2713 switch (port->phy_interface) {
2714 case PHY_INTERFACE_MODE_SGMII:
2715 val |= MVPP2_GMAC_INBAND_AN_MASK;
2717 case PHY_INTERFACE_MODE_RGMII:
2718 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2720 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2723 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2726 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2730 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2731 val |= MVPP2_GMAC_FC_ADV_EN;
2732 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2735 static void mvpp2_port_enable(struct mvpp2_port *port)
2739 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2740 val |= MVPP2_GMAC_PORT_EN_MASK;
2741 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2742 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2745 static void mvpp2_port_disable(struct mvpp2_port *port)
2749 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2750 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2751 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2754 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2755 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2759 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2760 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2761 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2764 /* Configure loopback port */
2765 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2769 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2771 if (port->speed == 1000)
2772 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2774 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2776 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2777 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2779 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2781 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2784 static void mvpp2_port_reset(struct mvpp2_port *port)
2788 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2789 ~MVPP2_GMAC_PORT_RESET_MASK;
2790 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2792 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2793 MVPP2_GMAC_PORT_RESET_MASK)
2797 /* Change maximum receive size of the port */
2798 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2802 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2803 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2804 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2805 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2806 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2809 /* Set defaults to the MVPP2 port */
2810 static void mvpp2_defaults_set(struct mvpp2_port *port)
2812 int tx_port_num, val, queue, ptxq, lrxq;
2814 if (port->priv->hw_version == MVPP21) {
2815 /* Configure port to loopback if needed */
2816 if (port->flags & MVPP2_F_LOOPBACK)
2817 mvpp2_port_loopback_set(port);
2819 /* Update TX FIFO MIN Threshold */
2820 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2821 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
2822 /* Min. TX threshold must be less than minimal packet length */
2823 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2824 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2827 /* Disable Legacy WRR, Disable EJP, Release from reset */
2828 tx_port_num = mvpp2_egress_port(port);
2829 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
2831 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
2833 /* Close bandwidth for all queues */
2834 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
2835 ptxq = mvpp2_txq_phys(port->id, queue);
2836 mvpp2_write(port->priv,
2837 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
2840 /* Set refill period to 1 usec, refill tokens
2841 * and bucket size to maximum
2843 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
2844 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
2845 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
2846 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2847 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
2848 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
2849 val = MVPP2_TXP_TOKEN_SIZE_MAX;
2850 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2852 /* Set MaximumLowLatencyPacketSize value to 256 */
2853 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
2854 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
2855 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2857 /* Enable Rx cache snoop */
2858 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2859 queue = port->rxqs[lrxq]->id;
2860 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2861 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
2862 MVPP2_SNOOP_BUF_HDR_MASK;
2863 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2867 /* Enable/disable receiving packets */
2868 static void mvpp2_ingress_enable(struct mvpp2_port *port)
2873 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2874 queue = port->rxqs[lrxq]->id;
2875 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2876 val &= ~MVPP2_RXQ_DISABLE_MASK;
2877 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2881 static void mvpp2_ingress_disable(struct mvpp2_port *port)
2886 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2887 queue = port->rxqs[lrxq]->id;
2888 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2889 val |= MVPP2_RXQ_DISABLE_MASK;
2890 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2894 /* Enable transmit via physical egress queue
2895 * - HW starts take descriptors from DRAM
2897 static void mvpp2_egress_enable(struct mvpp2_port *port)
2901 int tx_port_num = mvpp2_egress_port(port);
2903 /* Enable all initialized TXs. */
2905 for (queue = 0; queue < txq_number; queue++) {
2906 struct mvpp2_tx_queue *txq = port->txqs[queue];
2908 if (txq->descs != NULL)
2909 qmap |= (1 << queue);
2912 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2913 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2916 /* Disable transmit via physical egress queue
2917 * - HW doesn't take descriptors from DRAM
2919 static void mvpp2_egress_disable(struct mvpp2_port *port)
2923 int tx_port_num = mvpp2_egress_port(port);
2925 /* Issue stop command for active channels only */
2926 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2927 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2928 MVPP2_TXP_SCHED_ENQ_MASK;
2930 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2931 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2933 /* Wait for all Tx activity to terminate. */
2936 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2937 netdev_warn(port->dev,
2938 "Tx stop timed out, status=0x%08x\n",
2945 /* Check port TX Command register that all
2946 * Tx queues are stopped
2948 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2949 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2952 /* Rx descriptors helper methods */
2954 /* Get number of Rx descriptors occupied by received packets */
2956 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2958 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2960 return val & MVPP2_RXQ_OCCUPIED_MASK;
2963 /* Update Rx queue status with the number of occupied and available
2964 * Rx descriptor slots.
2967 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2968 int used_count, int free_count)
2970 /* Decrement the number of used descriptors and increment count
2971 * increment the number of free descriptors.
2973 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2975 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2978 /* Get pointer to next RX descriptor to be processed by SW */
2979 static inline struct mvpp2_rx_desc *
2980 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
2982 int rx_desc = rxq->next_desc_to_proc;
2984 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
2985 prefetch(rxq->descs + rxq->next_desc_to_proc);
2986 return rxq->descs + rx_desc;
2989 /* Set rx queue offset */
2990 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
2991 int prxq, int offset)
2995 /* Convert offset from bytes to units of 32 bytes */
2996 offset = offset >> 5;
2998 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2999 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
3002 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
3003 MVPP2_RXQ_PACKET_OFFSET_MASK);
3005 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3008 /* Obtain BM cookie information from descriptor */
3009 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
3010 struct mvpp2_rx_desc *rx_desc)
3012 int cpu = smp_processor_id();
3015 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
3016 MVPP2_RXD_BM_POOL_ID_MASK) >>
3017 MVPP2_RXD_BM_POOL_ID_OFFS;
3019 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
3020 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
3023 /* Tx descriptors helper methods */
3025 /* Get number of Tx descriptors waiting to be transmitted by HW */
3026 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
3027 struct mvpp2_tx_queue *txq)
3031 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3032 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3034 return val & MVPP2_TXQ_PENDING_MASK;
3037 /* Get pointer to next Tx descriptor to be processed (send) by HW */
3038 static struct mvpp2_tx_desc *
3039 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
3041 int tx_desc = txq->next_desc_to_proc;
3043 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
3044 return txq->descs + tx_desc;
3047 /* Update HW with number of aggregated Tx descriptors to be sent */
3048 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
3050 /* aggregated access - relevant TXQ number is written in TX desc */
3051 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3054 /* Get number of sent descriptors and decrement counter.
3055 * The number of sent descriptors is returned.
3058 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
3059 struct mvpp2_tx_queue *txq)
3063 /* Reading status reg resets transmitted descriptor counter */
3064 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
3066 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
3067 MVPP2_TRANSMITTED_COUNT_OFFSET;
3070 static void mvpp2_txq_sent_counter_clear(void *arg)
3072 struct mvpp2_port *port = arg;
3075 for (queue = 0; queue < txq_number; queue++) {
3076 int id = port->txqs[queue]->id;
3078 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
3082 /* Set max sizes for Tx queues */
3083 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
3086 int txq, tx_port_num;
3088 mtu = port->pkt_size * 8;
3089 if (mtu > MVPP2_TXP_MTU_MAX)
3090 mtu = MVPP2_TXP_MTU_MAX;
3092 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3095 /* Indirect access to registers */
3096 tx_port_num = mvpp2_egress_port(port);
3097 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3100 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
3101 val &= ~MVPP2_TXP_MTU_MAX;
3103 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
3105 /* TXP token size and all TXQs token size must be larger that MTU */
3106 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
3107 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
3110 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
3112 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3115 for (txq = 0; txq < txq_number; txq++) {
3116 val = mvpp2_read(port->priv,
3117 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
3118 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
3122 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
3124 mvpp2_write(port->priv,
3125 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
3131 /* Free Tx queue skbuffs */
3132 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
3133 struct mvpp2_tx_queue *txq,
3134 struct mvpp2_txq_pcpu *txq_pcpu, int num)
3138 for (i = 0; i < num; i++)
3139 mvpp2_txq_inc_get(txq_pcpu);
3142 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
3145 int queue = fls(cause) - 1;
3147 return port->rxqs[queue];
3150 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
3153 int queue = fls(cause) - 1;
3155 return port->txqs[queue];
3158 /* Rx/Tx queue initialization/cleanup methods */
3160 /* Allocate and initialize descriptors for aggr TXQ */
3161 static int mvpp2_aggr_txq_init(struct udevice *dev,
3162 struct mvpp2_tx_queue *aggr_txq,
3163 int desc_num, int cpu,
3168 /* Allocate memory for TX descriptors */
3169 aggr_txq->descs = buffer_loc.aggr_tx_descs;
3170 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
3171 if (!aggr_txq->descs)
3174 /* Make sure descriptor address is cache line size aligned */
3175 BUG_ON(aggr_txq->descs !=
3176 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3178 aggr_txq->last_desc = aggr_txq->size - 1;
3180 /* Aggr TXQ no reset WA */
3181 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
3182 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
3184 /* Set Tx descriptors queue starting address indirect
3187 if (priv->hw_version == MVPP21)
3188 txq_dma = aggr_txq->descs_dma;
3190 txq_dma = aggr_txq->descs_dma >>
3191 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
3193 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
3194 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
3199 /* Create a specified Rx queue */
3200 static int mvpp2_rxq_init(struct mvpp2_port *port,
3201 struct mvpp2_rx_queue *rxq)
3206 rxq->size = port->rx_ring_size;
3208 /* Allocate memory for RX descriptors */
3209 rxq->descs = buffer_loc.rx_descs;
3210 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
3214 BUG_ON(rxq->descs !=
3215 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3217 rxq->last_desc = rxq->size - 1;
3219 /* Zero occupied and non-occupied counters - direct access */
3220 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3222 /* Set Rx descriptors queue starting address - indirect access */
3223 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
3224 if (port->priv->hw_version == MVPP21)
3225 rxq_dma = rxq->descs_dma;
3227 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
3228 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
3229 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
3230 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
3233 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
3235 /* Add number of descriptors ready for receiving packets */
3236 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
3241 /* Push packets received by the RXQ to BM pool */
3242 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
3243 struct mvpp2_rx_queue *rxq)
3247 rx_received = mvpp2_rxq_received(port, rxq->id);
3251 for (i = 0; i < rx_received; i++) {
3252 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3253 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
3255 mvpp2_pool_refill(port, bm,
3256 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
3257 mvpp2_rxdesc_cookie_get(port, rx_desc));
3259 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
3262 /* Cleanup Rx queue */
3263 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
3264 struct mvpp2_rx_queue *rxq)
3266 mvpp2_rxq_drop_pkts(port, rxq);
3270 rxq->next_desc_to_proc = 0;
3273 /* Clear Rx descriptors queue starting address and size;
3274 * free descriptor number
3276 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3277 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
3278 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
3279 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
3282 /* Create and initialize a Tx queue */
3283 static int mvpp2_txq_init(struct mvpp2_port *port,
3284 struct mvpp2_tx_queue *txq)
3287 int cpu, desc, desc_per_txq, tx_port_num;
3288 struct mvpp2_txq_pcpu *txq_pcpu;
3290 txq->size = port->tx_ring_size;
3292 /* Allocate memory for Tx descriptors */
3293 txq->descs = buffer_loc.tx_descs;
3294 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
3298 /* Make sure descriptor address is cache line size aligned */
3299 BUG_ON(txq->descs !=
3300 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3302 txq->last_desc = txq->size - 1;
3304 /* Set Tx descriptors queue starting address - indirect access */
3305 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3306 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
3307 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
3308 MVPP2_TXQ_DESC_SIZE_MASK);
3309 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
3310 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
3311 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
3312 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3313 val &= ~MVPP2_TXQ_PENDING_MASK;
3314 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
3316 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
3317 * for each existing TXQ.
3318 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3319 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
3322 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
3323 (txq->log_id * desc_per_txq);
3325 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
3326 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
3327 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
3329 /* WRR / EJP configuration - indirect access */
3330 tx_port_num = mvpp2_egress_port(port);
3331 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3333 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
3334 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
3335 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3336 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
3337 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
3339 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
3340 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
3343 for_each_present_cpu(cpu) {
3344 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3345 txq_pcpu->size = txq->size;
3351 /* Free allocated TXQ resources */
3352 static void mvpp2_txq_deinit(struct mvpp2_port *port,
3353 struct mvpp2_tx_queue *txq)
3357 txq->next_desc_to_proc = 0;
3360 /* Set minimum bandwidth for disabled TXQs */
3361 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
3363 /* Set Tx descriptors queue starting address and size */
3364 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3365 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
3366 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
3369 /* Cleanup Tx ports */
3370 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
3372 struct mvpp2_txq_pcpu *txq_pcpu;
3373 int delay, pending, cpu;
3376 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3377 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
3378 val |= MVPP2_TXQ_DRAIN_EN_MASK;
3379 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3381 /* The napi queue has been stopped so wait for all packets
3382 * to be transmitted.
3386 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
3387 netdev_warn(port->dev,
3388 "port %d: cleaning queue %d timed out\n",
3389 port->id, txq->log_id);
3395 pending = mvpp2_txq_pend_desc_num_get(port, txq);
3398 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
3399 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3401 for_each_present_cpu(cpu) {
3402 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3404 /* Release all packets */
3405 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
3408 txq_pcpu->count = 0;
3409 txq_pcpu->txq_put_index = 0;
3410 txq_pcpu->txq_get_index = 0;
3414 /* Cleanup all Tx queues */
3415 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
3417 struct mvpp2_tx_queue *txq;
3421 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
3423 /* Reset Tx ports and delete Tx queues */
3424 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
3425 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3427 for (queue = 0; queue < txq_number; queue++) {
3428 txq = port->txqs[queue];
3429 mvpp2_txq_clean(port, txq);
3430 mvpp2_txq_deinit(port, txq);
3433 mvpp2_txq_sent_counter_clear(port);
3435 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
3436 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3439 /* Cleanup all Rx queues */
3440 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
3444 for (queue = 0; queue < rxq_number; queue++)
3445 mvpp2_rxq_deinit(port, port->rxqs[queue]);
3448 /* Init all Rx queues for port */
3449 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
3453 for (queue = 0; queue < rxq_number; queue++) {
3454 err = mvpp2_rxq_init(port, port->rxqs[queue]);
3461 mvpp2_cleanup_rxqs(port);
3465 /* Init all tx queues for port */
3466 static int mvpp2_setup_txqs(struct mvpp2_port *port)
3468 struct mvpp2_tx_queue *txq;
3471 for (queue = 0; queue < txq_number; queue++) {
3472 txq = port->txqs[queue];
3473 err = mvpp2_txq_init(port, txq);
3478 mvpp2_txq_sent_counter_clear(port);
3482 mvpp2_cleanup_txqs(port);
3487 static void mvpp2_link_event(struct mvpp2_port *port)
3489 struct phy_device *phydev = port->phy_dev;
3490 int status_change = 0;
3494 if ((port->speed != phydev->speed) ||
3495 (port->duplex != phydev->duplex)) {
3498 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3499 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
3500 MVPP2_GMAC_CONFIG_GMII_SPEED |
3501 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3502 MVPP2_GMAC_AN_SPEED_EN |
3503 MVPP2_GMAC_AN_DUPLEX_EN);
3506 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
3508 if (phydev->speed == SPEED_1000)
3509 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
3510 else if (phydev->speed == SPEED_100)
3511 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
3513 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3515 port->duplex = phydev->duplex;
3516 port->speed = phydev->speed;
3520 if (phydev->link != port->link) {
3521 if (!phydev->link) {
3526 port->link = phydev->link;
3530 if (status_change) {
3532 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3533 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
3534 MVPP2_GMAC_FORCE_LINK_DOWN);
3535 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3536 mvpp2_egress_enable(port);
3537 mvpp2_ingress_enable(port);
3539 mvpp2_ingress_disable(port);
3540 mvpp2_egress_disable(port);
3545 /* Main RX/TX processing routines */
3547 /* Display more error info */
3548 static void mvpp2_rx_error(struct mvpp2_port *port,
3549 struct mvpp2_rx_desc *rx_desc)
3551 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3552 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
3554 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3555 case MVPP2_RXD_ERR_CRC:
3556 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
3559 case MVPP2_RXD_ERR_OVERRUN:
3560 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
3563 case MVPP2_RXD_ERR_RESOURCE:
3564 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
3570 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
3571 static int mvpp2_rx_refill(struct mvpp2_port *port,
3572 struct mvpp2_bm_pool *bm_pool,
3573 u32 bm, dma_addr_t dma_addr)
3575 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
3579 /* Set hw internals when starting port */
3580 static void mvpp2_start_dev(struct mvpp2_port *port)
3582 mvpp2_gmac_max_rx_size_set(port);
3583 mvpp2_txp_max_tx_size_set(port);
3585 mvpp2_port_enable(port);
3588 /* Set hw internals when stopping port */
3589 static void mvpp2_stop_dev(struct mvpp2_port *port)
3591 /* Stop new packets from arriving to RXQs */
3592 mvpp2_ingress_disable(port);
3594 mvpp2_egress_disable(port);
3595 mvpp2_port_disable(port);
3598 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
3600 struct phy_device *phy_dev;
3602 if (!port->init || port->link == 0) {
3603 phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
3604 port->phy_interface);
3605 port->phy_dev = phy_dev;
3607 netdev_err(port->dev, "cannot connect to phy\n");
3610 phy_dev->supported &= PHY_GBIT_FEATURES;
3611 phy_dev->advertising = phy_dev->supported;
3613 port->phy_dev = phy_dev;
3618 phy_config(phy_dev);
3619 phy_startup(phy_dev);
3620 if (!phy_dev->link) {
3621 printf("%s: No link\n", phy_dev->dev->name);
3627 mvpp2_egress_enable(port);
3628 mvpp2_ingress_enable(port);
3634 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
3636 unsigned char mac_bcast[ETH_ALEN] = {
3637 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3640 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
3642 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3645 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
3646 port->dev_addr, true);
3648 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
3651 err = mvpp2_prs_def_flow(port);
3653 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3657 /* Allocate the Rx/Tx queues */
3658 err = mvpp2_setup_rxqs(port);
3660 netdev_err(port->dev, "cannot allocate Rx queues\n");
3664 err = mvpp2_setup_txqs(port);
3666 netdev_err(port->dev, "cannot allocate Tx queues\n");
3670 err = mvpp2_phy_connect(dev, port);
3674 mvpp2_link_event(port);
3676 mvpp2_start_dev(port);
3681 /* No Device ops here in U-Boot */
3683 /* Driver initialization */
3685 static void mvpp2_port_power_up(struct mvpp2_port *port)
3687 struct mvpp2 *priv = port->priv;
3689 mvpp2_port_mii_set(port);
3690 mvpp2_port_periodic_xon_disable(port);
3691 if (priv->hw_version == MVPP21)
3692 mvpp2_port_fc_adv_enable(port);
3693 mvpp2_port_reset(port);
3696 /* Initialize port HW */
3697 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
3699 struct mvpp2 *priv = port->priv;
3700 struct mvpp2_txq_pcpu *txq_pcpu;
3701 int queue, cpu, err;
3703 if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM)
3707 mvpp2_egress_disable(port);
3708 mvpp2_port_disable(port);
3710 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
3715 /* Associate physical Tx queues to this port and initialize.
3716 * The mapping is predefined.
3718 for (queue = 0; queue < txq_number; queue++) {
3719 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
3720 struct mvpp2_tx_queue *txq;
3722 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
3726 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
3731 txq->id = queue_phy_id;
3732 txq->log_id = queue;
3733 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
3734 for_each_present_cpu(cpu) {
3735 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3736 txq_pcpu->cpu = cpu;
3739 port->txqs[queue] = txq;
3742 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
3747 /* Allocate and initialize Rx queue for this port */
3748 for (queue = 0; queue < rxq_number; queue++) {
3749 struct mvpp2_rx_queue *rxq;
3751 /* Map physical Rx queue to port's logical Rx queue */
3752 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
3755 /* Map this Rx queue to a physical queue */
3756 rxq->id = port->first_rxq + queue;
3757 rxq->port = port->id;
3758 rxq->logic_rxq = queue;
3760 port->rxqs[queue] = rxq;
3763 /* Configure Rx queue group interrupt for this port */
3764 if (priv->hw_version == MVPP21) {
3765 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
3770 val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
3771 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
3773 val = (CONFIG_MV_ETH_RXQ <<
3774 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
3775 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
3778 /* Create Rx descriptor rings */
3779 for (queue = 0; queue < rxq_number; queue++) {
3780 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3782 rxq->size = port->rx_ring_size;
3783 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
3784 rxq->time_coal = MVPP2_RX_COAL_USEC;
3787 mvpp2_ingress_disable(port);
3789 /* Port default configuration */
3790 mvpp2_defaults_set(port);
3792 /* Port's classifier configuration */
3793 mvpp2_cls_oversize_rxq_set(port);
3794 mvpp2_cls_port_config(port);
3796 /* Provide an initial Rx packet size */
3797 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
3799 /* Initialize pools for swf */
3800 err = mvpp2_swf_bm_pool_init(port);
3807 /* Ports initialization */
3808 static int mvpp2_port_probe(struct udevice *dev,
3809 struct mvpp2_port *port,
3812 int *next_first_rxq)
3817 const char *phy_mode_str;
3819 int priv_common_regs_num = 2;
3822 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
3824 dev_err(&pdev->dev, "missing phy\n");
3828 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
3830 phy_mode = phy_get_interface_by_name(phy_mode_str);
3831 if (phy_mode == -1) {
3832 dev_err(&pdev->dev, "incorrect phy mode\n");
3836 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
3838 dev_err(&pdev->dev, "missing port-id value\n");
3842 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
3846 port->first_rxq = *next_first_rxq;
3847 port->phy_node = phy_node;
3848 port->phy_interface = phy_mode;
3849 port->phyaddr = phyaddr;
3851 if (priv->hw_version == MVPP21) {
3852 port->base = (void __iomem *)dev_get_addr_index(
3853 dev->parent, priv_common_regs_num + id);
3854 if (IS_ERR(port->base))
3855 return PTR_ERR(port->base);
3859 gop_id = fdtdec_get_int(gd->fdt_blob, port_node,
3862 dev_err(&pdev->dev, "missing gop-port-id value\n");
3866 port->base = priv->iface_base + MVPP22_PORT_BASE +
3867 gop_id * MVPP22_PORT_OFFSET;
3870 port->tx_ring_size = MVPP2_MAX_TXD;
3871 port->rx_ring_size = MVPP2_MAX_RXD;
3873 err = mvpp2_port_init(dev, port);
3875 dev_err(&pdev->dev, "failed to init port %d\n", id);
3878 mvpp2_port_power_up(port);
3880 /* Increment the first Rx queue number to be used by the next port */
3881 *next_first_rxq += CONFIG_MV_ETH_RXQ;
3882 priv->port_list[id] = port;
3886 /* Initialize decoding windows */
3887 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
3893 for (i = 0; i < 6; i++) {
3894 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
3895 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
3898 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
3903 for (i = 0; i < dram->num_cs; i++) {
3904 const struct mbus_dram_window *cs = dram->cs + i;
3906 mvpp2_write(priv, MVPP2_WIN_BASE(i),
3907 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
3908 dram->mbus_dram_target_id);
3910 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
3911 (cs->size - 1) & 0xffff0000);
3913 win_enable |= (1 << i);
3916 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
3919 /* Initialize Rx FIFO's */
3920 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
3924 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
3925 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
3926 MVPP2_RX_FIFO_PORT_DATA_SIZE);
3927 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
3928 MVPP2_RX_FIFO_PORT_ATTR_SIZE);
3931 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
3932 MVPP2_RX_FIFO_PORT_MIN_PKT);
3933 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
3936 static void mvpp2_axi_init(struct mvpp2 *priv)
3938 u32 val, rdval, wrval;
3940 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
3942 /* AXI Bridge Configuration */
3944 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
3945 << MVPP22_AXI_ATTR_CACHE_OFFS;
3946 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
3947 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
3949 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
3950 << MVPP22_AXI_ATTR_CACHE_OFFS;
3951 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
3952 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
3955 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
3956 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
3959 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
3960 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
3961 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
3962 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
3965 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
3966 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
3968 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
3969 << MVPP22_AXI_CODE_CACHE_OFFS;
3970 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
3971 << MVPP22_AXI_CODE_DOMAIN_OFFS;
3972 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
3973 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
3975 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
3976 << MVPP22_AXI_CODE_CACHE_OFFS;
3977 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
3978 << MVPP22_AXI_CODE_DOMAIN_OFFS;
3980 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
3982 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
3983 << MVPP22_AXI_CODE_CACHE_OFFS;
3984 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
3985 << MVPP22_AXI_CODE_DOMAIN_OFFS;
3987 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
3990 /* Initialize network controller common part HW */
3991 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
3993 const struct mbus_dram_target_info *dram_target_info;
3997 /* Checks for hardware constraints (U-Boot uses only one rxq) */
3998 if ((rxq_number > MVPP2_MAX_RXQ) || (txq_number > MVPP2_MAX_TXQ)) {
3999 dev_err(&pdev->dev, "invalid queue size parameter\n");
4003 /* MBUS windows configuration */
4004 dram_target_info = mvebu_mbus_dram_info();
4005 if (dram_target_info)
4006 mvpp2_conf_mbus_windows(dram_target_info, priv);
4008 if (priv->hw_version == MVPP22)
4009 mvpp2_axi_init(priv);
4011 /* Disable HW PHY polling */
4012 if (priv->hw_version == MVPP21) {
4013 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4014 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
4015 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4017 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
4018 val &= ~MVPP22_SMI_POLLING_EN;
4019 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
4022 /* Allocate and initialize aggregated TXQs */
4023 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
4024 sizeof(struct mvpp2_tx_queue),
4026 if (!priv->aggr_txqs)
4029 for_each_present_cpu(i) {
4030 priv->aggr_txqs[i].id = i;
4031 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
4032 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
4033 MVPP2_AGGR_TXQ_SIZE, i, priv);
4039 mvpp2_rx_fifo_init(priv);
4041 /* Reset Rx queue group interrupt configuration */
4042 for (i = 0; i < MVPP2_MAX_PORTS; i++) {
4043 if (priv->hw_version == MVPP21) {
4044 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
4050 val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
4051 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4053 val = (CONFIG_MV_ETH_RXQ <<
4054 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
4056 MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4060 if (priv->hw_version == MVPP21)
4061 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
4062 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
4064 /* Allow cache snoop when transmiting packets */
4065 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
4067 /* Buffer Manager initialization */
4068 err = mvpp2_bm_init(dev, priv);
4072 /* Parser default initialization */
4073 err = mvpp2_prs_default_init(dev, priv);
4077 /* Classifier default initialization */
4078 mvpp2_cls_init(priv);
4083 /* SMI / MDIO functions */
4085 static int smi_wait_ready(struct mvpp2 *priv)
4087 u32 timeout = MVPP2_SMI_TIMEOUT;
4090 /* wait till the SMI is not busy */
4092 /* read smi register */
4093 smi_reg = readl(priv->lms_base + MVPP2_SMI);
4094 if (timeout-- == 0) {
4095 printf("Error: SMI busy timeout\n");
4098 } while (smi_reg & MVPP2_SMI_BUSY);
4104 * mpp2_mdio_read - miiphy_read callback function.
4106 * Returns 16bit phy register value, or 0xffff on error
4108 static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
4110 struct mvpp2 *priv = bus->priv;
4114 /* check parameters */
4115 if (addr > MVPP2_PHY_ADDR_MASK) {
4116 printf("Error: Invalid PHY address %d\n", addr);
4120 if (reg > MVPP2_PHY_REG_MASK) {
4121 printf("Err: Invalid register offset %d\n", reg);
4125 /* wait till the SMI is not busy */
4126 if (smi_wait_ready(priv) < 0)
4129 /* fill the phy address and regiser offset and read opcode */
4130 smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS)
4131 | (reg << MVPP2_SMI_REG_ADDR_OFFS)
4132 | MVPP2_SMI_OPCODE_READ;
4134 /* write the smi register */
4135 writel(smi_reg, priv->lms_base + MVPP2_SMI);
4137 /* wait till read value is ready */
4138 timeout = MVPP2_SMI_TIMEOUT;
4141 /* read smi register */
4142 smi_reg = readl(priv->lms_base + MVPP2_SMI);
4143 if (timeout-- == 0) {
4144 printf("Err: SMI read ready timeout\n");
4147 } while (!(smi_reg & MVPP2_SMI_READ_VALID));
4149 /* Wait for the data to update in the SMI register */
4150 for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
4153 return readl(priv->lms_base + MVPP2_SMI) & MVPP2_SMI_DATA_MASK;
4157 * mpp2_mdio_write - miiphy_write callback function.
4159 * Returns 0 if write succeed, -EINVAL on bad parameters
4162 static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
4165 struct mvpp2 *priv = bus->priv;
4168 /* check parameters */
4169 if (addr > MVPP2_PHY_ADDR_MASK) {
4170 printf("Error: Invalid PHY address %d\n", addr);
4174 if (reg > MVPP2_PHY_REG_MASK) {
4175 printf("Err: Invalid register offset %d\n", reg);
4179 /* wait till the SMI is not busy */
4180 if (smi_wait_ready(priv) < 0)
4183 /* fill the phy addr and reg offset and write opcode and data */
4184 smi_reg = value << MVPP2_SMI_DATA_OFFS;
4185 smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS)
4186 | (reg << MVPP2_SMI_REG_ADDR_OFFS);
4187 smi_reg &= ~MVPP2_SMI_OPCODE_READ;
4189 /* write the smi register */
4190 writel(smi_reg, priv->lms_base + MVPP2_SMI);
4195 static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
4197 struct mvpp2_port *port = dev_get_priv(dev);
4198 struct mvpp2_rx_desc *rx_desc;
4199 struct mvpp2_bm_pool *bm_pool;
4200 dma_addr_t dma_addr;
4202 int pool, rx_bytes, err;
4204 struct mvpp2_rx_queue *rxq;
4205 u32 cause_rx_tx, cause_rx, cause_misc;
4208 cause_rx_tx = mvpp2_read(port->priv,
4209 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
4210 cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
4211 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
4212 if (!cause_rx_tx && !cause_misc)
4215 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
4217 /* Process RX packets */
4218 cause_rx |= port->pending_cause_rx;
4219 rxq = mvpp2_get_rx_queue(port, cause_rx);
4221 /* Get number of received packets and clamp the to-do */
4222 rx_received = mvpp2_rxq_received(port, rxq->id);
4224 /* Return if no packets are received */
4228 rx_desc = mvpp2_rxq_next_desc_get(rxq);
4229 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
4230 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
4231 rx_bytes -= MVPP2_MH_SIZE;
4232 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
4234 bm = mvpp2_bm_cookie_build(port, rx_desc);
4235 pool = mvpp2_bm_cookie_pool_get(bm);
4236 bm_pool = &port->priv->bm_pools[pool];
4238 /* In case of an error, release the requested buffer pointer
4239 * to the Buffer Manager. This request process is controlled
4240 * by the hardware, and the information about the buffer is
4241 * comprised by the RX descriptor.
4243 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
4244 mvpp2_rx_error(port, rx_desc);
4245 /* Return the buffer to the pool */
4246 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
4250 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
4252 netdev_err(port->dev, "failed to refill BM pools\n");
4256 /* Update Rx queue management counters */
4258 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
4260 /* give packet to stack - skip on first n bytes */
4261 data = (u8 *)dma_addr + 2 + 32;
4267 * No cache invalidation needed here, since the rx_buffer's are
4268 * located in a uncached memory region
4276 static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4281 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4282 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4284 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4286 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4287 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4290 static int mvpp2_send(struct udevice *dev, void *packet, int length)
4292 struct mvpp2_port *port = dev_get_priv(dev);
4293 struct mvpp2_tx_queue *txq, *aggr_txq;
4294 struct mvpp2_tx_desc *tx_desc;
4298 txq = port->txqs[0];
4299 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
4301 /* Get a descriptor for the first part of the packet */
4302 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4303 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4304 mvpp2_txdesc_size_set(port, tx_desc, length);
4305 mvpp2_txdesc_offset_set(port, tx_desc,
4306 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
4307 mvpp2_txdesc_dma_addr_set(port, tx_desc,
4308 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
4309 /* First and Last descriptor */
4310 mvpp2_txdesc_cmd_set(port, tx_desc,
4311 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
4312 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
4315 flush_dcache_range((unsigned long)packet,
4316 (unsigned long)packet + ALIGN(length, PKTALIGN));
4318 /* Enable transmit */
4320 mvpp2_aggr_txq_pend_desc_add(port, 1);
4322 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4326 if (timeout++ > 10000) {
4327 printf("timeout: packet not sent from aggregated to phys TXQ\n");
4330 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
4333 /* Enable TXQ drain */
4334 mvpp2_txq_drain(port, txq, 1);
4338 if (timeout++ > 10000) {
4339 printf("timeout: packet not sent\n");
4342 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
4345 /* Disable TXQ drain */
4346 mvpp2_txq_drain(port, txq, 0);
4351 static int mvpp2_start(struct udevice *dev)
4353 struct eth_pdata *pdata = dev_get_platdata(dev);
4354 struct mvpp2_port *port = dev_get_priv(dev);
4356 /* Load current MAC address */
4357 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
4359 /* Reconfigure parser accept the original MAC address */
4360 mvpp2_prs_update_mac_da(port, port->dev_addr);
4362 mvpp2_port_power_up(port);
4364 mvpp2_open(dev, port);
4369 static void mvpp2_stop(struct udevice *dev)
4371 struct mvpp2_port *port = dev_get_priv(dev);
4373 mvpp2_stop_dev(port);
4374 mvpp2_cleanup_rxqs(port);
4375 mvpp2_cleanup_txqs(port);
4378 static int mvpp2_probe(struct udevice *dev)
4380 struct mvpp2_port *port = dev_get_priv(dev);
4381 struct mvpp2 *priv = dev_get_priv(dev->parent);
4384 /* Initialize network controller */
4385 err = mvpp2_init(dev, priv);
4387 dev_err(&pdev->dev, "failed to initialize controller\n");
4391 return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv,
4392 &buffer_loc.first_rxq);
4395 static const struct eth_ops mvpp2_ops = {
4396 .start = mvpp2_start,
4402 static struct driver mvpp2_driver = {
4405 .probe = mvpp2_probe,
4407 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
4408 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
4412 * Use a MISC device to bind the n instances (child nodes) of the
4413 * network base controller in UCLASS_ETH.
4415 static int mvpp2_base_probe(struct udevice *dev)
4417 struct mvpp2 *priv = dev_get_priv(dev);
4418 struct mii_dev *bus;
4423 /* Save hw-version */
4424 priv->hw_version = dev_get_driver_data(dev);
4427 * U-Boot special buffer handling:
4429 * Allocate buffer area for descs and rx_buffers. This is only
4430 * done once for all interfaces. As only one interface can
4431 * be active. Make this area DMA-safe by disabling the D-cache
4434 /* Align buffer area for descs and rx_buffers to 1MiB */
4435 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
4436 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
4437 BD_SPACE, DCACHE_OFF);
4439 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
4440 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
4442 buffer_loc.tx_descs =
4443 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
4444 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
4446 buffer_loc.rx_descs =
4447 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
4448 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
4450 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
4451 buffer_loc.bm_pool[i] =
4452 (unsigned long *)((unsigned long)bd_space + size);
4453 if (priv->hw_version == MVPP21)
4454 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
4456 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
4459 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
4460 buffer_loc.rx_buffer[i] =
4461 (unsigned long *)((unsigned long)bd_space + size);
4462 size += RX_BUFFER_SIZE;
4465 /* Save base addresses for later use */
4466 priv->base = (void *)dev_get_addr_index(dev, 0);
4467 if (IS_ERR(priv->base))
4468 return PTR_ERR(priv->base);
4470 if (priv->hw_version == MVPP21) {
4471 priv->lms_base = (void *)dev_get_addr_index(dev, 1);
4472 if (IS_ERR(priv->lms_base))
4473 return PTR_ERR(priv->lms_base);
4475 priv->iface_base = (void *)dev_get_addr_index(dev, 1);
4476 if (IS_ERR(priv->iface_base))
4477 return PTR_ERR(priv->iface_base);
4480 /* Finally create and register the MDIO bus driver */
4483 printf("Failed to allocate MDIO bus\n");
4487 bus->read = mpp2_mdio_read;
4488 bus->write = mpp2_mdio_write;
4489 snprintf(bus->name, sizeof(bus->name), dev->name);
4490 bus->priv = (void *)priv;
4493 return mdio_register(bus);
4496 static int mvpp2_base_bind(struct udevice *parent)
4498 const void *blob = gd->fdt_blob;
4499 int node = dev_of_offset(parent);
4500 struct uclass_driver *drv;
4501 struct udevice *dev;
4502 struct eth_pdata *plat;
4507 /* Lookup eth driver */
4508 drv = lists_uclass_lookup(UCLASS_ETH);
4510 puts("Cannot find eth driver\n");
4514 fdt_for_each_subnode(subnode, blob, node) {
4515 /* Skip disabled ports */
4516 if (!fdtdec_get_is_enabled(blob, subnode))
4519 plat = calloc(1, sizeof(*plat));
4523 id = fdtdec_get_int(blob, subnode, "port-id", -1);
4525 name = calloc(1, 16);
4526 sprintf(name, "mvpp2-%d", id);
4528 /* Create child device UCLASS_ETH and bind it */
4529 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
4530 dev_set_of_offset(dev, subnode);
4536 static const struct udevice_id mvpp2_ids[] = {
4538 .compatible = "marvell,armada-375-pp2",
4544 U_BOOT_DRIVER(mvpp2_base) = {
4545 .name = "mvpp2_base",
4547 .of_match = mvpp2_ids,
4548 .bind = mvpp2_base_bind,
4549 .probe = mvpp2_base_probe,
4550 .priv_auto_alloc_size = sizeof(struct mvpp2),