1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
6 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
8 * Based on the Linux version which is:
9 * Copyright (C) 2012 Marvell
11 * Rami Rosen <rosenr@marvell.com>
12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
22 #include <linux/errno.h>
26 #include <asm/arch/cpu.h>
27 #include <asm/arch/soc.h>
28 #include <linux/compat.h>
29 #include <linux/mbus.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #if !defined(CONFIG_PHYLIB)
34 # error Marvell mvneta requires PHYLIB
37 /* Some linux -> U-Boot compatibility stuff */
38 #define netdev_err(dev, fmt, args...) \
40 #define netdev_warn(dev, fmt, args...) \
42 #define netdev_info(dev, fmt, args...) \
45 #define CONFIG_NR_CPUS 1
46 #define ETH_HLEN 14 /* Total octets in header */
48 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
49 #define WRAP (2 + ETH_HLEN + 4 + 32)
51 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
53 #define MVNETA_SMI_TIMEOUT 10000
56 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
57 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
58 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
59 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
60 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
61 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
62 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
63 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
64 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
65 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
66 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
67 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
68 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
69 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
70 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
71 #define MVNETA_PORT_RX_RESET 0x1cc0
72 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
73 #define MVNETA_PHY_ADDR 0x2000
74 #define MVNETA_PHY_ADDR_MASK 0x1f
75 #define MVNETA_SMI 0x2004
76 #define MVNETA_PHY_REG_MASK 0x1f
77 /* SMI register fields */
78 #define MVNETA_SMI_DATA_OFFS 0 /* Data */
79 #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
80 #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
81 #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
82 #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
83 #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
84 #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */
85 #define MVNETA_SMI_BUSY (1 << 28) /* Busy */
86 #define MVNETA_MBUS_RETRY 0x2010
87 #define MVNETA_UNIT_INTR_CAUSE 0x2080
88 #define MVNETA_UNIT_CONTROL 0x20B0
89 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
90 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
91 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
92 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
93 #define MVNETA_WIN_SIZE_MASK (0xffff0000)
94 #define MVNETA_BASE_ADDR_ENABLE 0x2290
95 #define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
96 #define MVNETA_PORT_ACCESS_PROTECT 0x2294
97 #define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
98 #define MVNETA_PORT_CONFIG 0x2400
99 #define MVNETA_UNI_PROMISC_MODE BIT(0)
100 #define MVNETA_DEF_RXQ(q) ((q) << 1)
101 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
102 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
103 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
104 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
105 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
106 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
107 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
108 MVNETA_DEF_RXQ_ARP(q) | \
109 MVNETA_DEF_RXQ_TCP(q) | \
110 MVNETA_DEF_RXQ_UDP(q) | \
111 MVNETA_DEF_RXQ_BPDU(q) | \
112 MVNETA_TX_UNSET_ERR_SUM | \
113 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
114 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
115 #define MVNETA_MAC_ADDR_LOW 0x2414
116 #define MVNETA_MAC_ADDR_HIGH 0x2418
117 #define MVNETA_SDMA_CONFIG 0x241c
118 #define MVNETA_SDMA_BRST_SIZE_16 4
119 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
120 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
121 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
122 #define MVNETA_DESC_SWAP BIT(6)
123 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
124 #define MVNETA_PORT_STATUS 0x2444
125 #define MVNETA_TX_IN_PRGRS BIT(1)
126 #define MVNETA_TX_FIFO_EMPTY BIT(8)
127 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
128 #define MVNETA_SERDES_CFG 0x24A0
129 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
130 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
131 #define MVNETA_TYPE_PRIO 0x24bc
132 #define MVNETA_FORCE_UNI BIT(21)
133 #define MVNETA_TXQ_CMD_1 0x24e4
134 #define MVNETA_TXQ_CMD 0x2448
135 #define MVNETA_TXQ_DISABLE_SHIFT 8
136 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
137 #define MVNETA_ACC_MODE 0x2500
138 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
139 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
140 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
141 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
143 /* Exception Interrupt Port/Queue Cause register */
145 #define MVNETA_INTR_NEW_CAUSE 0x25a0
146 #define MVNETA_INTR_NEW_MASK 0x25a4
148 /* bits 0..7 = TXQ SENT, one bit per queue.
149 * bits 8..15 = RXQ OCCUP, one bit per queue.
150 * bits 16..23 = RXQ FREE, one bit per queue.
151 * bit 29 = OLD_REG_SUM, see old reg ?
152 * bit 30 = TX_ERR_SUM, one bit for 4 ports
153 * bit 31 = MISC_SUM, one bit for 4 ports
155 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
156 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
157 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
158 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
160 #define MVNETA_INTR_OLD_CAUSE 0x25a8
161 #define MVNETA_INTR_OLD_MASK 0x25ac
163 /* Data Path Port/Queue Cause Register */
164 #define MVNETA_INTR_MISC_CAUSE 0x25b0
165 #define MVNETA_INTR_MISC_MASK 0x25b4
166 #define MVNETA_INTR_ENABLE 0x25b8
168 #define MVNETA_RXQ_CMD 0x2680
169 #define MVNETA_RXQ_DISABLE_SHIFT 8
170 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
171 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
172 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
173 #define MVNETA_GMAC_CTRL_0 0x2c00
174 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
175 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
176 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
177 #define MVNETA_GMAC_CTRL_2 0x2c08
178 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
179 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
180 #define MVNETA_GMAC2_PORT_RESET BIT(6)
181 #define MVNETA_GMAC_STATUS 0x2c10
182 #define MVNETA_GMAC_LINK_UP BIT(0)
183 #define MVNETA_GMAC_SPEED_1000 BIT(1)
184 #define MVNETA_GMAC_SPEED_100 BIT(2)
185 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
186 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
187 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
188 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
189 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
190 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
191 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
192 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
193 #define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1))
194 #define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
195 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
196 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
197 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
198 #define MVNETA_GMAC_SET_FC_EN BIT(8)
199 #define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
200 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
201 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
202 #define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
203 #define MVNETA_MIB_COUNTERS_BASE 0x3080
204 #define MVNETA_MIB_LATE_COLLISION 0x7c
205 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
206 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
207 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
208 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
209 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
210 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
211 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
212 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
213 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
214 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
215 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
216 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
217 #define MVNETA_PORT_TX_RESET 0x3cf0
218 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
219 #define MVNETA_TX_MTU 0x3e0c
220 #define MVNETA_TX_TOKEN_SIZE 0x3e14
221 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
222 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
223 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
225 /* Descriptor ring Macros */
226 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
227 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
229 /* Various constants */
232 #define MVNETA_TXDONE_COAL_PKTS 16
233 #define MVNETA_RX_COAL_PKTS 32
234 #define MVNETA_RX_COAL_USEC 100
236 /* The two bytes Marvell header. Either contains a special value used
237 * by Marvell switches when a specific hardware mode is enabled (not
238 * supported by this driver) or is filled automatically by zeroes on
239 * the RX side. Those two bytes being at the front of the Ethernet
240 * header, they allow to have the IP header aligned on a 4 bytes
241 * boundary automatically: the hardware skips those two bytes on its
244 #define MVNETA_MH_SIZE 2
246 #define MVNETA_VLAN_TAG_LEN 4
248 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
249 #define MVNETA_TX_CSUM_MAX_SIZE 9800
250 #define MVNETA_ACC_MODE_EXT 1
252 /* Timeout constants */
253 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
254 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
255 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
257 #define MVNETA_TX_MTU_MAX 0x3ffff
259 /* Max number of Rx descriptors */
260 #define MVNETA_MAX_RXD 16
262 /* Max number of Tx descriptors */
263 #define MVNETA_MAX_TXD 16
265 /* descriptor aligned size */
266 #define MVNETA_DESC_ALIGNED_SIZE 32
270 struct mvneta_rx_queue *rxqs;
271 struct mvneta_tx_queue *txqs;
277 phy_interface_t phy_interface;
284 struct phy_device *phydev;
288 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
289 * layout of the transmit and reception DMA descriptors, and their
290 * layout is therefore defined by the hardware design
293 #define MVNETA_TX_L3_OFF_SHIFT 0
294 #define MVNETA_TX_IP_HLEN_SHIFT 8
295 #define MVNETA_TX_L4_UDP BIT(16)
296 #define MVNETA_TX_L3_IP6 BIT(17)
297 #define MVNETA_TXD_IP_CSUM BIT(18)
298 #define MVNETA_TXD_Z_PAD BIT(19)
299 #define MVNETA_TXD_L_DESC BIT(20)
300 #define MVNETA_TXD_F_DESC BIT(21)
301 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
302 MVNETA_TXD_L_DESC | \
304 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
305 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
307 #define MVNETA_RXD_ERR_CRC 0x0
308 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
309 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
310 #define MVNETA_RXD_ERR_LEN BIT(18)
311 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
312 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
313 #define MVNETA_RXD_L3_IP4 BIT(25)
314 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
315 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
317 struct mvneta_tx_desc {
318 u32 command; /* Options used by HW for packet transmitting.*/
319 u16 reserverd1; /* csum_l4 (for future use) */
320 u16 data_size; /* Data size of transmitted packet in bytes */
321 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
322 u32 reserved2; /* hw_cmd - (for future use, PMT) */
323 u32 reserved3[4]; /* Reserved - (for future use) */
326 struct mvneta_rx_desc {
327 u32 status; /* Info about received packet */
328 u16 reserved1; /* pnc_info - (for future use, PnC) */
329 u16 data_size; /* Size of received packet in bytes */
331 u32 buf_phys_addr; /* Physical address of the buffer */
332 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
334 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
335 u16 reserved3; /* prefetch_cmd, for future use */
336 u16 reserved4; /* csum_l4 - (for future use, PnC) */
338 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
339 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
342 struct mvneta_tx_queue {
343 /* Number of this TX queue, in the range 0-7 */
346 /* Number of TX DMA descriptors in the descriptor ring */
349 /* Index of last TX DMA descriptor that was inserted */
352 /* Index of the TX DMA descriptor to be cleaned up */
355 /* Virtual address of the TX DMA descriptors array */
356 struct mvneta_tx_desc *descs;
358 /* DMA address of the TX DMA descriptors array */
359 dma_addr_t descs_phys;
361 /* Index of the last TX DMA descriptor */
364 /* Index of the next TX DMA descriptor to process */
365 int next_desc_to_proc;
368 struct mvneta_rx_queue {
369 /* rx queue number, in the range 0-7 */
372 /* num of rx descriptors in the rx descriptor ring */
375 /* Virtual address of the RX DMA descriptors array */
376 struct mvneta_rx_desc *descs;
378 /* DMA address of the RX DMA descriptors array */
379 dma_addr_t descs_phys;
381 /* Index of the last RX DMA descriptor */
384 /* Index of the next RX DMA descriptor to process */
385 int next_desc_to_proc;
388 /* U-Boot doesn't use the queues, so set the number to 1 */
389 static int rxq_number = 1;
390 static int txq_number = 1;
393 struct buffer_location {
394 struct mvneta_tx_desc *tx_descs;
395 struct mvneta_rx_desc *rx_descs;
400 * All 4 interfaces use the same global buffer, since only one interface
401 * can be enabled at once
403 static struct buffer_location buffer_loc;
406 * Page table entries are set to 1MB, or multiples of 1MB
407 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
409 #define BD_SPACE (1 << 20)
412 * Dummy implementation that can be overwritten by a board
415 __weak int board_network_enable(struct mii_dev *bus)
420 /* Utility/helper methods */
422 /* Write helper method */
423 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
425 writel(data, pp->base + offset);
428 /* Read helper method */
429 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
431 return readl(pp->base + offset);
434 /* Clear all MIB counters */
435 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
439 /* Perform dummy reads from MIB counters */
440 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
441 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
444 /* Rx descriptors helper methods */
446 /* Checks whether the RX descriptor having this status is both the first
447 * and the last descriptor for the RX packet. Each RX packet is currently
448 * received through a single RX descriptor, so not having each RX
449 * descriptor with its first and last bits set is an error
451 static int mvneta_rxq_desc_is_first_last(u32 status)
453 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
454 MVNETA_RXD_FIRST_LAST_DESC;
457 /* Add number of descriptors ready to receive new packets */
458 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
459 struct mvneta_rx_queue *rxq,
462 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
465 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
466 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
467 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
468 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
469 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
472 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
473 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
476 /* Get number of RX descriptors occupied by received packets */
477 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
478 struct mvneta_rx_queue *rxq)
482 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
483 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
486 /* Update num of rx desc called upon return from rx path or
487 * from mvneta_rxq_drop_pkts().
489 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
490 struct mvneta_rx_queue *rxq,
491 int rx_done, int rx_filled)
495 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
497 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
498 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
502 /* Only 255 descriptors can be added at once */
503 while ((rx_done > 0) || (rx_filled > 0)) {
504 if (rx_done <= 0xff) {
511 if (rx_filled <= 0xff) {
512 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
515 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
518 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
522 /* Get pointer to next RX descriptor to be processed by SW */
523 static struct mvneta_rx_desc *
524 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
526 int rx_desc = rxq->next_desc_to_proc;
528 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
529 return rxq->descs + rx_desc;
532 /* Tx descriptors helper methods */
534 /* Update HW with number of TX descriptors to be sent */
535 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
536 struct mvneta_tx_queue *txq,
541 /* Only 255 descriptors can be added at once ; Assume caller
542 * process TX descriptors in quanta less than 256
545 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
548 /* Get pointer to next TX descriptor to be processed (send) by HW */
549 static struct mvneta_tx_desc *
550 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
552 int tx_desc = txq->next_desc_to_proc;
554 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
555 return txq->descs + tx_desc;
558 /* Set rxq buf size */
559 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
560 struct mvneta_rx_queue *rxq,
565 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
567 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
568 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
570 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
573 static int mvneta_port_is_fixed_link(struct mvneta_port *pp)
575 /* phy_addr is set to invalid value for fixed link */
576 return pp->phyaddr > PHY_MAX_ADDR;
580 /* Start the Ethernet port RX and TX activity */
581 static void mvneta_port_up(struct mvneta_port *pp)
586 /* Enable all initialized TXs. */
587 mvneta_mib_counters_clear(pp);
589 for (queue = 0; queue < txq_number; queue++) {
590 struct mvneta_tx_queue *txq = &pp->txqs[queue];
591 if (txq->descs != NULL)
592 q_map |= (1 << queue);
594 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
596 /* Enable all initialized RXQs. */
598 for (queue = 0; queue < rxq_number; queue++) {
599 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
600 if (rxq->descs != NULL)
601 q_map |= (1 << queue);
603 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
606 /* Stop the Ethernet port activity */
607 static void mvneta_port_down(struct mvneta_port *pp)
612 /* Stop Rx port activity. Check port Rx activity. */
613 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
615 /* Issue stop command for active channels only */
617 mvreg_write(pp, MVNETA_RXQ_CMD,
618 val << MVNETA_RXQ_DISABLE_SHIFT);
620 /* Wait for all Rx activity to terminate. */
623 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
625 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
631 val = mvreg_read(pp, MVNETA_RXQ_CMD);
632 } while (val & 0xff);
634 /* Stop Tx port activity. Check port Tx activity. Issue stop
635 * command for active channels only
637 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
640 mvreg_write(pp, MVNETA_TXQ_CMD,
641 (val << MVNETA_TXQ_DISABLE_SHIFT));
643 /* Wait for all Tx activity to terminate. */
646 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
648 "TIMEOUT for TX stopped status=0x%08x\n",
654 /* Check TX Command reg that all Txqs are stopped */
655 val = mvreg_read(pp, MVNETA_TXQ_CMD);
657 } while (val & 0xff);
659 /* Double check to verify that TX FIFO is empty */
662 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
664 "TX FIFO empty timeout status=0x08%x\n",
670 val = mvreg_read(pp, MVNETA_PORT_STATUS);
671 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
672 (val & MVNETA_TX_IN_PRGRS));
677 /* Enable the port by setting the port enable bit of the MAC control register */
678 static void mvneta_port_enable(struct mvneta_port *pp)
683 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
684 val |= MVNETA_GMAC0_PORT_ENABLE;
685 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
688 /* Disable the port and wait for about 200 usec before retuning */
689 static void mvneta_port_disable(struct mvneta_port *pp)
693 /* Reset the Enable bit in the Serial Control Register */
694 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
695 val &= ~MVNETA_GMAC0_PORT_ENABLE;
696 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
701 /* Multicast tables methods */
703 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
704 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
712 val = 0x1 | (queue << 1);
713 val |= (val << 24) | (val << 16) | (val << 8);
716 for (offset = 0; offset <= 0xc; offset += 4)
717 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
720 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
721 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
729 val = 0x1 | (queue << 1);
730 val |= (val << 24) | (val << 16) | (val << 8);
733 for (offset = 0; offset <= 0xfc; offset += 4)
734 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
737 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
738 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
744 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
747 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
748 val = 0x1 | (queue << 1);
749 val |= (val << 24) | (val << 16) | (val << 8);
752 for (offset = 0; offset <= 0xfc; offset += 4)
753 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
756 /* This method sets defaults to the NETA port:
757 * Clears interrupt Cause and Mask registers.
758 * Clears all MAC tables.
759 * Sets defaults to all registers.
760 * Resets RX and TX descriptor rings.
762 * This method can be called after mvneta_port_down() to return the port
763 * settings to defaults.
765 static void mvneta_defaults_set(struct mvneta_port *pp)
771 /* Clear all Cause registers */
772 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
773 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
774 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
776 /* Mask all interrupts */
777 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
778 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
779 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
780 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
782 /* Enable MBUS Retry bit16 */
783 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
785 /* Set CPU queue access map - all CPUs have access to all RX
786 * queues and to all TX queues
788 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
789 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
790 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
791 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
793 /* Reset RX and TX DMAs */
794 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
795 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
797 /* Disable Legacy WRR, Disable EJP, Release from reset */
798 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
799 for (queue = 0; queue < txq_number; queue++) {
800 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
801 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
804 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
805 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
807 /* Set Port Acceleration Mode */
808 val = MVNETA_ACC_MODE_EXT;
809 mvreg_write(pp, MVNETA_ACC_MODE, val);
811 /* Update val of portCfg register accordingly with all RxQueue types */
812 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
813 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
816 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
817 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
819 /* Build PORT_SDMA_CONFIG_REG */
822 /* Default burst size */
823 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
824 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
825 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
827 /* Assign port SDMA configuration */
828 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
830 /* Enable PHY polling in hardware if not in fixed-link mode */
831 if (!mvneta_port_is_fixed_link(pp)) {
832 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
833 val |= MVNETA_PHY_POLLING_ENABLE;
834 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
837 mvneta_set_ucast_table(pp, -1);
838 mvneta_set_special_mcast_table(pp, -1);
839 mvneta_set_other_mcast_table(pp, -1);
842 /* Set unicast address */
843 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
846 unsigned int unicast_reg;
847 unsigned int tbl_offset;
848 unsigned int reg_offset;
850 /* Locate the Unicast table entry */
851 last_nibble = (0xf & last_nibble);
853 /* offset from unicast tbl base */
854 tbl_offset = (last_nibble / 4) * 4;
856 /* offset within the above reg */
857 reg_offset = last_nibble % 4;
859 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
862 /* Clear accepts frame bit at specified unicast DA tbl entry */
863 unicast_reg &= ~(0xff << (8 * reg_offset));
865 unicast_reg &= ~(0xff << (8 * reg_offset));
866 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
869 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
872 /* Set mac address */
873 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
880 mac_l = (addr[4] << 8) | (addr[5]);
881 mac_h = (addr[0] << 24) | (addr[1] << 16) |
882 (addr[2] << 8) | (addr[3] << 0);
884 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
885 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
888 /* Accept frames of this address */
889 mvneta_set_ucast_addr(pp, addr[5], queue);
892 static int mvneta_write_hwaddr(struct udevice *dev)
894 mvneta_mac_addr_set(dev_get_priv(dev),
895 ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr,
901 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
902 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
903 u32 phys_addr, u32 cookie)
905 rx_desc->buf_cookie = cookie;
906 rx_desc->buf_phys_addr = phys_addr;
909 /* Decrement sent descriptors counter */
910 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
911 struct mvneta_tx_queue *txq,
916 /* Only 255 TX descriptors can be updated at once */
917 while (sent_desc > 0xff) {
918 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
919 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
920 sent_desc = sent_desc - 0xff;
923 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
924 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
927 /* Get number of TX descriptors already sent by HW */
928 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
929 struct mvneta_tx_queue *txq)
934 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
935 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
936 MVNETA_TXQ_SENT_DESC_SHIFT;
941 /* Display more error info */
942 static void mvneta_rx_error(struct mvneta_port *pp,
943 struct mvneta_rx_desc *rx_desc)
945 u32 status = rx_desc->status;
947 if (!mvneta_rxq_desc_is_first_last(status)) {
949 "bad rx status %08x (buffer oversize), size=%d\n",
950 status, rx_desc->data_size);
954 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
955 case MVNETA_RXD_ERR_CRC:
956 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
957 status, rx_desc->data_size);
959 case MVNETA_RXD_ERR_OVERRUN:
960 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
961 status, rx_desc->data_size);
963 case MVNETA_RXD_ERR_LEN:
964 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
965 status, rx_desc->data_size);
967 case MVNETA_RXD_ERR_RESOURCE:
968 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
969 status, rx_desc->data_size);
974 static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
977 return &pp->rxqs[rxq];
981 /* Drop packets received by the RXQ and free buffers */
982 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
983 struct mvneta_rx_queue *rxq)
987 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
989 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
992 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
993 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
998 for (i = 0; i < num; i++) {
1001 /* U-Boot special: Fill in the rx buffer addresses */
1002 addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
1003 mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
1006 /* Add this number of RX descriptors as non occupied (ready to
1009 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
1014 /* Rx/Tx queue initialization/cleanup methods */
1016 /* Create a specified RX queue */
1017 static int mvneta_rxq_init(struct mvneta_port *pp,
1018 struct mvneta_rx_queue *rxq)
1021 rxq->size = pp->rx_ring_size;
1023 /* Allocate memory for RX descriptors */
1024 rxq->descs_phys = (dma_addr_t)rxq->descs;
1025 if (rxq->descs == NULL)
1028 rxq->last_desc = rxq->size - 1;
1030 /* Set Rx descriptors queue starting address */
1031 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
1032 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
1034 /* Fill RXQ with buffers from RX pool */
1035 mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
1036 mvneta_rxq_fill(pp, rxq, rxq->size);
1041 /* Cleanup Rx queue */
1042 static void mvneta_rxq_deinit(struct mvneta_port *pp,
1043 struct mvneta_rx_queue *rxq)
1045 mvneta_rxq_drop_pkts(pp, rxq);
1049 rxq->next_desc_to_proc = 0;
1050 rxq->descs_phys = 0;
1053 /* Create and initialize a tx queue */
1054 static int mvneta_txq_init(struct mvneta_port *pp,
1055 struct mvneta_tx_queue *txq)
1057 txq->size = pp->tx_ring_size;
1059 /* Allocate memory for TX descriptors */
1060 txq->descs_phys = (dma_addr_t)txq->descs;
1061 if (txq->descs == NULL)
1064 txq->last_desc = txq->size - 1;
1066 /* Set maximum bandwidth for enabled TXQs */
1067 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
1068 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
1070 /* Set Tx descriptors queue starting address */
1071 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
1072 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
1077 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
1078 static void mvneta_txq_deinit(struct mvneta_port *pp,
1079 struct mvneta_tx_queue *txq)
1083 txq->next_desc_to_proc = 0;
1084 txq->descs_phys = 0;
1086 /* Set minimum bandwidth for disabled TXQs */
1087 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
1088 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
1090 /* Set Tx descriptors queue starting address and size */
1091 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
1092 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
1095 /* Cleanup all Tx queues */
1096 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
1100 for (queue = 0; queue < txq_number; queue++)
1101 mvneta_txq_deinit(pp, &pp->txqs[queue]);
1104 /* Cleanup all Rx queues */
1105 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
1109 for (queue = 0; queue < rxq_number; queue++)
1110 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
1114 /* Init all Rx queues */
1115 static int mvneta_setup_rxqs(struct mvneta_port *pp)
1119 for (queue = 0; queue < rxq_number; queue++) {
1120 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
1122 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
1124 mvneta_cleanup_rxqs(pp);
1132 /* Init all tx queues */
1133 static int mvneta_setup_txqs(struct mvneta_port *pp)
1137 for (queue = 0; queue < txq_number; queue++) {
1138 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
1140 netdev_err(pp->dev, "%s: can't create txq=%d\n",
1142 mvneta_cleanup_txqs(pp);
1150 static void mvneta_start_dev(struct mvneta_port *pp)
1152 /* start the Rx/Tx activity */
1153 mvneta_port_enable(pp);
1156 static void mvneta_adjust_link(struct udevice *dev)
1158 struct mvneta_port *pp = dev_get_priv(dev);
1159 struct phy_device *phydev = pp->phydev;
1160 int status_change = 0;
1162 if (mvneta_port_is_fixed_link(pp)) {
1163 debug("Using fixed link, skip link adjust\n");
1168 if ((pp->speed != phydev->speed) ||
1169 (pp->duplex != phydev->duplex)) {
1172 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1173 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
1174 MVNETA_GMAC_CONFIG_GMII_SPEED |
1175 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
1176 MVNETA_GMAC_AN_SPEED_EN |
1177 MVNETA_GMAC_AN_DUPLEX_EN);
1180 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
1182 if (phydev->speed == SPEED_1000)
1183 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1185 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
1187 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1189 pp->duplex = phydev->duplex;
1190 pp->speed = phydev->speed;
1194 if (phydev->link != pp->link) {
1195 if (!phydev->link) {
1200 pp->link = phydev->link;
1204 if (status_change) {
1206 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1207 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
1208 MVNETA_GMAC_FORCE_LINK_DOWN);
1209 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1212 mvneta_port_down(pp);
1217 static int mvneta_open(struct udevice *dev)
1219 struct mvneta_port *pp = dev_get_priv(dev);
1222 ret = mvneta_setup_rxqs(pp);
1226 ret = mvneta_setup_txqs(pp);
1230 mvneta_adjust_link(dev);
1232 mvneta_start_dev(pp);
1238 static int mvneta_init2(struct mvneta_port *pp)
1243 mvneta_port_disable(pp);
1245 /* Set port default values */
1246 mvneta_defaults_set(pp);
1248 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
1253 /* U-Boot special: use preallocated area */
1254 pp->txqs[0].descs = buffer_loc.tx_descs;
1256 /* Initialize TX descriptor rings */
1257 for (queue = 0; queue < txq_number; queue++) {
1258 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1260 txq->size = pp->tx_ring_size;
1263 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
1270 /* U-Boot special: use preallocated area */
1271 pp->rxqs[0].descs = buffer_loc.rx_descs;
1273 /* Create Rx descriptor rings */
1274 for (queue = 0; queue < rxq_number; queue++) {
1275 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1277 rxq->size = pp->rx_ring_size;
1283 /* platform glue : initialize decoding windows */
1286 * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
1287 * First layer is: GbE Address window that resides inside the GBE unit,
1288 * Second layer is: Fabric address window which is located in the NIC400
1290 * To simplify the address decode configuration for Armada3700, we bypass the
1291 * first layer of GBE decode window by setting the first window to 4GB.
1293 static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
1296 * Set window size to 4GB, to bypass GBE address decode, leave the
1297 * work to MBUS decode window
1299 mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
1301 /* Enable GBE address decode window 0 by set bit 0 to 0 */
1302 clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
1303 MVNETA_BASE_ADDR_ENABLE_BIT);
1305 /* Set GBE address decode window 0 to full Access (read or write) */
1306 setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
1307 MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
1310 static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
1312 const struct mbus_dram_target_info *dram;
1317 dram = mvebu_mbus_dram_info();
1318 for (i = 0; i < 6; i++) {
1319 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1320 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1323 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1329 for (i = 0; i < dram->num_cs; i++) {
1330 const struct mbus_dram_window *cs = dram->cs + i;
1331 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
1332 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
1334 mvreg_write(pp, MVNETA_WIN_SIZE(i),
1335 (cs->size - 1) & 0xffff0000);
1337 win_enable &= ~(1 << i);
1338 win_protect |= 3 << (2 * i);
1341 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1344 /* Power up the port */
1345 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
1349 /* MAC Cause register should be cleared */
1350 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
1352 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1354 /* Even though it might look weird, when we're configured in
1355 * SGMII or QSGMII mode, the RGMII bit needs to be set.
1358 case PHY_INTERFACE_MODE_QSGMII:
1359 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
1360 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1362 case PHY_INTERFACE_MODE_SGMII:
1363 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
1364 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1366 case PHY_INTERFACE_MODE_RGMII:
1367 case PHY_INTERFACE_MODE_RGMII_ID:
1368 ctrl |= MVNETA_GMAC2_PORT_RGMII;
1374 /* Cancel Port Reset */
1375 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
1376 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
1378 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
1379 MVNETA_GMAC2_PORT_RESET) != 0)
1385 /* Device initialization routine */
1386 static int mvneta_init(struct udevice *dev)
1388 struct eth_pdata *pdata = dev_get_platdata(dev);
1389 struct mvneta_port *pp = dev_get_priv(dev);
1392 pp->tx_ring_size = MVNETA_MAX_TXD;
1393 pp->rx_ring_size = MVNETA_MAX_RXD;
1395 err = mvneta_init2(pp);
1397 dev_err(&pdev->dev, "can't init eth hal\n");
1401 mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
1403 err = mvneta_port_power_up(pp, pp->phy_interface);
1405 dev_err(&pdev->dev, "can't power up port\n");
1409 /* Call open() now as it needs to be done before runing send() */
1415 /* U-Boot only functions follow here */
1417 /* SMI / MDIO functions */
1419 static int smi_wait_ready(struct mvneta_port *pp)
1421 u32 timeout = MVNETA_SMI_TIMEOUT;
1424 /* wait till the SMI is not busy */
1426 /* read smi register */
1427 smi_reg = mvreg_read(pp, MVNETA_SMI);
1428 if (timeout-- == 0) {
1429 printf("Error: SMI busy timeout\n");
1432 } while (smi_reg & MVNETA_SMI_BUSY);
1438 * mvneta_mdio_read - miiphy_read callback function.
1440 * Returns 16bit phy register value, or 0xffff on error
1442 static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
1444 struct mvneta_port *pp = bus->priv;
1448 /* check parameters */
1449 if (addr > MVNETA_PHY_ADDR_MASK) {
1450 printf("Error: Invalid PHY address %d\n", addr);
1454 if (reg > MVNETA_PHY_REG_MASK) {
1455 printf("Err: Invalid register offset %d\n", reg);
1459 /* wait till the SMI is not busy */
1460 if (smi_wait_ready(pp) < 0)
1463 /* fill the phy address and regiser offset and read opcode */
1464 smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1465 | (reg << MVNETA_SMI_REG_ADDR_OFFS)
1466 | MVNETA_SMI_OPCODE_READ;
1468 /* write the smi register */
1469 mvreg_write(pp, MVNETA_SMI, smi_reg);
1471 /* wait till read value is ready */
1472 timeout = MVNETA_SMI_TIMEOUT;
1475 /* read smi register */
1476 smi_reg = mvreg_read(pp, MVNETA_SMI);
1477 if (timeout-- == 0) {
1478 printf("Err: SMI read ready timeout\n");
1481 } while (!(smi_reg & MVNETA_SMI_READ_VALID));
1483 /* Wait for the data to update in the SMI register */
1484 for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
1487 return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
1491 * mvneta_mdio_write - miiphy_write callback function.
1493 * Returns 0 if write succeed, -EINVAL on bad parameters
1496 static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
1499 struct mvneta_port *pp = bus->priv;
1502 /* check parameters */
1503 if (addr > MVNETA_PHY_ADDR_MASK) {
1504 printf("Error: Invalid PHY address %d\n", addr);
1508 if (reg > MVNETA_PHY_REG_MASK) {
1509 printf("Err: Invalid register offset %d\n", reg);
1513 /* wait till the SMI is not busy */
1514 if (smi_wait_ready(pp) < 0)
1517 /* fill the phy addr and reg offset and write opcode and data */
1518 smi_reg = value << MVNETA_SMI_DATA_OFFS;
1519 smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1520 | (reg << MVNETA_SMI_REG_ADDR_OFFS);
1521 smi_reg &= ~MVNETA_SMI_OPCODE_READ;
1523 /* write the smi register */
1524 mvreg_write(pp, MVNETA_SMI, smi_reg);
1529 static int mvneta_start(struct udevice *dev)
1531 struct mvneta_port *pp = dev_get_priv(dev);
1532 struct phy_device *phydev;
1534 mvneta_port_power_up(pp, pp->phy_interface);
1536 if (!pp->init || pp->link == 0) {
1537 if (mvneta_port_is_fixed_link(pp)) {
1544 val = MVNETA_GMAC_FORCE_LINK_UP |
1545 MVNETA_GMAC_IB_BYPASS_AN_EN |
1546 MVNETA_GMAC_SET_FC_EN |
1547 MVNETA_GMAC_ADVERT_FC_EN |
1548 MVNETA_GMAC_SAMPLE_TX_CFG_EN;
1551 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
1553 if (pp->speed == SPEED_1000)
1554 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1555 else if (pp->speed == SPEED_100)
1556 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
1558 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1560 /* Set phy address of the port */
1561 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
1563 phydev = phy_connect(pp->bus, pp->phyaddr, dev,
1566 pp->phydev = phydev;
1568 phy_startup(phydev);
1569 if (!phydev->link) {
1570 printf("%s: No link.\n", phydev->dev->name);
1574 /* Full init on first call */
1581 /* Upon all following calls, this is enough */
1583 mvneta_port_enable(pp);
1588 static int mvneta_send(struct udevice *dev, void *packet, int length)
1590 struct mvneta_port *pp = dev_get_priv(dev);
1591 struct mvneta_tx_queue *txq = &pp->txqs[0];
1592 struct mvneta_tx_desc *tx_desc;
1596 /* Get a descriptor for the first part of the packet */
1597 tx_desc = mvneta_txq_next_desc_get(txq);
1599 tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
1600 tx_desc->data_size = length;
1601 flush_dcache_range((ulong)packet,
1602 (ulong)packet + ALIGN(length, PKTALIGN));
1604 /* First and Last descriptor */
1605 tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
1606 mvneta_txq_pend_desc_add(pp, txq, 1);
1608 /* Wait for packet to be sent (queue might help with speed here) */
1609 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1610 while (!sent_desc) {
1611 if (timeout++ > 10000) {
1612 printf("timeout: packet not sent\n");
1615 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1618 /* txDone has increased - hw sent packet */
1619 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1624 static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
1626 struct mvneta_port *pp = dev_get_priv(dev);
1628 struct mvneta_rx_queue *rxq;
1632 rxq = mvneta_rxq_handle_get(pp, rxq_def);
1633 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1636 struct mvneta_rx_desc *rx_desc;
1637 unsigned char *data;
1641 * No cache invalidation needed here, since the desc's are
1642 * located in a uncached memory region
1644 rx_desc = mvneta_rxq_next_desc_get(rxq);
1646 rx_status = rx_desc->status;
1647 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1648 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1649 mvneta_rx_error(pp, rx_desc);
1650 /* leave the descriptor untouched */
1654 /* 2 bytes for marvell header. 4 bytes for crc */
1655 rx_bytes = rx_desc->data_size - 6;
1657 /* give packet to stack - skip on first 2 bytes */
1658 data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
1660 * No cache invalidation needed here, since the rx_buffer's are
1661 * located in a uncached memory region
1666 * Only mark one descriptor as free
1667 * since only one was processed
1669 mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
1675 static int mvneta_probe(struct udevice *dev)
1677 struct eth_pdata *pdata = dev_get_platdata(dev);
1678 struct mvneta_port *pp = dev_get_priv(dev);
1679 void *blob = (void *)gd->fdt_blob;
1680 int node = dev_of_offset(dev);
1681 struct mii_dev *bus;
1688 * Allocate buffer area for descs and rx_buffers. This is only
1689 * done once for all interfaces. As only one interface can
1690 * be active. Make this area DMA safe by disabling the D-cache
1692 if (!buffer_loc.tx_descs) {
1693 /* Align buffer area for descs and rx_buffers to 1MiB */
1694 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
1695 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
1697 buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
1698 buffer_loc.rx_descs = (struct mvneta_rx_desc *)
1699 ((phys_addr_t)bd_space +
1700 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc));
1701 buffer_loc.rx_buffers = (phys_addr_t)
1703 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) +
1704 MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
1707 pp->base = (void __iomem *)pdata->iobase;
1709 /* Configure MBUS address windows */
1710 if (device_is_compatible(dev, "marvell,armada-3700-neta"))
1711 mvneta_bypass_mbus_windows(pp);
1713 mvneta_conf_mbus_windows(pp);
1715 /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
1716 pp->phy_interface = pdata->phy_interface;
1718 /* fetch 'fixed-link' property from 'neta' node */
1719 fl_node = fdt_subnode_offset(blob, node, "fixed-link");
1720 if (fl_node != -FDT_ERR_NOTFOUND) {
1721 /* set phy_addr to invalid value for fixed link */
1722 pp->phyaddr = PHY_MAX_ADDR + 1;
1723 pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
1724 pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
1726 /* Now read phyaddr from DT */
1727 addr = fdtdec_get_int(blob, node, "phy", 0);
1728 addr = fdt_node_offset_by_phandle(blob, addr);
1729 pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
1734 printf("Failed to allocate MDIO bus\n");
1738 bus->read = mvneta_mdio_read;
1739 bus->write = mvneta_mdio_write;
1740 snprintf(bus->name, sizeof(bus->name), dev->name);
1741 bus->priv = (void *)pp;
1744 ret = mdio_register(bus);
1748 return board_network_enable(bus);
1751 static void mvneta_stop(struct udevice *dev)
1753 struct mvneta_port *pp = dev_get_priv(dev);
1755 mvneta_port_down(pp);
1756 mvneta_port_disable(pp);
1759 static const struct eth_ops mvneta_ops = {
1760 .start = mvneta_start,
1761 .send = mvneta_send,
1762 .recv = mvneta_recv,
1763 .stop = mvneta_stop,
1764 .write_hwaddr = mvneta_write_hwaddr,
1767 static int mvneta_ofdata_to_platdata(struct udevice *dev)
1769 struct eth_pdata *pdata = dev_get_platdata(dev);
1770 const char *phy_mode;
1772 pdata->iobase = devfdt_get_addr(dev);
1774 /* Get phy-mode / phy_interface from DT */
1775 pdata->phy_interface = -1;
1776 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1779 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1780 if (pdata->phy_interface == -1) {
1781 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1788 static const struct udevice_id mvneta_ids[] = {
1789 { .compatible = "marvell,armada-370-neta" },
1790 { .compatible = "marvell,armada-xp-neta" },
1791 { .compatible = "marvell,armada-3700-neta" },
1795 U_BOOT_DRIVER(mvneta) = {
1798 .of_match = mvneta_ids,
1799 .ofdata_to_platdata = mvneta_ofdata_to_platdata,
1800 .probe = mvneta_probe,
1802 .priv_auto_alloc_size = sizeof(struct mvneta_port),
1803 .platdata_auto_alloc_size = sizeof(struct eth_pdata),