1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
8 * Ingo Assmus <ingo.assmus@keymile.com>
10 * based on - Driver for MV64360X ethernet ports
11 * Copyright (C) 2002 rabeeh@galileo.co.il
19 #include <linux/errno.h>
20 #include <asm/types.h>
21 #include <asm/system.h>
22 #include <asm/byteorder.h>
23 #include <asm/arch/cpu.h>
25 #if defined(CONFIG_KIRKWOOD)
26 #include <asm/arch/soc.h>
27 #elif defined(CONFIG_ORION5X)
28 #include <asm/arch/orion5x.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #ifndef CONFIG_MVGBE_PORTS
36 # define CONFIG_MVGBE_PORTS {0, 0}
39 #define MV_PHY_ADR_REQUEST 0xee
40 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
42 #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
44 * smi_reg_read - miiphy_read callback function.
46 * Returns 16bit phy register value, or 0xffff on error
48 static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
52 struct eth_device *dev = eth_get_dev_by_name(bus->name);
53 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
54 struct mvgbe_registers *regs = dmvgbe->regs;
58 /* Phyadr read request */
59 if (phy_adr == MV_PHY_ADR_REQUEST &&
60 reg_ofs == MV_PHY_ADR_REQUEST) {
62 data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
65 /* check parameters */
66 if (phy_adr > PHYADR_MASK) {
67 printf("Err..(%s) Invalid PHY address %d\n",
71 if (reg_ofs > PHYREG_MASK) {
72 printf("Err..(%s) Invalid register offset %d\n",
77 timeout = MVGBE_PHY_SMI_TIMEOUT;
78 /* wait till the SMI is not busy */
80 /* read smi register */
81 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
83 printf("Err..(%s) SMI busy timeout\n", __func__);
86 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
88 /* fill the phy address and regiser offset and read opcode */
89 smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
90 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
91 | MVGBE_PHY_SMI_OPCODE_READ;
93 /* write the smi register */
94 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
96 /*wait till read value is ready */
97 timeout = MVGBE_PHY_SMI_TIMEOUT;
100 /* read smi register */
101 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
102 if (timeout-- == 0) {
103 printf("Err..(%s) SMI read ready timeout\n",
107 } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
109 /* Wait for the data to update in the SMI register */
110 for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
113 data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
115 debug("%s:(adr %d, off %d) value= %04x\n", __func__, phy_adr, reg_ofs,
122 * smi_reg_write - imiiphy_write callback function.
124 * Returns 0 if write succeed, -EINVAL on bad parameters
127 static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
128 int reg_ofs, u16 data)
130 struct eth_device *dev = eth_get_dev_by_name(bus->name);
131 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
132 struct mvgbe_registers *regs = dmvgbe->regs;
136 /* Phyadr write request*/
137 if (phy_adr == MV_PHY_ADR_REQUEST &&
138 reg_ofs == MV_PHY_ADR_REQUEST) {
139 MVGBE_REG_WR(regs->phyadr, data);
143 /* check parameters */
144 if (phy_adr > PHYADR_MASK) {
145 printf("Err..(%s) Invalid phy address\n", __func__);
148 if (reg_ofs > PHYREG_MASK) {
149 printf("Err..(%s) Invalid register offset\n", __func__);
153 /* wait till the SMI is not busy */
154 timeout = MVGBE_PHY_SMI_TIMEOUT;
156 /* read smi register */
157 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
158 if (timeout-- == 0) {
159 printf("Err..(%s) SMI busy timeout\n", __func__);
162 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
164 /* fill the phy addr and reg offset and write opcode and data */
165 smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
166 smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
167 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
168 smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
170 /* write the smi register */
171 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
177 /* Stop and checks all queues */
178 static void stop_queue(u32 * qreg)
182 reg_data = readl(qreg);
184 if (reg_data & 0xFF) {
185 /* Issue stop command for active channels only */
186 writel((reg_data << 8), qreg);
188 /* Wait for all queue activity to terminate. */
191 * Check port cause register that all queues
194 reg_data = readl(qreg);
196 while (reg_data & 0xFF);
201 * set_access_control - Config address decode parameters for Ethernet unit
203 * This function configures the address decode parameters for the Gigabit
204 * Ethernet Controller according the given parameters struct.
206 * @regs Register struct pointer.
207 * @param Address decode parameter struct.
209 static void set_access_control(struct mvgbe_registers *regs,
210 struct mvgbe_winparam *param)
214 /* Set access control register */
215 access_prot_reg = MVGBE_REG_RD(regs->epap);
216 /* clear window permission */
217 access_prot_reg &= (~(3 << (param->win * 2)));
218 access_prot_reg |= (param->access_ctrl << (param->win * 2));
219 MVGBE_REG_WR(regs->epap, access_prot_reg);
221 /* Set window Size reg (SR) */
222 MVGBE_REG_WR(regs->barsz[param->win].size,
223 (((param->size / 0x10000) - 1) << 16));
225 /* Set window Base address reg (BA) */
226 MVGBE_REG_WR(regs->barsz[param->win].bar,
227 (param->target | param->attrib | param->base_addr));
228 /* High address remap reg (HARR) */
230 MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
232 /* Base address enable reg (BARER) */
233 if (param->enable == 1)
234 MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
236 MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
239 static void set_dram_access(struct mvgbe_registers *regs)
241 struct mvgbe_winparam win_param;
244 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
245 /* Set access parameters for DRAM bank i */
246 win_param.win = i; /* Use Ethernet window i */
247 /* Window target - DDR */
248 win_param.target = MVGBE_TARGET_DRAM;
249 /* Enable full access */
250 win_param.access_ctrl = EWIN_ACCESS_FULL;
251 win_param.high_addr = 0;
252 /* Get bank base and size */
253 win_param.base_addr = gd->bd->bi_dram[i].start;
254 win_param.size = gd->bd->bi_dram[i].size;
255 if (win_param.size == 0)
256 win_param.enable = 0;
258 win_param.enable = 1; /* Enable the access */
260 /* Enable DRAM bank */
263 win_param.attrib = EBAR_DRAM_CS0;
266 win_param.attrib = EBAR_DRAM_CS1;
269 win_param.attrib = EBAR_DRAM_CS2;
272 win_param.attrib = EBAR_DRAM_CS3;
275 /* invalid bank, disable access */
276 win_param.enable = 0;
277 win_param.attrib = 0;
280 /* Set the access control for address window(EPAPR) RD/WR */
281 set_access_control(regs, &win_param);
286 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
288 * Go through all the DA filter tables (Unicast, Special Multicast & Other
289 * Multicast) and set each entry to 0.
291 static void port_init_mac_tables(struct mvgbe_registers *regs)
295 /* Clear DA filter unicast table (Ex_dFUT) */
296 for (table_index = 0; table_index < 4; ++table_index)
297 MVGBE_REG_WR(regs->dfut[table_index], 0);
299 for (table_index = 0; table_index < 64; ++table_index) {
300 /* Clear DA filter special multicast table (Ex_dFSMT) */
301 MVGBE_REG_WR(regs->dfsmt[table_index], 0);
302 /* Clear DA filter other multicast table (Ex_dFOMT) */
303 MVGBE_REG_WR(regs->dfomt[table_index], 0);
308 * port_uc_addr - This function Set the port unicast address table
310 * This function locates the proper entry in the Unicast table for the
311 * specified MAC nibble and sets its properties according to function
313 * This function add/removes MAC addresses from the port unicast address
316 * @uc_nibble Unicast MAC Address last nibble.
317 * @option 0 = Add, 1 = remove address.
319 * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
321 static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
328 /* Locate the Unicast table entry */
329 uc_nibble = (0xf & uc_nibble);
330 /* Register offset from unicast table base */
331 tbl_offset = (uc_nibble / 4);
332 /* Entry offset within the above register */
333 reg_offset = uc_nibble % 4;
336 case REJECT_MAC_ADDR:
338 * Clear accepts frame bit at specified unicast
341 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
342 unicast_reg &= (0xFF << (8 * reg_offset));
343 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
345 case ACCEPT_MAC_ADDR:
346 /* Set accepts frame bit at unicast DA filter table entry */
347 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
348 unicast_reg &= (0xFF << (8 * reg_offset));
349 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
350 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
359 * port_uc_addr_set - This function Set the port Unicast address.
361 static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
366 mac_l = (p_addr[4] << 8) | (p_addr[5]);
367 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
370 MVGBE_REG_WR(regs->macal, mac_l);
371 MVGBE_REG_WR(regs->macah, mac_h);
373 /* Accept frames of this address */
374 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
378 * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
380 static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
382 struct mvgbe_rxdesc *p_rx_desc;
385 /* initialize the Rx descriptors ring */
386 p_rx_desc = dmvgbe->p_rxdesc;
387 for (i = 0; i < RINGSZ; i++) {
389 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
390 p_rx_desc->buf_size = PKTSIZE_ALIGN;
391 p_rx_desc->byte_cnt = 0;
392 p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
393 if (i == (RINGSZ - 1))
394 p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
396 p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
397 ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
398 p_rx_desc = p_rx_desc->nxtdesc_p;
401 dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
404 static int mvgbe_init(struct eth_device *dev)
406 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
407 struct mvgbe_registers *regs = dmvgbe->regs;
408 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
409 !defined(CONFIG_PHYLIB) && \
410 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
414 mvgbe_init_rx_desc_ring(dmvgbe);
416 /* Clear the ethernet port interrupts */
417 MVGBE_REG_WR(regs->ic, 0);
418 MVGBE_REG_WR(regs->ice, 0);
419 /* Unmask RX buffer and TX end interrupt */
420 MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
421 /* Unmask phy and link status changes interrupts */
422 MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
424 set_dram_access(regs);
425 port_init_mac_tables(regs);
426 port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
428 /* Assign port configuration and command. */
429 MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
430 MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
431 MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
433 /* Assign port SDMA configuration */
434 MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
435 MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
436 MVGBE_REG_WR(regs->tqx[0].tqxtbc,
437 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
438 /* Turn off the port/RXUQ bandwidth limitation */
439 MVGBE_REG_WR(regs->pmtu, 0);
441 /* Set maximum receive buffer to 9700 bytes */
442 MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
443 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
445 /* Enable port initially */
446 MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
449 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
450 * disable the leaky bucket mechanism .
452 MVGBE_REG_WR(regs->pmtu, 0);
454 /* Assignment of Rx CRDB of given RXUQ */
455 MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
456 /* ensure previous write is done before enabling Rx DMA */
458 /* Enable port Rx. */
459 MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
461 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
462 !defined(CONFIG_PHYLIB) && \
463 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
464 /* Wait up to 5s for the link status */
465 for (i = 0; i < 5; i++) {
468 miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
469 MV_PHY_ADR_REQUEST, &phyadr);
470 /* Return if we get link up */
471 if (miiphy_link(dev->name, phyadr))
476 printf("No link on %s\n", dev->name);
482 static int mvgbe_halt(struct eth_device *dev)
484 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
485 struct mvgbe_registers *regs = dmvgbe->regs;
487 /* Disable all gigE address decoder */
488 MVGBE_REG_WR(regs->bare, 0x3f);
490 stop_queue(®s->tqc);
491 stop_queue(®s->rqc);
494 MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
495 /* Set port is not reset */
496 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
497 #ifdef CONFIG_SYS_MII_MODE
498 /* Set MMI interface up */
499 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
501 /* Disable & mask ethernet port interrupts */
502 MVGBE_REG_WR(regs->ic, 0);
503 MVGBE_REG_WR(regs->ice, 0);
504 MVGBE_REG_WR(regs->pim, 0);
505 MVGBE_REG_WR(regs->peim, 0);
510 static int mvgbe_write_hwaddr(struct eth_device *dev)
512 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
513 struct mvgbe_registers *regs = dmvgbe->regs;
515 /* Programs net device MAC address after initialization */
516 port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
520 static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
522 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
523 struct mvgbe_registers *regs = dmvgbe->regs;
524 struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
525 void *p = (void *)dataptr;
529 /* Copy buffer if it's misaligned */
530 if ((u32) dataptr & 0x07) {
531 if (datasize > PKTSIZE_ALIGN) {
532 printf("Non-aligned data too large (%d)\n",
537 memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
538 p = dmvgbe->p_aligned_txbuf;
541 p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
542 p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
543 p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
544 p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
545 p_txdesc->buf_ptr = (u8 *) p;
546 p_txdesc->byte_cnt = datasize;
548 /* Set this tc desc as zeroth TXUQ */
549 txuq0_reg_addr = (u32)®s->tcqdp[TXUQ];
550 writel((u32) p_txdesc, txuq0_reg_addr);
552 /* ensure tx desc writes above are performed before we start Tx DMA */
555 /* Apply send command using zeroth TXUQ */
556 MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
559 * wait for packet xmit completion
561 cmd_sts = readl(&p_txdesc->cmd_sts);
562 while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
563 /* return fail if error is detected */
564 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
565 (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
566 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
567 printf("Err..(%s) in xmit packet\n", __func__);
570 cmd_sts = readl(&p_txdesc->cmd_sts);
575 static int mvgbe_recv(struct eth_device *dev)
577 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
578 struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
581 u32 rxdesc_curr_addr;
583 /* wait untill rx packet available or timeout */
585 if (timeout < MVGBE_PHY_SMI_TIMEOUT)
588 debug("%s time out...\n", __func__);
591 } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
593 if (p_rxdesc_curr->byte_cnt != 0) {
594 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
595 __func__, (u32) p_rxdesc_curr->byte_cnt,
596 (u32) p_rxdesc_curr->buf_ptr,
597 (u32) p_rxdesc_curr->cmd_sts);
601 * In case received a packet without first/last bits on
602 * OR the error summary bit is on,
603 * the packets needs to be dropeed.
605 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
608 (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
609 != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
611 printf("Err..(%s) Dropping packet spread on"
612 " multiple descriptors\n", __func__);
614 } else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
616 printf("Err..(%s) Dropping packet with errors\n",
620 /* !!! call higher layer processing */
621 debug("%s: Sending Received packet to"
622 " upper layer (net_process_received_packet)\n",
625 /* let the upper layer handle the packet */
626 net_process_received_packet((p_rxdesc_curr->buf_ptr +
628 (int)(p_rxdesc_curr->byte_cnt -
632 * free these descriptors and point next in the ring
634 p_rxdesc_curr->cmd_sts =
635 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
636 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
637 p_rxdesc_curr->byte_cnt = 0;
639 rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
640 writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
645 #if defined(CONFIG_PHYLIB)
646 int mvgbe_phylib_init(struct eth_device *dev, int phyid)
649 struct phy_device *phydev;
654 printf("mdio_alloc failed\n");
657 bus->read = smi_reg_read;
658 bus->write = smi_reg_write;
659 strcpy(bus->name, dev->name);
661 ret = mdio_register(bus);
663 printf("mdio_register failed\n");
668 /* Set phy address of the port */
669 smi_reg_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
671 phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
673 printf("phy_connect failed\n");
684 int mvgbe_initialize(bd_t *bis)
686 struct mvgbe_device *dmvgbe;
687 struct eth_device *dev;
689 u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
691 for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
692 /*skip if port is configured not to use */
693 if (used_ports[devnum] == 0)
696 dmvgbe = malloc(sizeof(struct mvgbe_device));
701 memset(dmvgbe, 0, sizeof(struct mvgbe_device));
704 (struct mvgbe_rxdesc *)memalign(PKTALIGN,
705 MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
707 if (!dmvgbe->p_rxdesc)
710 dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
711 RINGSZ*PKTSIZE_ALIGN + 1);
713 if (!dmvgbe->p_rxbuf)
716 dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
718 if (!dmvgbe->p_aligned_txbuf)
721 dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
722 PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
724 if (!dmvgbe->p_txdesc) {
725 free(dmvgbe->p_aligned_txbuf);
727 free(dmvgbe->p_rxbuf);
729 free(dmvgbe->p_rxdesc);
733 printf("Err.. %s Failed to allocate memory\n",
740 /* must be less than sizeof(dev->name) */
741 sprintf(dev->name, "egiga%d", devnum);
745 dmvgbe->regs = (void *)MVGBE0_BASE;
747 #if defined(MVGBE1_BASE)
749 dmvgbe->regs = (void *)MVGBE1_BASE;
752 default: /* this should never happen */
753 printf("Err..(%s) Invalid device number %d\n",
758 dev->init = (void *)mvgbe_init;
759 dev->halt = (void *)mvgbe_halt;
760 dev->send = (void *)mvgbe_send;
761 dev->recv = (void *)mvgbe_recv;
762 dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
766 #if defined(CONFIG_PHYLIB)
767 mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
768 #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
770 struct mii_dev *mdiodev = mdio_alloc();
773 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
774 mdiodev->read = smi_reg_read;
775 mdiodev->write = smi_reg_write;
777 retval = mdio_register(mdiodev);
780 /* Set phy address of the port */
781 miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
782 MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);