1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 MediaTek Inc.
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 * Author: Mark Lee <mark-mc.lee@mediatek.com>
20 #include <linux/err.h>
21 #include <linux/ioport.h>
22 #include <linux/mdio.h>
23 #include <linux/mii.h>
27 #define NUM_TX_DESC 24
28 #define NUM_RX_DESC 24
29 #define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN)
30 #define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN)
31 #define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE)
33 #define MT7530_NUM_PHYS 5
34 #define MT7530_DFL_SMI_ADDR 31
36 #define MT7530_PHY_ADDR(base, addr) \
37 (((base) + (addr)) & 0x1f)
39 #define GDMA_FWD_TO_CPU \
45 (DP_PDMA << MYMAC_DP_S) | \
46 (DP_PDMA << BC_DP_S) | \
47 (DP_PDMA << MC_DP_S) | \
50 #define GDMA_FWD_DISCARD \
56 (DP_DISCARD << MYMAC_DP_S) | \
57 (DP_DISCARD << BC_DP_S) | \
58 (DP_DISCARD << MC_DP_S) | \
59 (DP_DISCARD << UN_DP_S))
61 struct pdma_rxd_info1 {
65 struct pdma_rxd_info2 {
74 struct pdma_rxd_info3 {
78 struct pdma_rxd_info4 {
92 struct pdma_rxd_info1 rxd_info1;
93 struct pdma_rxd_info2 rxd_info2;
94 struct pdma_rxd_info3 rxd_info3;
95 struct pdma_rxd_info4 rxd_info4;
98 struct pdma_txd_info1 {
102 struct pdma_txd_info2 {
111 struct pdma_txd_info3 {
115 struct pdma_txd_info4 {
126 struct pdma_txd_info1 txd_info1;
127 struct pdma_txd_info2 txd_info2;
128 struct pdma_txd_info3 txd_info3;
129 struct pdma_txd_info4 txd_info4;
142 struct mtk_eth_priv {
143 char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
145 struct pdma_txdesc *tx_ring_noc;
146 struct pdma_rxdesc *rx_ring_noc;
148 int rx_dma_owner_idx0;
149 int tx_cpu_owner_idx0;
151 void __iomem *fe_base;
152 void __iomem *gmac_base;
153 void __iomem *ethsys_base;
155 struct mii_dev *mdio_bus;
156 int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
157 int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
158 int (*mmd_read)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg);
159 int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
168 struct phy_device *phydev;
173 int (*switch_init)(struct mtk_eth_priv *priv);
177 struct gpio_desc rst_gpio;
180 struct reset_ctl rst_fe;
181 struct reset_ctl rst_mcm;
184 static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
186 writel(val, priv->fe_base + PDMA_BASE + reg);
189 static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
192 clrsetbits_le32(priv->fe_base + PDMA_BASE + reg, clr, set);
195 static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg,
201 gdma_base = GDMA2_BASE;
203 gdma_base = GDMA1_BASE;
205 writel(val, priv->fe_base + gdma_base + reg);
208 static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
210 return readl(priv->gmac_base + reg);
213 static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
215 writel(val, priv->gmac_base + reg);
218 static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
220 clrsetbits_le32(priv->gmac_base + reg, clr, set);
223 static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
226 clrsetbits_le32(priv->ethsys_base + reg, clr, set);
229 /* Direct MDIO clause 22/45 access via SoC */
230 static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
236 val = (st << MDIO_ST_S) |
237 ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
238 (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
239 (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
241 if (cmd == MDIO_CMD_WRITE)
242 val |= data & MDIO_RW_DATA_M;
244 mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
246 ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG,
247 PHY_ACS_ST, 0, 5000, 0);
249 pr_warn("MDIO access timeout\n");
253 if (cmd == MDIO_CMD_READ) {
254 val = mtk_gmac_read(priv, GMAC_PIAC_REG);
255 return val & MDIO_RW_DATA_M;
261 /* Direct MDIO clause 22 read via SoC */
262 static int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg)
264 return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22);
267 /* Direct MDIO clause 22 write via SoC */
268 static int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data)
270 return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22);
273 /* Direct MDIO clause 45 read via SoC */
274 static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
278 ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
282 return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45,
286 /* Direct MDIO clause 45 write via SoC */
287 static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
292 ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
296 return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE,
300 /* Indirect MDIO clause 45 read via MII registers */
301 static int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
306 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
307 (MMD_ADDR << MMD_CMD_S) |
308 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
312 ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
316 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
317 (MMD_DATA << MMD_CMD_S) |
318 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
322 return priv->mii_read(priv, addr, MII_MMD_ADDR_DATA_REG);
325 /* Indirect MDIO clause 45 write via MII registers */
326 static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
331 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
332 (MMD_ADDR << MMD_CMD_S) |
333 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
337 ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
341 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
342 (MMD_DATA << MMD_CMD_S) |
343 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
347 return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val);
350 static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
352 struct mtk_eth_priv *priv = bus->priv;
355 return priv->mii_read(priv, addr, reg);
357 return priv->mmd_read(priv, addr, devad, reg);
360 static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
363 struct mtk_eth_priv *priv = bus->priv;
366 return priv->mii_write(priv, addr, reg, val);
368 return priv->mmd_write(priv, addr, devad, reg, val);
371 static int mtk_mdio_register(struct udevice *dev)
373 struct mtk_eth_priv *priv = dev_get_priv(dev);
374 struct mii_dev *mdio_bus = mdio_alloc();
380 /* Assign MDIO access APIs according to the switch/phy */
383 priv->mii_read = mtk_mii_read;
384 priv->mii_write = mtk_mii_write;
385 priv->mmd_read = mtk_mmd_ind_read;
386 priv->mmd_write = mtk_mmd_ind_write;
389 priv->mii_read = mtk_mii_read;
390 priv->mii_write = mtk_mii_write;
391 priv->mmd_read = mtk_mmd_read;
392 priv->mmd_write = mtk_mmd_write;
395 mdio_bus->read = mtk_mdio_read;
396 mdio_bus->write = mtk_mdio_write;
397 snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name);
399 mdio_bus->priv = (void *)priv;
401 ret = mdio_register(mdio_bus);
406 priv->mdio_bus = mdio_bus;
412 * MT7530 Internal Register Address Bits
413 * -------------------------------------------------------------------
414 * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 |
415 * |----------------------------------------|---------------|--------|
416 * | Page Address | Reg Address | Unused |
417 * -------------------------------------------------------------------
420 static int mt7530_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data)
422 int ret, low_word, high_word;
424 /* Write page address */
425 ret = mtk_mii_write(priv, priv->mt7530_smi_addr, 0x1f, reg >> 6);
430 low_word = mtk_mii_read(priv, priv->mt7530_smi_addr, (reg >> 2) & 0xf);
435 high_word = mtk_mii_read(priv, priv->mt7530_smi_addr, 0x10);
440 *data = ((u32)high_word << 16) | (low_word & 0xffff);
445 static int mt7530_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data)
449 /* Write page address */
450 ret = mtk_mii_write(priv, priv->mt7530_smi_addr, 0x1f, reg >> 6);
455 ret = mtk_mii_write(priv, priv->mt7530_smi_addr, (reg >> 2) & 0xf,
460 /* Write high word */
461 return mtk_mii_write(priv, priv->mt7530_smi_addr, 0x10, data >> 16);
464 static void mt7530_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
469 mt7530_reg_read(priv, reg, &val);
472 mt7530_reg_write(priv, reg, val);
475 static void mt7530_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
477 u8 phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, 0);
479 mtk_mmd_ind_write(priv, phy_addr, 0x1f, reg, val);
482 static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode)
484 u32 ncpo1, ssc_delta;
487 case PHY_INTERFACE_MODE_RGMII:
492 printf("error: xMII mode %d not supported\n", mode);
496 /* Disable MT7530 core clock */
497 mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0);
499 /* Disable MT7530 PLL */
500 mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1,
501 (2 << RG_GSWPLL_POSDIV_200M_S) |
502 (32 << RG_GSWPLL_FBKDIV_200M_S));
504 /* For MT7530 core clock = 500Mhz */
505 mt7530_core_reg_write(priv, CORE_GSWPLL_GRP2,
506 (1 << RG_GSWPLL_POSDIV_500M_S) |
507 (25 << RG_GSWPLL_FBKDIV_500M_S));
509 /* Enable MT7530 PLL */
510 mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1,
511 (2 << RG_GSWPLL_POSDIV_200M_S) |
512 (32 << RG_GSWPLL_FBKDIV_200M_S) |
517 mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
519 /* Setup the MT7530 TRGMII Tx Clock */
520 mt7530_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1);
521 mt7530_core_reg_write(priv, CORE_PLL_GROUP6, 0);
522 mt7530_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta);
523 mt7530_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta);
524 mt7530_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
525 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
527 mt7530_core_reg_write(priv, CORE_PLL_GROUP2,
528 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
529 (1 << RG_SYSPLL_POSDIV_S));
531 mt7530_core_reg_write(priv, CORE_PLL_GROUP7,
532 RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) |
533 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
535 /* Enable MT7530 core clock */
536 mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG,
537 REG_GSWCK_EN | REG_TRGMIICK_EN);
542 static int mt7530_setup(struct mtk_eth_priv *priv)
544 u16 phy_addr, phy_val;
548 /* Select 250MHz clk for RGMII mode */
549 mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
550 ETHSYS_TRGMII_CLK_SEL362_5, 0);
552 /* Global reset switch */
554 reset_assert(&priv->rst_mcm);
556 reset_deassert(&priv->rst_mcm);
558 } else if (dm_gpio_is_valid(&priv->rst_gpio)) {
559 dm_gpio_set_value(&priv->rst_gpio, 0);
561 dm_gpio_set_value(&priv->rst_gpio, 1);
565 /* Modify HWTRAP first to allow direct access to internal PHYs */
566 mt7530_reg_read(priv, HWTRAP_REG, &val);
569 mt7530_reg_write(priv, MHWTRAP_REG, val);
571 /* Calculate the phy base address */
572 val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3;
573 priv->mt7530_phy_base = (val | 0x7) + 1;
576 for (i = 0; i < MT7530_NUM_PHYS; i++) {
577 phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, i);
578 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
579 phy_val |= BMCR_PDOWN;
580 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
583 /* Force MAC link down before reset */
584 mt7530_reg_write(priv, PCMR_REG(5), FORCE_MODE);
585 mt7530_reg_write(priv, PCMR_REG(6), FORCE_MODE);
588 mt7530_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
591 val = (1 << IPG_CFG_S) |
592 MAC_MODE | FORCE_MODE |
593 MAC_TX_EN | MAC_RX_EN |
594 BKOFF_EN | BACKPR_EN |
595 (SPEED_1000M << FORCE_SPD_S) |
596 FORCE_DPX | FORCE_LINK;
598 /* MT7530 Port6: Forced 1000M/FD, FC disabled */
599 mt7530_reg_write(priv, PCMR_REG(6), val);
601 /* MT7530 Port5: Forced link down */
602 mt7530_reg_write(priv, PCMR_REG(5), FORCE_MODE);
604 /* MT7530 Port6: Set to RGMII */
605 mt7530_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
607 /* Hardware Trap: Enable Port6, Disable Port5 */
608 mt7530_reg_read(priv, HWTRAP_REG, &val);
609 val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS |
610 (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) |
611 (P5_INTF_MODE_RGMII << P5_INTF_MODE_S);
612 val &= ~(C_MDIO_BPS | P6_INTF_DIS);
613 mt7530_reg_write(priv, MHWTRAP_REG, val);
615 /* Setup switch core pll */
616 mt7530_pad_clk_setup(priv, priv->phy_interface);
618 /* Lower Tx Driving for TRGMII path */
619 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
620 mt7530_reg_write(priv, MT7530_TRGMII_TD_ODT(i),
621 (8 << TD_DM_DRVP_S) | (8 << TD_DM_DRVN_S));
623 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
624 mt7530_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
627 for (i = 0; i < MT7530_NUM_PHYS; i++) {
628 phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, i);
629 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
630 phy_val &= ~BMCR_PDOWN;
631 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
634 /* Set port isolation */
635 for (i = 0; i < 8; i++) {
636 /* Set port matrix mode */
638 mt7530_reg_write(priv, PCR_REG(i),
639 (0x40 << PORT_MATRIX_S));
641 mt7530_reg_write(priv, PCR_REG(i),
642 (0x3f << PORT_MATRIX_S));
644 /* Set port mode to user port */
645 mt7530_reg_write(priv, PVC_REG(i),
646 (0x8100 << STAG_VPID_S) |
647 (VLAN_ATTR_USER << VLAN_ATTR_S));
653 static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
655 u16 lcl_adv = 0, rmt_adv = 0;
659 mcr = (1 << IPG_CFG_S) |
660 (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
661 MAC_MODE | FORCE_MODE |
662 MAC_TX_EN | MAC_RX_EN |
663 BKOFF_EN | BACKPR_EN;
665 switch (priv->phydev->speed) {
667 mcr |= (SPEED_10M << FORCE_SPD_S);
670 mcr |= (SPEED_100M << FORCE_SPD_S);
673 mcr |= (SPEED_1000M << FORCE_SPD_S);
677 if (priv->phydev->link)
680 if (priv->phydev->duplex) {
683 if (priv->phydev->pause)
684 rmt_adv = LPA_PAUSE_CAP;
685 if (priv->phydev->asym_pause)
686 rmt_adv |= LPA_PAUSE_ASYM;
688 if (priv->phydev->advertising & ADVERTISED_Pause)
689 lcl_adv |= ADVERTISE_PAUSE_CAP;
690 if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
691 lcl_adv |= ADVERTISE_PAUSE_ASYM;
693 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
695 if (flowctrl & FLOW_CTRL_TX)
697 if (flowctrl & FLOW_CTRL_RX)
700 debug("rx pause %s, tx pause %s\n",
701 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
702 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
705 mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
708 static int mtk_phy_start(struct mtk_eth_priv *priv)
710 struct phy_device *phydev = priv->phydev;
713 ret = phy_startup(phydev);
716 debug("Could not initialize PHY %s\n", phydev->dev->name);
721 debug("%s: link down.\n", phydev->dev->name);
725 mtk_phy_link_adjust(priv);
727 debug("Speed: %d, %s duplex%s\n", phydev->speed,
728 (phydev->duplex) ? "full" : "half",
729 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
734 static int mtk_phy_probe(struct udevice *dev)
736 struct mtk_eth_priv *priv = dev_get_priv(dev);
737 struct phy_device *phydev;
739 phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev,
740 priv->phy_interface);
744 phydev->supported &= PHY_GBIT_FEATURES;
745 phydev->advertising = phydev->supported;
747 priv->phydev = phydev;
753 static void mtk_mac_init(struct mtk_eth_priv *priv)
758 switch (priv->phy_interface) {
759 case PHY_INTERFACE_MODE_RGMII_RXID:
760 case PHY_INTERFACE_MODE_RGMII:
761 case PHY_INTERFACE_MODE_SGMII:
762 ge_mode = GE_MODE_RGMII;
764 case PHY_INTERFACE_MODE_MII:
765 case PHY_INTERFACE_MODE_GMII:
766 ge_mode = GE_MODE_MII;
768 case PHY_INTERFACE_MODE_RMII:
769 ge_mode = GE_MODE_RMII;
775 /* set the gmac to the right mode */
776 mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
777 SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
778 ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id));
780 if (priv->force_mode) {
781 mcr = (1 << IPG_CFG_S) |
782 (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
783 MAC_MODE | FORCE_MODE |
784 MAC_TX_EN | MAC_RX_EN |
785 BKOFF_EN | BACKPR_EN |
788 switch (priv->speed) {
790 mcr |= SPEED_10M << FORCE_SPD_S;
793 mcr |= SPEED_100M << FORCE_SPD_S;
796 mcr |= SPEED_1000M << FORCE_SPD_S;
803 mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
806 if (priv->soc == SOC_MT7623) {
807 /* Lower Tx Driving for TRGMII path */
808 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
809 mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i),
810 (8 << TD_DM_DRVP_S) |
811 (8 << TD_DM_DRVN_S));
813 mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0,
814 RX_RST | RXC_DQSISEL);
815 mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0);
819 static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
821 char *pkt_base = priv->pkt_pool;
824 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0);
827 memset(priv->tx_ring_noc, 0, NUM_TX_DESC * sizeof(struct pdma_txdesc));
828 memset(priv->rx_ring_noc, 0, NUM_RX_DESC * sizeof(struct pdma_rxdesc));
829 memset(priv->pkt_pool, 0, TOTAL_PKT_BUF_SIZE);
831 flush_dcache_range((u32)pkt_base, (u32)(pkt_base + TOTAL_PKT_BUF_SIZE));
833 priv->rx_dma_owner_idx0 = 0;
834 priv->tx_cpu_owner_idx0 = 0;
836 for (i = 0; i < NUM_TX_DESC; i++) {
837 priv->tx_ring_noc[i].txd_info2.LS0 = 1;
838 priv->tx_ring_noc[i].txd_info2.DDONE = 1;
839 priv->tx_ring_noc[i].txd_info4.FPORT = priv->gmac_id + 1;
841 priv->tx_ring_noc[i].txd_info1.SDP0 = virt_to_phys(pkt_base);
842 pkt_base += PKTSIZE_ALIGN;
845 for (i = 0; i < NUM_RX_DESC; i++) {
846 priv->rx_ring_noc[i].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
847 priv->rx_ring_noc[i].rxd_info1.PDP0 = virt_to_phys(pkt_base);
848 pkt_base += PKTSIZE_ALIGN;
851 mtk_pdma_write(priv, TX_BASE_PTR_REG(0),
852 virt_to_phys(priv->tx_ring_noc));
853 mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC);
854 mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
856 mtk_pdma_write(priv, RX_BASE_PTR_REG(0),
857 virt_to_phys(priv->rx_ring_noc));
858 mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC);
859 mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1);
861 mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0);
864 static int mtk_eth_start(struct udevice *dev)
866 struct mtk_eth_priv *priv = dev_get_priv(dev);
870 reset_assert(&priv->rst_fe);
872 reset_deassert(&priv->rst_fe);
875 /* Packets forward to PDMA */
876 mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
878 if (priv->gmac_id == 0)
879 mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
881 mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
885 mtk_eth_fifo_init(priv);
888 if (priv->sw == SW_NONE) {
889 ret = mtk_phy_start(priv);
894 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0,
895 TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
901 static void mtk_eth_stop(struct udevice *dev)
903 struct mtk_eth_priv *priv = dev_get_priv(dev);
905 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
906 TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
909 wait_for_bit_le32(priv->fe_base + PDMA_BASE + PDMA_GLO_CFG_REG,
910 RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0);
913 static int mtk_eth_write_hwaddr(struct udevice *dev)
915 struct eth_pdata *pdata = dev_get_platdata(dev);
916 struct mtk_eth_priv *priv = dev_get_priv(dev);
917 unsigned char *mac = pdata->enetaddr;
918 u32 macaddr_lsb, macaddr_msb;
920 macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1];
921 macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) |
922 ((u32)mac[4] << 8) | (u32)mac[5];
924 mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb);
925 mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb);
930 static int mtk_eth_send(struct udevice *dev, void *packet, int length)
932 struct mtk_eth_priv *priv = dev_get_priv(dev);
933 u32 idx = priv->tx_cpu_owner_idx0;
936 if (!priv->tx_ring_noc[idx].txd_info2.DDONE) {
937 debug("mtk-eth: TX DMA descriptor ring is full\n");
941 pkt_base = (void *)phys_to_virt(priv->tx_ring_noc[idx].txd_info1.SDP0);
942 memcpy(pkt_base, packet, length);
943 flush_dcache_range((u32)pkt_base, (u32)pkt_base +
944 roundup(length, ARCH_DMA_MINALIGN));
946 priv->tx_ring_noc[idx].txd_info2.SDL0 = length;
947 priv->tx_ring_noc[idx].txd_info2.DDONE = 0;
949 priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC;
950 mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
955 static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp)
957 struct mtk_eth_priv *priv = dev_get_priv(dev);
958 u32 idx = priv->rx_dma_owner_idx0;
962 if (!priv->rx_ring_noc[idx].rxd_info2.DDONE) {
963 debug("mtk-eth: RX DMA descriptor ring is empty\n");
967 length = priv->rx_ring_noc[idx].rxd_info2.PLEN0;
968 pkt_base = (void *)phys_to_virt(priv->rx_ring_noc[idx].rxd_info1.PDP0);
969 invalidate_dcache_range((u32)pkt_base, (u32)pkt_base +
970 roundup(length, ARCH_DMA_MINALIGN));
978 static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
980 struct mtk_eth_priv *priv = dev_get_priv(dev);
981 u32 idx = priv->rx_dma_owner_idx0;
983 priv->rx_ring_noc[idx].rxd_info2.DDONE = 0;
984 priv->rx_ring_noc[idx].rxd_info2.LS0 = 0;
985 priv->rx_ring_noc[idx].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
987 mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx);
988 priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC;
993 static int mtk_eth_probe(struct udevice *dev)
995 struct eth_pdata *pdata = dev_get_platdata(dev);
996 struct mtk_eth_priv *priv = dev_get_priv(dev);
997 u32 iobase = pdata->iobase;
1000 /* Frame Engine Register Base */
1001 priv->fe_base = (void *)iobase;
1003 /* GMAC Register Base */
1004 priv->gmac_base = (void *)(iobase + GMAC_BASE);
1007 ret = mtk_mdio_register(dev);
1011 /* Prepare for tx/rx rings */
1012 priv->tx_ring_noc = (struct pdma_txdesc *)
1013 noncached_alloc(sizeof(struct pdma_txdesc) * NUM_TX_DESC,
1015 priv->rx_ring_noc = (struct pdma_rxdesc *)
1016 noncached_alloc(sizeof(struct pdma_rxdesc) * NUM_RX_DESC,
1022 /* Probe phy if switch is not specified */
1023 if (priv->sw == SW_NONE)
1024 return mtk_phy_probe(dev);
1026 /* Initialize switch */
1027 return priv->switch_init(priv);
1030 static int mtk_eth_remove(struct udevice *dev)
1032 struct mtk_eth_priv *priv = dev_get_priv(dev);
1034 /* MDIO unregister */
1035 mdio_unregister(priv->mdio_bus);
1036 mdio_free(priv->mdio_bus);
1038 /* Stop possibly started DMA */
1044 static int mtk_eth_ofdata_to_platdata(struct udevice *dev)
1046 struct eth_pdata *pdata = dev_get_platdata(dev);
1047 struct mtk_eth_priv *priv = dev_get_priv(dev);
1048 struct ofnode_phandle_args args;
1049 struct regmap *regmap;
1054 priv->soc = dev_get_driver_data(dev);
1056 pdata->iobase = devfdt_get_addr(dev);
1058 /* get corresponding ethsys phandle */
1059 ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0,
1064 regmap = syscon_node_to_regmap(args.node);
1066 return PTR_ERR(regmap);
1068 priv->ethsys_base = regmap_get_range(regmap, 0);
1069 if (!priv->ethsys_base) {
1070 dev_err(dev, "Unable to find ethsys\n");
1074 /* Reset controllers */
1075 ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
1077 printf("error: Unable to get reset ctrl for frame engine\n");
1081 priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0);
1083 /* Interface mode is required */
1084 str = dev_read_string(dev, "phy-mode");
1086 pdata->phy_interface = phy_get_interface_by_name(str);
1087 priv->phy_interface = pdata->phy_interface;
1089 printf("error: phy-mode is not set\n");
1093 /* Force mode or autoneg */
1094 subnode = ofnode_find_subnode(dev_ofnode(dev), "fixed-link");
1095 if (ofnode_valid(subnode)) {
1096 priv->force_mode = 1;
1097 priv->speed = ofnode_read_u32_default(subnode, "speed", 0);
1098 priv->duplex = ofnode_read_bool(subnode, "full-duplex");
1100 if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
1101 priv->speed != SPEED_1000) {
1102 printf("error: no valid speed set in fixed-link\n");
1107 /* check for switch first, otherwise phy will be used */
1109 priv->switch_init = NULL;
1110 str = dev_read_string(dev, "mediatek,switch");
1113 if (!strcmp(str, "mt7530")) {
1114 priv->sw = SW_MT7530;
1115 priv->switch_init = mt7530_setup;
1116 priv->mt7530_smi_addr = MT7530_DFL_SMI_ADDR;
1118 printf("error: unsupported switch\n");
1122 priv->mcm = dev_read_bool(dev, "mediatek,mcm");
1124 ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm);
1126 printf("error: no reset ctrl for mcm\n");
1130 gpio_request_by_name(dev, "reset-gpios", 0,
1131 &priv->rst_gpio, GPIOD_IS_OUT);
1134 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0,
1137 printf("error: phy-handle is not specified\n");
1141 priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1);
1142 if (priv->phy_addr < 0) {
1143 printf("error: phy address is not specified\n");
1151 static const struct udevice_id mtk_eth_ids[] = {
1152 { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 },
1153 { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 },
1157 static const struct eth_ops mtk_eth_ops = {
1158 .start = mtk_eth_start,
1159 .stop = mtk_eth_stop,
1160 .send = mtk_eth_send,
1161 .recv = mtk_eth_recv,
1162 .free_pkt = mtk_eth_free_pkt,
1163 .write_hwaddr = mtk_eth_write_hwaddr,
1166 U_BOOT_DRIVER(mtk_eth) = {
1169 .of_match = mtk_eth_ids,
1170 .ofdata_to_platdata = mtk_eth_ofdata_to_platdata,
1171 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1172 .probe = mtk_eth_probe,
1173 .remove = mtk_eth_remove,
1174 .ops = &mtk_eth_ops,
1175 .priv_auto_alloc_size = sizeof(struct mtk_eth_priv),
1176 .flags = DM_FLAG_ALLOC_PRIV_DMA,