1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2019 Microsemi Corporation
9 #include <dm/of_access.h>
10 #include <dm/of_addr.h>
11 #include <fdt_support.h>
13 #include <linux/ioport.h>
18 #include "mscc_xfer.h"
19 #include "mscc_miim.h"
22 #define PHY_CFG_ENA 0x3
23 #define PHY_CFG_COMMON_RST BIT(2)
24 #define PHY_CFG_RST (0x3 << 3)
26 #define PHY_STAT_SUPERVISOR_COMPLETE BIT(0)
28 #define ANA_AC_RAM_CTRL_RAM_INIT 0x14fdc
29 #define ANA_AC_STAT_GLOBAL_CFG_PORT_RESET 0x15474
31 #define ANA_CL_PORT_VLAN_CFG(x) (0xa018 + 0xc8 * (x))
32 #define ANA_CL_PORT_VLAN_CFG_AWARE_ENA BIT(19)
33 #define ANA_CL_PORT_VLAN_CFG_POP_CNT(x) ((x) << 17)
35 #define ANA_L2_COMMON_FWD_CFG 0x18498
36 #define ANA_L2_COMMON_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6)
38 #define ASM_CFG_STAT_CFG 0xb08
39 #define ASM_CFG_PORT(x) (0xb74 + 0x4 * (x))
40 #define ASM_CFG_PORT_NO_PREAMBLE_ENA BIT(8)
41 #define ASM_CFG_PORT_INJ_FORMAT_CFG(x) ((x) << 1)
42 #define ASM_RAM_CTRL_RAM_INIT 0xbfc
44 #define DEV_DEV_CFG_DEV_RST_CTRL 0x0
45 #define DEV_DEV_CFG_DEV_RST_CTRL_SPEED_SEL(x) ((x) << 20)
46 #define DEV_MAC_CFG_MAC_ENA 0x24
47 #define DEV_MAC_CFG_MAC_ENA_RX_ENA BIT(4)
48 #define DEV_MAC_CFG_MAC_ENA_TX_ENA BIT(0)
49 #define DEV_MAC_CFG_MAC_IFG 0x3c
50 #define DEV_MAC_CFG_MAC_IFG_TX_IFG(x) ((x) << 8)
51 #define DEV_MAC_CFG_MAC_IFG_RX_IFG2(x) ((x) << 4)
52 #define DEV_MAC_CFG_MAC_IFG_RX_IFG1(x) (x)
53 #define DEV_PCS1G_CFG_PCS1G_CFG 0x48
54 #define DEV_PCS1G_CFG_PCS1G_CFG_PCS_ENA BIT(0)
55 #define DEV_PCS1G_CFG_PCS1G_MODE 0x4c
56 #define DEV_PCS1G_CFG_PCS1G_SD 0x50
57 #define DEV_PCS1G_CFG_PCS1G_ANEG 0x54
58 #define DEV_PCS1G_CFG_PCS1G_ANEG_ADV_ABILITY(x) ((x) << 16)
60 #define LRN_COMMON_ACCESS_CTRL 0x0
61 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT BIT(0)
62 #define LRN_COMMON_MAC_ACCESS_CFG0 0x4
63 #define LRN_COMMON_MAC_ACCESS_CFG1 0x8
64 #define LRN_COMMON_MAC_ACCESS_CFG2 0xc
65 #define LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_ADDR(x) (x)
66 #define LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_TYPE(x) ((x) << 12)
67 #define LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_VLD BIT(15)
68 #define LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_LOCKED BIT(16)
69 #define LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_CPU_COPY BIT(23)
70 #define LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_CPU_QU(x) ((x) << 24)
72 #define QFWD_SYSTEM_SWITCH_PORT_MODE(x) (0x4400 + 0x4 * (x))
73 #define QFWD_SYSTEM_SWITCH_PORT_MODE_PORT_ENA BIT(17)
75 #define QS_XTR_GRP_CFG(x) (4 * (x))
76 #define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
78 #define QSYS_SYSTEM_RESET_CFG 0x1048
79 #define QSYS_CALCFG_CAL_AUTO 0x1134
80 #define QSYS_CALCFG_CAL_CTRL 0x113c
81 #define QSYS_CALCFG_CAL_CTRL_CAL_MODE(x) ((x) << 11)
82 #define QSYS_RAM_CTRL_RAM_INIT 0x1140
84 #define REW_RAM_CTRL_RAM_INIT 0xFFF4
90 #define PGID_BROADCAST 50
91 #define PGID_UNICAST 51
93 static const char * const regs_names[] = {
95 "ana_ac", "ana_cl", "ana_l2", "asm", "lrn", "qfwd", "qs", "qsys", "rew",
98 #define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
101 enum servalt_ctrl_regs {
113 #define SERVALT_MIIM_BUS_COUNT 2
115 struct servalt_phy_port_t {
120 struct servalt_private {
121 void __iomem *regs[REGS_NAMES_COUNT];
122 struct mii_dev *bus[SERVALT_MIIM_BUS_COUNT];
123 struct servalt_phy_port_t ports[MAX_PORT];
126 static const unsigned long servalt_regs_qs[] = {
127 [MSCC_QS_XTR_RD] = 0x8,
128 [MSCC_QS_XTR_FLUSH] = 0x18,
129 [MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
130 [MSCC_QS_INJ_WR] = 0x2c,
131 [MSCC_QS_INJ_CTRL] = 0x34,
134 static struct mscc_miim_dev miim[SERVALT_MIIM_BUS_COUNT];
135 static int miim_count = -1;
137 static void mscc_phy_reset(void)
139 writel(0, BASE_DEVCPU_GCB + GCB_PHY_CFG + PHY_CFG);
140 writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
141 | PHY_CFG_ENA, BASE_DEVCPU_GCB + GCB_PHY_CFG + PHY_CFG);
142 if (wait_for_bit_le32((const void *)(BASE_DEVCPU_GCB + GCB_PHY_CFG) +
143 PHY_STAT, PHY_STAT_SUPERVISOR_COMPLETE,
144 true, 2000, false)) {
145 pr_err("Timeout in phy reset\n");
149 static void servalt_cpu_capture_setup(struct servalt_private *priv)
151 /* ASM: No preamble and IFH prefix on CPU injected frames */
152 writel(ASM_CFG_PORT_NO_PREAMBLE_ENA |
153 ASM_CFG_PORT_INJ_FORMAT_CFG(1),
154 priv->regs[ASM] + ASM_CFG_PORT(CPU_PORT));
156 /* Set Manual injection via DEVCPU_QS registers for CPU queue 0 */
157 writel(0x5, priv->regs[QS] + QS_INJ_GRP_CFG(0));
159 /* Set Manual extraction via DEVCPU_QS registers for CPU queue 0 */
160 writel(0x7, priv->regs[QS] + QS_XTR_GRP_CFG(0));
162 /* Enable CPU port for any frame transfer */
163 setbits_le32(priv->regs[QFWD] + QFWD_SYSTEM_SWITCH_PORT_MODE(CPU_PORT),
164 QFWD_SYSTEM_SWITCH_PORT_MODE_PORT_ENA);
166 /* Send a copy to CPU when found as forwarding entry */
167 setbits_le32(priv->regs[ANA_L2] + ANA_L2_COMMON_FWD_CFG,
168 ANA_L2_COMMON_FWD_CFG_CPU_DMAC_COPY_ENA);
171 static void servalt_port_init(struct servalt_private *priv, int port)
173 void __iomem *regs = priv->regs[port];
176 writel(DEV_PCS1G_CFG_PCS1G_CFG_PCS_ENA,
177 regs + DEV_PCS1G_CFG_PCS1G_CFG);
179 /* Disable Signal Detect */
180 writel(0, regs + DEV_PCS1G_CFG_PCS1G_SD);
182 /* Enable MAC RX and TX */
183 writel(DEV_MAC_CFG_MAC_ENA_RX_ENA |
184 DEV_MAC_CFG_MAC_ENA_TX_ENA,
185 regs + DEV_MAC_CFG_MAC_ENA);
187 /* Clear sgmii_mode_ena */
188 writel(0, regs + DEV_PCS1G_CFG_PCS1G_MODE);
191 * Clear sw_resolve_ena(bit 0) and set adv_ability to
192 * something meaningful just in case
194 writel(DEV_PCS1G_CFG_PCS1G_ANEG_ADV_ABILITY(0x20),
195 regs + DEV_PCS1G_CFG_PCS1G_ANEG);
197 /* Set MAC IFG Gaps */
198 writel(DEV_MAC_CFG_MAC_IFG_TX_IFG(4) |
199 DEV_MAC_CFG_MAC_IFG_RX_IFG1(5) |
200 DEV_MAC_CFG_MAC_IFG_RX_IFG2(1),
201 regs + DEV_MAC_CFG_MAC_IFG);
203 /* Set link speed and release all resets */
204 writel(DEV_DEV_CFG_DEV_RST_CTRL_SPEED_SEL(2),
205 regs + DEV_DEV_CFG_DEV_RST_CTRL);
207 /* Make VLAN aware for CPU traffic */
208 writel(ANA_CL_PORT_VLAN_CFG_AWARE_ENA |
209 ANA_CL_PORT_VLAN_CFG_POP_CNT(1) |
211 priv->regs[ANA_CL] + ANA_CL_PORT_VLAN_CFG(port));
213 /* Enable CPU port for any frame transfer */
214 setbits_le32(priv->regs[QFWD] + QFWD_SYSTEM_SWITCH_PORT_MODE(port),
215 QFWD_SYSTEM_SWITCH_PORT_MODE_PORT_ENA);
218 static int ram_init(u32 val, void __iomem *addr)
222 if (wait_for_bit_le32(addr, BIT(1), false, 2000, false)) {
223 printf("Timeout in memory reset, reg = 0x%08x\n", val);
230 static int servalt_switch_init(struct servalt_private *priv)
232 /* Initialize memories */
233 ram_init(0x3, priv->regs[QSYS] + QSYS_RAM_CTRL_RAM_INIT);
234 ram_init(0x3, priv->regs[ASM] + ASM_RAM_CTRL_RAM_INIT);
235 ram_init(0x3, priv->regs[ANA_AC] + ANA_AC_RAM_CTRL_RAM_INIT);
236 ram_init(0x3, priv->regs[REW] + REW_RAM_CTRL_RAM_INIT);
239 writel(0x1, priv->regs[ANA_AC] + ANA_AC_STAT_GLOBAL_CFG_PORT_RESET);
240 writel(0x1, priv->regs[ASM] + ASM_CFG_STAT_CFG);
242 /* Enable switch-core and queue system */
243 writel(0x1, priv->regs[QSYS] + QSYS_SYSTEM_RESET_CFG);
248 static void servalt_switch_config(struct servalt_private *priv)
250 writel(0x55555555, priv->regs[QSYS] + QSYS_CALCFG_CAL_AUTO);
252 writel(readl(priv->regs[QSYS] + QSYS_CALCFG_CAL_CTRL) |
253 QSYS_CALCFG_CAL_CTRL_CAL_MODE(8),
254 priv->regs[QSYS] + QSYS_CALCFG_CAL_CTRL);
257 static int servalt_initialize(struct servalt_private *priv)
261 /* Initialize switch memories, enable core */
262 ret = servalt_switch_init(priv);
266 servalt_switch_config(priv);
268 for (i = 0; i < MAX_PORT; i++)
269 servalt_port_init(priv, i);
271 servalt_cpu_capture_setup(priv);
277 int servalt_vlant_wait_for_completion(struct servalt_private *priv)
279 if (wait_for_bit_le32(priv->regs[LRN] + LRN_COMMON_ACCESS_CTRL,
280 LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT,
287 static int servalt_mac_table_add(struct servalt_private *priv,
288 const unsigned char mac[ETH_ALEN], int pgid)
290 u32 macl = 0, mach = 0;
293 * Set the MAC address to handle and the vlan associated in a format
294 * understood by the hardware.
296 mach |= MAC_VID << 16;
297 mach |= ((u32)mac[0]) << 8;
298 mach |= ((u32)mac[1]) << 0;
299 macl |= ((u32)mac[2]) << 24;
300 macl |= ((u32)mac[3]) << 16;
301 macl |= ((u32)mac[4]) << 8;
302 macl |= ((u32)mac[5]) << 0;
304 writel(mach, priv->regs[LRN] + LRN_COMMON_MAC_ACCESS_CFG0);
305 writel(macl, priv->regs[LRN] + LRN_COMMON_MAC_ACCESS_CFG1);
307 writel(LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_ADDR(pgid) |
308 LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_TYPE(0x3) |
309 LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_CPU_COPY |
310 LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_CPU_QU(0) |
311 LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_VLD |
312 LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_LOCKED,
313 priv->regs[LRN] + LRN_COMMON_MAC_ACCESS_CFG2);
315 writel(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT,
316 priv->regs[LRN] + LRN_COMMON_ACCESS_CTRL);
318 return servalt_vlant_wait_for_completion(priv);
321 static int servalt_write_hwaddr(struct udevice *dev)
323 struct servalt_private *priv = dev_get_priv(dev);
324 struct eth_pdata *pdata = dev_get_platdata(dev);
326 return servalt_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
329 static int servalt_start(struct udevice *dev)
331 struct servalt_private *priv = dev_get_priv(dev);
332 struct eth_pdata *pdata = dev_get_platdata(dev);
333 const unsigned char mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff,
337 ret = servalt_initialize(priv);
341 /* Set MAC address tables entries for CPU redirection */
342 ret = servalt_mac_table_add(priv, mac, PGID_BROADCAST);
346 ret = servalt_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
353 static void servalt_stop(struct udevice *dev)
357 static int servalt_send(struct udevice *dev, void *packet, int length)
359 struct servalt_private *priv = dev_get_priv(dev);
363 memset(ifh, '\0', IFH_LEN * 4);
365 /* Set DST PORT_MASK */
367 ifh[1] = htonl(0x1FFFFF);
369 /* Set DST_MODE to INJECT and UPDATE_FCS */
370 ifh[5] = htonl(0x4c0);
372 return mscc_send(priv->regs[QS], servalt_regs_qs,
373 ifh, IFH_LEN, buf, length);
376 static int servalt_recv(struct udevice *dev, int flags, uchar **packetp)
378 struct servalt_private *priv = dev_get_priv(dev);
379 u32 *rxbuf = (u32 *)net_rx_packets[0];
382 byte_cnt = mscc_recv(priv->regs[QS], servalt_regs_qs, rxbuf, IFH_LEN,
385 *packetp = net_rx_packets[0];
390 static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
394 for (i = 0; i < SERVALT_MIIM_BUS_COUNT; ++i)
395 if (miim[i].miim_base == base && miim[i].miim_size == size)
401 static void add_port_entry(struct servalt_private *priv, size_t index,
402 size_t phy_addr, struct mii_dev *bus)
404 priv->ports[index].phy_addr = phy_addr;
405 priv->ports[index].bus = bus;
408 static int servalt_probe(struct udevice *dev)
410 struct servalt_private *priv = dev_get_priv(dev);
414 phys_addr_t addr_base;
415 unsigned long addr_size;
416 ofnode eth_node, node, mdio_node;
419 struct ofnode_phandle_args phandle;
424 /* Get registers and map them to the private structure */
425 for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
426 priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
427 if (!priv->regs[i]) {
429 ("Error can't get regs base addresses for %s\n",
435 /* Initialize miim buses */
436 memset(&miim, 0x0, sizeof(struct mscc_miim_dev) *
437 SERVALT_MIIM_BUS_COUNT);
439 /* iterate all the ports and find out on which bus they are */
441 eth_node = dev_read_first_subnode(dev);
442 for (node = ofnode_first_subnode(eth_node);
444 node = ofnode_next_subnode(node)) {
445 if (ofnode_read_resource(node, 0, &res))
449 ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
452 /* Get phy address on mdio bus */
453 if (ofnode_read_resource(phandle.node, 0, &res))
455 phy_addr = res.start;
458 mdio_node = ofnode_get_parent(phandle.node);
460 if (ofnode_read_resource(mdio_node, 0, &res))
462 faddr = cpu_to_fdt32(res.start);
464 addr_base = ofnode_translate_address(mdio_node, &faddr);
465 addr_size = res.end - res.start;
467 /* If the bus is new then create a new bus */
468 if (!get_mdiobus(addr_base, addr_size))
469 priv->bus[miim_count] =
470 mscc_mdiobus_init(miim, &miim_count, addr_base,
473 /* Connect mdio bus with the port */
474 bus = get_mdiobus(addr_base, addr_size);
475 add_port_entry(priv, i, phy_addr, bus);
480 for (i = 0; i < MAX_PORT; i++) {
481 if (!priv->ports[i].bus)
484 phy_connect(priv->ports[i].bus, priv->ports[i].phy_addr, dev,
485 PHY_INTERFACE_MODE_NONE);
491 static int servalt_remove(struct udevice *dev)
493 struct servalt_private *priv = dev_get_priv(dev);
496 for (i = 0; i < SERVALT_MIIM_BUS_COUNT; i++) {
497 mdio_unregister(priv->bus[i]);
498 mdio_free(priv->bus[i]);
504 static const struct eth_ops servalt_ops = {
505 .start = servalt_start,
506 .stop = servalt_stop,
507 .send = servalt_send,
508 .recv = servalt_recv,
509 .write_hwaddr = servalt_write_hwaddr,
512 static const struct udevice_id mscc_servalt_ids[] = {
513 {.compatible = "mscc,vsc7437-switch" },
517 U_BOOT_DRIVER(servalt) = {
518 .name = "servalt-switch",
520 .of_match = mscc_servalt_ids,
521 .probe = servalt_probe,
522 .remove = servalt_remove,
524 .priv_auto_alloc_size = sizeof(struct servalt_private),
525 .platdata_auto_alloc_size = sizeof(struct eth_pdata),