drivers/net/mscc_eswitch/serval_switch.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2019 Microsemi Corporation
   4  */
   5
   6 #include <common.h>
   7 #include <config.h>
   8 #include <dm.h>
   9 #include <log.h>
  10 #include <malloc.h>
  11 #include <dm/of_access.h>
  12 #include <dm/of_addr.h>
  13 #include <fdt_support.h>
  14 #include <linux/bitops.h>
  15 #include <linux/io.h>
  16 #include <linux/ioport.h>
  17 #include <miiphy.h>
  18 #include <net.h>
  19 #include <wait_bit.h>
  20
  21 #include "mscc_xfer.h"
  22 #include "mscc_mac_table.h"
  23 #include "mscc_miim.h"
  24
  25 #define ANA_PORT_VLAN_CFG(x)                    (0xc000 + 0x100 * (x))
  26 #define         ANA_PORT_VLAN_CFG_AWARE_ENA             BIT(20)
  27 #define         ANA_PORT_VLAN_CFG_POP_CNT(x)            ((x) << 18)
  28 #define ANA_PORT_PORT_CFG(x)                    (0xc070 + 0x100 * (x))
  29 #define         ANA_PORT_PORT_CFG_RECV_ENA              BIT(6)
  30 #define ANA_PGID(x)                             (0x9c00 + 4 * (x))
  31
  32 #define HSIO_ANA_SERDES1G_DES_CFG               0x3c
  33 #define         HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)            ((x) << 1)
  34 #define         HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x)             ((x) << 5)
  35 #define         HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x)          ((x) << 8)
  36 #define         HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x)           ((x) << 13)
  37 #define HSIO_ANA_SERDES1G_IB_CFG                0x40
  38 #define         HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x)       (x)
  39 #define         HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x)             ((x) << 6)
  40 #define         HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP        BIT(9)
  41 #define         HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV             BIT(11)
  42 #define         HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM           BIT(13)
  43 #define         HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x)             ((x) << 19)
  44 #define         HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x)         ((x) << 24)
  45 #define HSIO_ANA_SERDES1G_OB_CFG                0x44
  46 #define         HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x)       (x)
  47 #define         HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)            ((x) << 4)
  48 #define         HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x)       ((x) << 10)
  49 #define         HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)            ((x) << 13)
  50 #define         HSIO_ANA_SERDES1G_OB_CFG_SLP(x)                 ((x) << 17)
  51 #define HSIO_ANA_SERDES1G_SER_CFG               0x48
  52 #define HSIO_ANA_SERDES1G_COMMON_CFG            0x4c
  53 #define         HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE            BIT(0)
  54 #define         HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE           BIT(18)
  55 #define         HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST            BIT(31)
  56 #define HSIO_ANA_SERDES1G_PLL_CFG               0x50
  57 #define         HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA               BIT(7)
  58 #define         HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x)      ((x) << 8)
  59 #define         HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2           BIT(21)
  60 #define HSIO_DIG_SERDES1G_DFT_CFG0              0x58
  61 #define HSIO_DIG_SERDES1G_MISC_CFG              0x6c
  62 #define         HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST             BIT(0)
  63 #define HSIO_MCB_SERDES1G_CFG                   0x74
  64 #define         HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT       BIT(31)
  65 #define         HSIO_MCB_SERDES1G_CFG_ADDR(x)           (x)
  66
  67 #define SYS_FRM_AGING                           0x584
  68 #define         SYS_FRM_AGING_ENA                       BIT(20)
  69 #define SYS_SYSTEM_RST_CFG                      0x518
  70 #define         SYS_SYSTEM_RST_MEM_INIT                 BIT(5)
  71 #define         SYS_SYSTEM_RST_MEM_ENA                  BIT(6)
  72 #define         SYS_SYSTEM_RST_CORE_ENA                 BIT(7)
  73 #define SYS_PORT_MODE(x)                        (0x524 + 0x4 * (x))
  74 #define         SYS_PORT_MODE_INCL_INJ_HDR(x)           ((x) << 4)
  75 #define         SYS_PORT_MODE_INCL_XTR_HDR(x)           ((x) << 2)
  76 #define SYS_PAUSE_CFG(x)                        (0x65c + 0x4 * (x))
  77 #define         SYS_PAUSE_CFG_PAUSE_ENA                 BIT(0)
  78
  79 #define QSYS_SWITCH_PORT_MODE(x)                (0x15a34 + 0x4 * (x))
  80 #define         QSYS_SWITCH_PORT_MODE_PORT_ENA          BIT(13)
  81 #define QSYS_EGR_NO_SHARING                     0x15a9c
  82 #define QSYS_QMAP                               0x15adc
  83
  84 /* Port registers */
  85 #define DEV_CLOCK_CFG                           0x0
  86 #define DEV_CLOCK_CFG_LINK_SPEED_1000                   1
  87 #define DEV_MAC_ENA_CFG                         0x10
  88 #define         DEV_MAC_ENA_CFG_RX_ENA                  BIT(4)
  89 #define         DEV_MAC_ENA_CFG_TX_ENA                  BIT(0)
  90 #define DEV_MAC_IFG_CFG                         0x24
  91 #define         DEV_MAC_IFG_CFG_TX_IFG(x)               ((x) << 8)
  92 #define         DEV_MAC_IFG_CFG_RX_IFG2(x)              ((x) << 4)
  93 #define         DEV_MAC_IFG_CFG_RX_IFG1(x)              (x)
  94 #define PCS1G_CFG                               0x3c
  95 #define         PCS1G_MODE_CFG_SGMII_MODE_ENA           BIT(0)
  96 #define PCS1G_MODE_CFG                          0x40
  97 #define PCS1G_SD_CFG                            0x44
  98 #define PCS1G_ANEG_CFG                          0x48
  99 #define         PCS1G_ANEG_CFG_ADV_ABILITY(x)           ((x) << 16)
 100
 101 #define QS_XTR_GRP_CFG(x)                       (4 * (x))
 102 #define         QS_XTR_GRP_CFG_MODE(x)                  ((x) << 2)
 103 #define         QS_XTR_GRP_CFG_BYTE_SWAP                BIT(0)
 104 #define QS_INJ_GRP_CFG(x)                       (0x24 + (x) * 4)
 105 #define         QS_INJ_GRP_CFG_MODE(x)                  ((x) << 2)
 106 #define         QS_INJ_GRP_CFG_BYTE_SWAP                BIT(0)
 107
 108 #define IFH_INJ_BYPASS          BIT(31)
 109 #define IFH_TAG_TYPE_C          0
 110 #define MAC_VID                 1
 111 #define CPU_PORT                11
 112 #define INTERNAL_PORT_MSK       0xFF
 113 #define IFH_LEN                 4
 114 #define ETH_ALEN                6
 115 #define PGID_BROADCAST          13
 116 #define PGID_UNICAST            14
 117
 118 static const char *const regs_names[] = {
 119         "port0", "port1", "port2", "port3", "port4", "port5", "port6",
 120         "port7", "port8", "port9", "port10",
 121         "ana", "qs", "qsys", "rew", "sys", "hsio",
 122 };
 123
 124 #define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
 125 #define MAX_PORT 11
 126
 127 enum serval_ctrl_regs {
 128         ANA = MAX_PORT,
 129         QS,
 130         QSYS,
 131         REW,
 132         SYS,
 133         HSIO,
 134 };
 135
 136 #define SERVAL_MIIM_BUS_COUNT 2
 137
 138 struct serval_phy_port_t {
 139         size_t phy_addr;
 140         struct mii_dev *bus;
 141         u8 serdes_index;
 142         u8 phy_mode;
 143 };
 144
 145 struct serval_private {
 146         void __iomem *regs[REGS_NAMES_COUNT];
 147         struct mii_dev *bus[SERVAL_MIIM_BUS_COUNT];
 148         struct serval_phy_port_t ports[MAX_PORT];
 149 };
 150
 151 static const unsigned long serval_regs_qs[] = {
 152         [MSCC_QS_XTR_RD] = 0x8,
 153         [MSCC_QS_XTR_FLUSH] = 0x18,
 154         [MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
 155         [MSCC_QS_INJ_WR] = 0x2c,
 156         [MSCC_QS_INJ_CTRL] = 0x34,
 157 };
 158
 159 static const unsigned long serval_regs_ana_table[] = {
 160         [MSCC_ANA_TABLES_MACHDATA] = 0x9b34,
 161         [MSCC_ANA_TABLES_MACLDATA] = 0x9b38,
 162         [MSCC_ANA_TABLES_MACACCESS] = 0x9b3c,
 163 };
 164
 165 static struct mscc_miim_dev miim[SERVAL_MIIM_BUS_COUNT];
 166 static int miim_count = -1;
 167
 168 static void serval_cpu_capture_setup(struct serval_private *priv)
 169 {
 170         int i;
 171
 172         /* map the 8 CPU extraction queues to CPU port 11 */
 173         writel(0, priv->regs[QSYS] + QSYS_QMAP);
 174
 175         for (i = 0; i <= 1; i++) {
 176                 /*
 177                  * Do byte-swap and expect status after last data word
 178                  * Extraction: Mode: manual extraction) | Byte_swap
 179                  */
 180                 writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP,
 181                        priv->regs[QS] + QS_XTR_GRP_CFG(i));
 182                 /*
 183                  * Injection: Mode: manual extraction | Byte_swap
 184                  */
 185                 writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP,
 186                        priv->regs[QS] + QS_INJ_GRP_CFG(i));
 187         }
 188
 189         for (i = 0; i <= 1; i++)
 190                 /* Enable IFH insertion/parsing on CPU ports */
 191                 writel(SYS_PORT_MODE_INCL_INJ_HDR(1) |
 192                        SYS_PORT_MODE_INCL_XTR_HDR(1),
 193                        priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
 194         /*
 195          * Setup the CPU port as VLAN aware to support switching frames
 196          * based on tags
 197          */
 198         writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
 199                MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
 200
 201         /* Disable learning (only RECV_ENA must be set) */
 202         writel(ANA_PORT_PORT_CFG_RECV_ENA,
 203                priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
 204
 205         /* Enable switching to/from cpu port */
 206         setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
 207                      QSYS_SWITCH_PORT_MODE_PORT_ENA);
 208
 209         /* No pause on CPU port - not needed (off by default) */
 210         clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
 211                      SYS_PAUSE_CFG_PAUSE_ENA);
 212
 213         setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
 214 }
 215
 216 static void serval_port_init(struct serval_private *priv, int port)
 217 {
 218         void __iomem *regs = priv->regs[port];
 219
 220         /* Enable PCS */
 221         writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);
 222
 223         /* Disable Signal Detect */
 224         writel(0, regs + PCS1G_SD_CFG);
 225
 226         /* Enable MAC RX and TX */
 227         writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA,
 228                regs + DEV_MAC_ENA_CFG);
 229
 230         /* Clear sgmii_mode_ena */
 231         writel(0, regs + PCS1G_MODE_CFG);
 232
 233         /*
 234          * Clear sw_resolve_ena(bit 0) and set adv_ability to
 235          * something meaningful just in case
 236          */
 237         writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);
 238
 239         /* Set MAC IFG Gaps */
 240         writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) |
 241                DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);
 242
 243         /* Set link speed and release all resets */
 244         writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);
 245
 246         /* Make VLAN aware for CPU traffic */
 247         writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
 248                MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
 249
 250         /* Enable the port in the core */
 251         setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port),
 252                      QSYS_SWITCH_PORT_MODE_PORT_ENA);
 253 }
 254
 255 static void serdes_write(void __iomem *base, u32 addr)
 256 {
 257         u32 data;
 258
 259         writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT |
 260                HSIO_MCB_SERDES1G_CFG_ADDR(addr),
 261                base + HSIO_MCB_SERDES1G_CFG);
 262
 263         do {
 264                 data = readl(base + HSIO_MCB_SERDES1G_CFG);
 265         } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
 266 }
 267
 268 static void serdes1g_setup(void __iomem *base, uint32_t addr,
 269                            phy_interface_t interface)
 270 {
 271         writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG);
 272         writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0);
 273         writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) |
 274                HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) |
 275                HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP |
 276                HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM |
 277                HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1),
 278                base + HSIO_ANA_SERDES1G_IB_CFG);
 279         writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) |
 280                HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) |
 281                HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) |
 282                HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6),
 283                base + HSIO_ANA_SERDES1G_DES_CFG);
 284         writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) |
 285                HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) |
 286                HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) |
 287                HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) |
 288                HSIO_ANA_SERDES1G_OB_CFG_SLP(3),
 289                base + HSIO_ANA_SERDES1G_OB_CFG);
 290         writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
 291                HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE,
 292                base + HSIO_ANA_SERDES1G_COMMON_CFG);
 293         writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA |
 294                HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) |
 295                HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2,
 296                base + HSIO_ANA_SERDES1G_PLL_CFG);
 297         writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST,
 298                base + HSIO_DIG_SERDES1G_MISC_CFG);
 299         serdes_write(base, addr);
 300
 301         writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
 302                HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE |
 303                HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST,
 304                base + HSIO_ANA_SERDES1G_COMMON_CFG);
 305         serdes_write(base, addr);
 306
 307         writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG);
 308         serdes_write(base, addr);
 309 }
 310
 311 static void serdes_setup(struct serval_private *priv)
 312 {
 313         size_t mask;
 314         int i = 0;
 315
 316         for (i = 0; i < MAX_PORT; ++i) {
 317                 if (!priv->ports[i].bus)
 318                         continue;
 319
 320                 mask = BIT(priv->ports[i].serdes_index);
 321                 serdes1g_setup(priv->regs[HSIO], mask,
 322                                priv->ports[i].phy_mode);
 323         }
 324 }
 325
 326 static int serval_switch_init(struct serval_private *priv)
 327 {
 328         /* Reset switch & memories */
 329         writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
 330                priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
 331
 332         if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
 333                               SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
 334                 pr_err("Timeout in memory reset\n");
 335                 return -EIO;
 336         }
 337
 338         /* Enable switch core */
 339         setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
 340                      SYS_SYSTEM_RST_CORE_ENA);
 341
 342         serdes_setup(priv);
 343
 344         return 0;
 345 }
 346
 347 static int serval_initialize(struct serval_private *priv)
 348 {
 349         int ret, i;
 350
 351         /* Initialize switch memories, enable core */
 352         ret = serval_switch_init(priv);
 353         if (ret)
 354                 return ret;
 355
 356         /* Flush queues */
 357         mscc_flush(priv->regs[QS], serval_regs_qs);
 358
 359         /* Setup frame ageing - "2 sec" - The unit is 6.5us on serval */
 360         writel(SYS_FRM_AGING_ENA | (20000000 / 65),
 361                priv->regs[SYS] + SYS_FRM_AGING);
 362
 363         for (i = 0; i < MAX_PORT; i++)
 364                 serval_port_init(priv, i);
 365
 366         serval_cpu_capture_setup(priv);
 367
 368         debug("Ports enabled\n");
 369
 370         return 0;
 371 }
 372
 373 static int serval_write_hwaddr(struct udevice *dev)
 374 {
 375         struct serval_private *priv = dev_get_priv(dev);
 376         struct eth_pdata *pdata = dev_get_platdata(dev);
 377
 378         mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
 379                            pdata->enetaddr, PGID_UNICAST);
 380
 381         writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
 382
 383         return 0;
 384 }
 385
 386 static int serval_start(struct udevice *dev)
 387 {
 388         struct serval_private *priv = dev_get_priv(dev);
 389         struct eth_pdata *pdata = dev_get_platdata(dev);
 390         const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
 391                                               0xff };
 392         int ret;
 393
 394         ret = serval_initialize(priv);
 395         if (ret)
 396                 return ret;
 397
 398         /* Set MAC address tables entries for CPU redirection */
 399         mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table, mac,
 400                            PGID_BROADCAST);
 401
 402         writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
 403                priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
 404
 405         /* It should be setup latter in serval_write_hwaddr */
 406         mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
 407                            pdata->enetaddr, PGID_UNICAST);
 408
 409         writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
 410         return 0;
 411 }
 412
 413 static void serval_stop(struct udevice *dev)
 414 {
 415         writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
 416         writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
 417 }
 418
 419 static int serval_send(struct udevice *dev, void *packet, int length)
 420 {
 421         struct serval_private *priv = dev_get_priv(dev);
 422         u32 ifh[IFH_LEN];
 423         u32 *buf = packet;
 424
 425         /*
 426          * Generate the IFH for frame injection
 427          *
 428          * The IFH is a 128bit-value
 429          * bit 127: bypass the analyzer processing
 430          * bit 57-67: destination mask
 431          * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
 432          * bit 20-27: cpu extraction queue mask
 433          * bit 16: tag type 0: C-tag, 1: S-tag
 434          * bit 0-11: VID
 435          */
 436         ifh[0] = IFH_INJ_BYPASS;
 437         ifh[1] = (0x07);
 438         ifh[2] = (0x7f) << 25;
 439         ifh[3] = (IFH_TAG_TYPE_C << 16);
 440
 441         return mscc_send(priv->regs[QS], serval_regs_qs,
 442                          ifh, IFH_LEN, buf, length);
 443 }
 444
 445 static int serval_recv(struct udevice *dev, int flags, uchar **packetp)
 446 {
 447         struct serval_private *priv = dev_get_priv(dev);
 448         u32 *rxbuf = (u32 *)net_rx_packets[0];
 449         int byte_cnt = 0;
 450
 451         byte_cnt = mscc_recv(priv->regs[QS], serval_regs_qs, rxbuf, IFH_LEN,
 452                              false);
 453
 454         *packetp = net_rx_packets[0];
 455
 456         return byte_cnt;
 457 }
 458
 459 static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
 460 {
 461         int i = 0;
 462
 463         for (i = 0; i < SERVAL_MIIM_BUS_COUNT; ++i)
 464                 if (miim[i].miim_base == base && miim[i].miim_size == size)
 465                         return miim[i].bus;
 466
 467         return NULL;
 468 }
 469
 470 static void add_port_entry(struct serval_private *priv, size_t index,
 471                            size_t phy_addr, struct mii_dev *bus,
 472                            u8 serdes_index, u8 phy_mode)
 473 {
 474         priv->ports[index].phy_addr = phy_addr;
 475         priv->ports[index].bus = bus;
 476         priv->ports[index].serdes_index = serdes_index;
 477         priv->ports[index].phy_mode = phy_mode;
 478 }
 479
 480 static int serval_probe(struct udevice *dev)
 481 {
 482         struct serval_private *priv = dev_get_priv(dev);
 483         int i, ret;
 484         struct resource res;
 485         fdt32_t faddr;
 486         phys_addr_t addr_base;
 487         unsigned long addr_size;
 488         ofnode eth_node, node, mdio_node;
 489         size_t phy_addr;
 490         struct mii_dev *bus;
 491         struct ofnode_phandle_args phandle;
 492         struct phy_device *phy;
 493
 494         if (!priv)
 495                 return -EINVAL;
 496
 497         /* Get registers and map them to the private structure */
 498         for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
 499                 priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
 500                 if (!priv->regs[i]) {
 501                         debug
 502                             ("Error can't get regs base addresses for %s\n",
 503                              regs_names[i]);
 504                         return -ENOMEM;
 505                 }
 506         }
 507
 508         /* Initialize miim buses */
 509         memset(&miim, 0x0, sizeof(miim) * SERVAL_MIIM_BUS_COUNT);
 510
 511         /* iterate all the ports and find out on which bus they are */
 512         i = 0;
 513         eth_node = dev_read_first_subnode(dev);
 514         for (node = ofnode_first_subnode(eth_node);
 515              ofnode_valid(node);
 516              node = ofnode_next_subnode(node)) {
 517                 if (ofnode_read_resource(node, 0, &res))
 518                         return -ENOMEM;
 519                 i = res.start;
 520
 521                 ret = ofnode_parse_phandle_with_args(node, "phy-handle", NULL,
 522                                                      0, 0, &phandle);
 523                 if (ret)
 524                         continue;
 525
 526                 /* Get phy address on mdio bus */
 527                 if (ofnode_read_resource(phandle.node, 0, &res))
 528                         return -ENOMEM;
 529                 phy_addr = res.start;
 530
 531                 /* Get mdio node */
 532                 mdio_node = ofnode_get_parent(phandle.node);
 533
 534                 if (ofnode_read_resource(mdio_node, 0, &res))
 535                         return -ENOMEM;
 536                 faddr = cpu_to_fdt32(res.start);
 537
 538                 addr_base = ofnode_translate_address(mdio_node, &faddr);
 539                 addr_size = res.end - res.start;
 540
 541                 /* If the bus is new then create a new bus */
 542                 if (!get_mdiobus(addr_base, addr_size))
 543                         priv->bus[miim_count] =
 544                                 mscc_mdiobus_init(miim, &miim_count, addr_base,
 545                                                   addr_size);
 546
 547                 /* Connect mdio bus with the port */
 548                 bus = get_mdiobus(addr_base, addr_size);
 549
 550                 /* Get serdes info */
 551                 ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
 552                                                      3, 0, &phandle);
 553                 if (ret)
 554                         return -ENOMEM;
 555
 556                 add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
 557                                phandle.args[2]);
 558         }
 559
 560         for (i = 0; i < MAX_PORT; i++) {
 561                 if (!priv->ports[i].bus)
 562                         continue;
 563
 564                 phy = phy_connect(priv->ports[i].bus,
 565                                   priv->ports[i].phy_addr, dev,
 566                                   PHY_INTERFACE_MODE_NONE);
 567                 if (phy)
 568                         board_phy_config(phy);
 569         }
 570
 571         return 0;
 572 }
 573
 574 static int serval_remove(struct udevice *dev)
 575 {
 576         struct serval_private *priv = dev_get_priv(dev);
 577         int i;
 578
 579         for (i = 0; i < SERVAL_MIIM_BUS_COUNT; i++) {
 580                 mdio_unregister(priv->bus[i]);
 581                 mdio_free(priv->bus[i]);
 582         }
 583
 584         return 0;
 585 }
 586
 587 static const struct eth_ops serval_ops = {
 588         .start        = serval_start,
 589         .stop         = serval_stop,
 590         .send         = serval_send,
 591         .recv         = serval_recv,
 592         .write_hwaddr = serval_write_hwaddr,
 593 };
 594
 595 static const struct udevice_id mscc_serval_ids[] = {
 596         {.compatible = "mscc,vsc7418-switch"},
 597         { /* Sentinel */ }
 598 };
 599
 600 U_BOOT_DRIVER(serval) = {
 601         .name                           = "serval-switch",
 602         .id                             = UCLASS_ETH,
 603         .of_match                       = mscc_serval_ids,
 604         .probe                          = serval_probe,
 605         .remove                         = serval_remove,
 606         .ops                            = &serval_ops,
 607         .priv_auto_alloc_size           = sizeof(struct serval_private),
 608         .platdata_auto_alloc_size       = sizeof(struct eth_pdata),
 609 };