1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Microsemi Corporation
10 #define MIIM_STATUS 0x0
11 #define MIIM_STAT_BUSY BIT(3)
13 #define MIIM_CMD_SCAN BIT(0)
14 #define MIIM_CMD_OPR_WRITE BIT(1)
15 #define MIIM_CMD_OPR_READ BIT(2)
16 #define MIIM_CMD_SINGLE_SCAN BIT(3)
17 #define MIIM_CMD_WRDATA(x) ((x) << 4)
18 #define MIIM_CMD_REGAD(x) ((x) << 20)
19 #define MIIM_CMD_PHYAD(x) ((x) << 25)
20 #define MIIM_CMD_VLD BIT(31)
22 #define MIIM_DATA_ERROR (0x2 << 16)
24 static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
26 return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY,
30 int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
32 struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
36 ret = mscc_miim_wait_ready(miim);
40 writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
41 MIIM_CMD_REGAD(reg) | MIIM_CMD_OPR_READ,
42 miim->regs + MIIM_CMD);
44 ret = mscc_miim_wait_ready(miim);
48 val = readl(miim->regs + MIIM_DATA);
49 if (val & MIIM_DATA_ERROR) {
59 int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
62 struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
65 ret = mscc_miim_wait_ready(miim);
69 writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
70 MIIM_CMD_REGAD(reg) | MIIM_CMD_WRDATA(val) |
71 MIIM_CMD_OPR_WRITE, miim->regs + MIIM_CMD);
76 struct mii_dev *mscc_mdiobus_init(struct mscc_miim_dev *miim, int *miim_count,
77 phys_addr_t miim_base,
78 unsigned long miim_size)
88 sprintf(bus->name, "miim-bus%d", *miim_count);
90 miim[*miim_count].regs = ioremap(miim_base, miim_size);
91 miim[*miim_count].miim_base = miim_base;
92 miim[*miim_count].miim_size = miim_size;
93 bus->priv = &miim[*miim_count];
94 bus->read = mscc_miim_read;
95 bus->write = mscc_miim_write;
97 if (mdio_register(bus))
100 miim[*miim_count].bus = bus;