1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
13 #include <asm/cpm_8xx.h>
15 #include <linux/delay.h>
18 #include <linux/mii.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 /* define WANT_MII when MII support is required */
23 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
32 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
33 #error "CONFIG_MII has to be defined!"
38 #if defined(CONFIG_RMII) && !defined(WANT_MII)
39 #error RMII support is unusable without a working PHY.
42 #ifdef CONFIG_SYS_DISCOVER_PHY
43 static int mii_discover_phy(struct eth_device *dev);
46 int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
47 int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
50 static struct ether_fcc_info_s
59 #if defined(CONFIG_ETHER_ON_FEC1)
62 offsetof(immap_t, im_cpm.cp_fec1),
69 #if defined(CONFIG_ETHER_ON_FEC2)
72 offsetof(immap_t, im_cpm.cp_fec2),
80 /* Ethernet Transmit and Receive Buffers */
81 #define DBUF_LENGTH 1520
87 #define PKT_MAXBUF_SIZE 1518
88 #define PKT_MINBUF_SIZE 64
89 #define PKT_MAXBLR_SIZE 1520
92 static char txbuf[DBUF_LENGTH] __aligned(8);
94 #error txbuf must be aligned.
97 static uint rxIdx; /* index of the current RX buffer */
98 static uint txIdx; /* index of the current TX buffer */
101 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
102 * immr->udata_bd address on Dual-Port RAM
103 * Provide for Double Buffering
106 struct common_buf_desc {
107 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
108 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
111 static struct common_buf_desc __iomem *rtx;
113 static int fec_send(struct eth_device *dev, void *packet, int length);
114 static int fec_recv(struct eth_device *dev);
115 static int fec_init(struct eth_device *dev, bd_t *bd);
116 static void fec_halt(struct eth_device *dev);
117 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
118 static void __mii_init(void);
121 int fec_initialize(bd_t *bis)
123 struct eth_device *dev;
124 struct ether_fcc_info_s *efis;
127 for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
128 dev = malloc(sizeof(*dev));
132 memset(dev, 0, sizeof(*dev));
134 /* for FEC1 make sure that the name of the interface is the same
135 as the old one for compatibility reasons */
137 strcpy(dev->name, "FEC");
139 sprintf(dev->name, "FEC%d",
140 ether_fcc_info[i].ether_index + 1);
142 efis = ðer_fcc_info[i];
145 * reset actual phy addr
147 efis->actual_phy_addr = -1;
150 dev->init = fec_init;
151 dev->halt = fec_halt;
152 dev->send = fec_send;
153 dev->recv = fec_recv;
157 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
159 struct mii_dev *mdiodev = mdio_alloc();
162 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
163 mdiodev->read = fec8xx_miiphy_read;
164 mdiodev->write = fec8xx_miiphy_write;
166 retval = mdio_register(mdiodev);
174 static int fec_send(struct eth_device *dev, void *packet, int length)
177 struct ether_fcc_info_s *efis = dev->priv;
178 fec_t __iomem *fecp =
179 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
185 while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
191 printf("TX not ready\n");
193 out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
194 out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
195 setbits_be16(&rtx->txbd[txIdx].cbd_sc,
196 BD_ENET_TX_READY | BD_ENET_TX_LAST);
198 /* Activate transmit Buffer Descriptor polling */
199 /* Descriptor polling active */
200 out_be32(&fecp->fec_x_des_active, 0x01000000);
203 while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
209 printf("TX timeout\n");
211 /* return only status bits */;
212 rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
214 txIdx = (txIdx + 1) % TX_BUF_CNT;
219 static int fec_recv(struct eth_device *dev)
221 struct ether_fcc_info_s *efis = dev->priv;
222 fec_t __iomem *fecp =
223 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
227 /* section 16.9.23.2 */
228 if (in_be16(&rtx->rxbd[rxIdx].cbd_sc) & BD_ENET_RX_EMPTY) {
230 break; /* nothing received - leave for() loop */
233 length = in_be16(&rtx->rxbd[rxIdx].cbd_datlen);
235 if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) {
236 uchar *rx = net_rx_packets[rxIdx];
240 #if defined(CONFIG_CMD_CDP)
241 if ((rx[0] & 1) != 0 &&
242 memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&
243 !is_cdp_packet((uchar *)rx))
247 * Pass the packet up to the protocol layers.
250 net_process_received_packet(rx, length);
253 /* Give the buffer back to the FEC. */
254 out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0);
256 /* wrap around buffer index when necessary */
257 if ((rxIdx + 1) >= PKTBUFSRX) {
258 out_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc,
259 BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
262 out_be16(&rtx->rxbd[rxIdx].cbd_sc, BD_ENET_RX_EMPTY);
266 /* Try to fill Buffer Descriptors */
267 /* Descriptor polling active */
268 out_be32(&fecp->fec_r_des_active, 0x01000000);
274 /**************************************************************
276 * FEC Ethernet Initialization Routine
278 *************************************************************/
280 #define FEC_ECNTRL_PINMUX 0x00000004
281 #define FEC_ECNTRL_ETHER_EN 0x00000002
282 #define FEC_ECNTRL_RESET 0x00000001
284 #define FEC_RCNTRL_BC_REJ 0x00000010
285 #define FEC_RCNTRL_PROM 0x00000008
286 #define FEC_RCNTRL_MII_MODE 0x00000004
287 #define FEC_RCNTRL_DRT 0x00000002
288 #define FEC_RCNTRL_LOOP 0x00000001
290 #define FEC_TCNTRL_FDEN 0x00000004
291 #define FEC_TCNTRL_HBC 0x00000002
292 #define FEC_TCNTRL_GTS 0x00000001
294 #define FEC_RESET_DELAY 50
296 #if defined(CONFIG_RMII)
298 static inline void fec_10Mbps(struct eth_device *dev)
300 struct ether_fcc_info_s *efis = dev->priv;
301 int fecidx = efis->ether_index;
302 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
303 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
305 if ((unsigned int)fecidx >= 2)
308 setbits_be32(&immr->im_cpm.cp_cptr, mask);
311 static inline void fec_100Mbps(struct eth_device *dev)
313 struct ether_fcc_info_s *efis = dev->priv;
314 int fecidx = efis->ether_index;
315 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
316 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
318 if ((unsigned int)fecidx >= 2)
321 clrbits_be32(&immr->im_cpm.cp_cptr, mask);
326 static inline void fec_full_duplex(struct eth_device *dev)
328 struct ether_fcc_info_s *efis = dev->priv;
329 fec_t __iomem *fecp =
330 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
332 clrbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
333 setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
336 static inline void fec_half_duplex(struct eth_device *dev)
338 struct ether_fcc_info_s *efis = dev->priv;
339 fec_t __iomem *fecp =
340 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
342 setbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
343 clrbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
346 static void fec_pin_init(int fecidx)
349 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
352 * Set MII speed to 2.5 MHz or slightly below.
354 * According to the MPC860T (Rev. D) Fast ethernet controller user
356 * the MII management interface clock must be less than or equal
358 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
359 * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
361 * All MII configuration is done via FEC1 registers:
363 out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed,
364 ((bd->bi_intfreq + 4999999) / 5000000) << 1);
366 #if defined(CONFIG_MPC885) && defined(WANT_MII)
367 /* use MDC for MII */
368 setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);
369 clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);
373 #if defined(CONFIG_ETHER_ON_FEC1)
375 #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
377 #if !defined(CONFIG_RMII)
379 setbits_be16(&immr->im_ioport.iop_papar, 0xf830);
380 setbits_be16(&immr->im_ioport.iop_padir, 0x0830);
381 clrbits_be16(&immr->im_ioport.iop_padir, 0xf000);
383 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001);
384 clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00001001);
386 setbits_be16(&immr->im_ioport.iop_pcpar, 0x000c);
387 clrbits_be16(&immr->im_ioport.iop_pcdir, 0x000c);
389 setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003);
390 setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003);
391 clrbits_be32(&immr->im_cpm.cp_peso, 0x00000003);
393 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
397 #if !defined(CONFIG_FEC1_PHY_NORXERR)
398 setbits_be16(&immr->im_ioport.iop_papar, 0x1000);
399 clrbits_be16(&immr->im_ioport.iop_padir, 0x1000);
401 setbits_be16(&immr->im_ioport.iop_papar, 0xe810);
402 setbits_be16(&immr->im_ioport.iop_padir, 0x0810);
403 clrbits_be16(&immr->im_ioport.iop_padir, 0xe000);
405 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001);
406 clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00000001);
408 setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
409 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000050);
411 #endif /* !CONFIG_RMII */
415 * Configure all of port D for MII.
417 out_be16(&immr->im_ioport.iop_pdpar, 0x1fff);
418 out_be16(&immr->im_ioport.iop_pddir, 0x1fff);
420 #if defined(CONFIG_TARGET_MCR3000)
421 out_be16(&immr->im_ioport.iop_papar, 0xBBFF);
422 out_be16(&immr->im_ioport.iop_padir, 0x04F0);
423 out_be16(&immr->im_ioport.iop_paodr, 0x0000);
425 out_be32(&immr->im_cpm.cp_pbpar, 0x000133FF);
426 out_be32(&immr->im_cpm.cp_pbdir, 0x0003BF0F);
427 out_be16(&immr->im_cpm.cp_pbodr, 0x0000);
429 out_be16(&immr->im_ioport.iop_pcpar, 0x0400);
430 out_be16(&immr->im_ioport.iop_pcdir, 0x0080);
431 out_be16(&immr->im_ioport.iop_pcso , 0x0D53);
432 out_be16(&immr->im_ioport.iop_pcint, 0x0000);
434 out_be16(&immr->im_ioport.iop_pdpar, 0x03FE);
435 out_be16(&immr->im_ioport.iop_pddir, 0x1C09);
437 setbits_be32(&immr->im_ioport.utmode, 0x80);
441 #endif /* CONFIG_ETHER_ON_FEC1 */
442 } else if (fecidx == 1) {
443 #if defined(CONFIG_ETHER_ON_FEC2)
445 #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
447 #if !defined(CONFIG_RMII)
448 setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);
449 setbits_be32(&immr->im_cpm.cp_pedir, 0x0003fffc);
450 clrbits_be32(&immr->im_cpm.cp_peso, 0x000087fc);
451 setbits_be32(&immr->im_cpm.cp_peso, 0x00037800);
453 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
456 #if !defined(CONFIG_FEC2_PHY_NORXERR)
457 setbits_be32(&immr->im_cpm.cp_pepar, 0x00000010);
458 setbits_be32(&immr->im_cpm.cp_pedir, 0x00000010);
459 clrbits_be32(&immr->im_cpm.cp_peso, 0x00000010);
461 setbits_be32(&immr->im_cpm.cp_pepar, 0x00039620);
462 setbits_be32(&immr->im_cpm.cp_pedir, 0x00039620);
463 setbits_be32(&immr->im_cpm.cp_peso, 0x00031000);
464 clrbits_be32(&immr->im_cpm.cp_peso, 0x00008620);
466 setbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
467 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);
468 #endif /* CONFIG_RMII */
470 #endif /* CONFIG_MPC885 */
472 #endif /* CONFIG_ETHER_ON_FEC2 */
476 static int fec_reset(fec_t __iomem *fecp)
481 * A delay is required between a reset of the FEC block and
482 * initialization of other FEC registers because the reset takes
483 * some time to complete. If you don't delay, subsequent writes
484 * to FEC registers might get killed by the reset routine which is
488 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
489 for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
490 (i < FEC_RESET_DELAY); ++i)
493 if (i == FEC_RESET_DELAY)
499 static int fec_init(struct eth_device *dev, bd_t *bd)
501 struct ether_fcc_info_s *efis = dev->priv;
502 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
503 fec_t __iomem *fecp =
504 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
507 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
508 /* the MII interface is connected to FEC1
509 * so for the miiphy_xxx function to work we must
510 * call mii_init since fec_halt messes the thing up
512 if (efis->ether_index != 0)
516 if (fec_reset(fecp) < 0)
517 printf("FEC_RESET_DELAY timeout\n");
519 /* We use strictly polling mode only
521 out_be32(&fecp->fec_imask, 0);
523 /* Clear any pending interrupt
525 out_be32(&fecp->fec_ievent, 0xffc0);
527 /* No need to set the IVEC register */
529 /* Set station address
531 #define ea dev->enetaddr
532 out_be32(&fecp->fec_addr_low, (ea[0] << 24) | (ea[1] << 16) |
533 (ea[2] << 8) | ea[3]);
534 out_be16(&fecp->fec_addr_high, (ea[4] << 8) | ea[5]);
537 #if defined(CONFIG_CMD_CDP)
539 * Turn on multicast address hash table
541 out_be32(&fecp->fec_hash_table_high, 0xffffffff);
542 out_be32(&fecp->fec_hash_table_low, 0xffffffff);
544 /* Clear multicast address hash table
546 out_be32(&fecp->fec_hash_table_high, 0);
547 out_be32(&fecp->fec_hash_table_low, 0);
550 /* Set maximum receive buffer size.
552 out_be32(&fecp->fec_r_buff_size, PKT_MAXBLR_SIZE);
554 /* Set maximum frame length
556 out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
559 * Setup Buffers and Buffer Descriptors
565 rtx = (struct common_buf_desc __iomem *)
566 (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
568 * Setup Receiver Buffer Descriptors (13.14.24.18)
572 for (i = 0; i < PKTBUFSRX; i++) {
573 out_be16(&rtx->rxbd[i].cbd_sc, BD_ENET_RX_EMPTY);
574 out_be16(&rtx->rxbd[i].cbd_datlen, 0); /* Reset */
575 out_be32(&rtx->rxbd[i].cbd_bufaddr, (uint)net_rx_packets[i]);
577 setbits_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, BD_ENET_RX_WRAP);
580 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
584 for (i = 0; i < TX_BUF_CNT; i++) {
585 out_be16(&rtx->txbd[i].cbd_sc, BD_ENET_TX_LAST | BD_ENET_TX_TC);
586 out_be16(&rtx->txbd[i].cbd_datlen, 0); /* Reset */
587 out_be32(&rtx->txbd[i].cbd_bufaddr, (uint)txbuf);
589 setbits_be16(&rtx->txbd[TX_BUF_CNT - 1].cbd_sc, BD_ENET_TX_WRAP);
591 /* Set receive and transmit descriptor base
593 out_be32(&fecp->fec_r_des_start, (__force unsigned int)rtx->rxbd);
594 out_be32(&fecp->fec_x_des_start, (__force unsigned int)rtx->txbd);
598 /* Half duplex mode */
599 out_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT);
600 out_be32(&fecp->fec_x_cntrl, 0);
602 /* Enable big endian and don't care about SDMA FC.
604 out_be32(&fecp->fec_fun_code, 0x78000000);
607 * Setup the pin configuration of the FEC
609 fec_pin_init(efis->ether_index);
615 * Now enable the transmit and receive processing
617 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
619 if (efis->phy_addr == -1) {
620 #ifdef CONFIG_SYS_DISCOVER_PHY
622 * wait for the PHY to wake up after reset
624 efis->actual_phy_addr = mii_discover_phy(dev);
626 if (efis->actual_phy_addr == -1) {
627 printf("Unable to discover phy!\n");
631 efis->actual_phy_addr = -1;
634 efis->actual_phy_addr = efis->phy_addr;
637 #if defined(CONFIG_MII) && defined(CONFIG_RMII)
639 * adapt the RMII speed to the speed of the phy
641 if (miiphy_speed(dev->name, efis->actual_phy_addr) == _100BASET)
647 #if defined(CONFIG_MII)
649 * adapt to the half/full speed settings
651 if (miiphy_duplex(dev->name, efis->actual_phy_addr) == FULL)
652 fec_full_duplex(dev);
654 fec_half_duplex(dev);
657 /* And last, try to fill Rx Buffer Descriptors */
658 /* Descriptor polling active */
659 out_be32(&fecp->fec_r_des_active, 0x01000000);
661 efis->initialized = 1;
667 static void fec_halt(struct eth_device *dev)
669 struct ether_fcc_info_s *efis = dev->priv;
670 fec_t __iomem *fecp =
671 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
674 /* avoid halt if initialized; mii gets stuck otherwise */
675 if (!efis->initialized)
679 * A delay is required between a reset of the FEC block and
680 * initialization of other FEC registers because the reset takes
681 * some time to complete. If you don't delay, subsequent writes
682 * to FEC registers might get killed by the reset routine which is
686 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
687 for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
688 (i < FEC_RESET_DELAY); ++i)
691 if (i == FEC_RESET_DELAY) {
692 printf("FEC_RESET_DELAY timeout\n");
696 efis->initialized = 0;
699 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
701 /* Make MII read/write commands for the FEC.
704 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
707 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
708 (REG & 0x1f) << 18) | \
711 /* Interrupt events/masks.
713 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
714 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
715 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
716 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
717 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
718 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
719 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
720 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
721 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
722 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
724 /* send command to phy using mii, wait for result */
726 mii_send(uint mii_cmd)
731 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
733 ep = &immr->im_cpm.cp_fec;
735 out_be32(&ep->fec_mii_data, mii_cmd); /* command to phy */
737 /* wait for mii complete */
739 while (!(in_be32(&ep->fec_ievent) & FEC_ENET_MII)) {
741 printf("mii_send STUCK!\n");
745 mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
746 out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
747 return mii_reply & 0xffff; /* data read from phy */
751 #if defined(CONFIG_SYS_DISCOVER_PHY)
752 static int mii_discover_phy(struct eth_device *dev)
754 #define MAX_PHY_PASSES 11
760 phyaddr = -1; /* didn't find a PHY yet */
761 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
763 /* PHY may need more time to recover from reset.
764 * The LXT970 needs 50ms typical, no maximum is
765 * specified, so wait 10ms before try again.
766 * With 11 passes this gives it 100ms to wake up.
768 udelay(10000); /* wait 10ms */
770 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
771 phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
772 if (phytype != 0xffff) {
774 phytype |= mii_send(mk_mii_read(phyno,
780 printf("No PHY device found.\n");
784 #endif /* CONFIG_SYS_DISCOVER_PHY */
786 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
788 /****************************************************************************
789 * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
790 * This function is a subset of eth_init
791 ****************************************************************************
793 static void __mii_init(void)
795 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
796 fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
798 if (fec_reset(fecp) < 0)
799 printf("FEC_RESET_DELAY timeout\n");
801 /* We use strictly polling mode only
803 out_be32(&fecp->fec_imask, 0);
805 /* Clear any pending interrupt
807 out_be32(&fecp->fec_ievent, 0xffc0);
809 /* Now enable the transmit and receive processing
811 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
820 /* Setup the pin configuration of the FEC(s)
822 for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
823 fec_pin_init(ether_fcc_info[i].ether_index);
826 /*****************************************************************************
827 * Read and write a MII PHY register, routines used by MII Utilities
829 * FIXME: These routines are expected to return 0 on success, but mii_send
830 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
831 * no PHY connected...
832 * For now always return 0.
833 * FIXME: These routines only work after calling eth_init() at least once!
834 * Otherwise they hang in mii_send() !!! Sorry!
835 *****************************************************************************/
837 int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
839 unsigned short value = 0;
840 short rdreg; /* register working value */
842 rdreg = mii_send(mk_mii_read(addr, reg));
848 int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
851 (void)mii_send(mk_mii_write(addr, reg, value));