2 * (C) Copyright 2003 - 2009
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Derived from the MPC8xx driver's header file.
8 #ifndef __MPC512X_FEC_H
9 #define __MPC512X_FEC_H
14 typedef unsigned long uint32;
15 typedef unsigned short uint16;
16 typedef unsigned char uint8;
18 /* Receive & Transmit Buffer Descriptor definitions */
19 typedef struct BufferDescriptor {
31 /* private structure */
33 SEVENWIRE, /* 7-wire */
34 MII10, /* MII 10Mbps */
35 MII100 /* MII 100Mbps */
38 /* BD Numer definitions */
39 #define FEC_TBD_NUM 48 /* The user can adjust this value */
40 #define FEC_RBD_NUM 32 /* The user can adjust this value */
42 /* packet size limit */
43 #define FEC_MAX_FRAME_LEN 1522 /* recommended default value */
45 /* Buffer size must be evenly divisible by 16 */
46 #define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
49 uint8 frame[FEC_BUFFER_SIZE];
53 FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */
54 FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */
55 mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */
59 volatile fec512x_t *eth;
60 xceiver_type xcv_type; /* transceiver type */
61 mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */
62 uint16 rbdIndex; /* next receive BD to read */
63 uint16 tbdIndex; /* next transmit BD to send */
64 uint16 usedTbdIndex; /* next transmit BD to clean */
65 uint16 cleanTbdNum; /* the number of available transmit BDs */
68 /* RBD bits definitions */
69 #define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */
70 #define FEC_RBD_WRAP 0x2000 /* Last BD in ring */
71 #define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */
72 #define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */
73 #define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */
74 #define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */
75 #define FEC_RBD_LG 0x0020 /* Frame length violation */
76 #define FEC_RBD_NO 0x0010 /* Nonoctet align frame */
77 #define FEC_RBD_SH 0x0008 /* Short frame */
78 #define FEC_RBD_CR 0x0004 /* CRC error */
79 #define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */
80 #define FEC_RBD_TR 0x0001 /* Frame is truncated */
81 #define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
82 FEC_RBD_OV | FEC_RBD_TR)
84 /* TBD bits definitions */
85 #define FEC_TBD_READY 0x8000 /* Buffer is ready */
86 #define FEC_TBD_WRAP 0x2000 /* Last BD in ring */
87 #define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */
88 #define FEC_TBD_TC 0x0400 /* Transmit the CRC */
89 #define FEC_TBD_ABC 0x0200 /* Append bad CRC */
91 /* MII-related definitios */
92 #define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
93 #define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
94 #define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
95 #define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
96 #define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
97 #define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
98 #define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
100 #define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
101 #define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
103 #endif /* __MPC512X_FEC_H */