1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
12 #ifdef CONFIG_MCF547x_8x
13 #include <asm/fsl_mcdmafec.h>
17 #include <asm/immap.h>
18 #include <linux/mii.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #if defined(CONFIG_CMD_NET)
26 /*extern int fecpin_setclear(struct eth_device *dev, int setclear);*/
28 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
31 /* Make MII read/write commands for the FEC. */
32 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
34 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
35 (REG & 0x1f) << 18) | (VAL & 0xffff))
37 #ifndef CONFIG_SYS_UNSPEC_PHYID
38 # define CONFIG_SYS_UNSPEC_PHYID 0
40 #ifndef CONFIG_SYS_UNSPEC_STRID
41 # define CONFIG_SYS_UNSPEC_STRID 0
44 typedef struct phy_info_struct {
49 phy_info_t phyinfo[] = {
50 {0x0022561B, "AMD79C784VC"}, /* AMD 79C784VC */
51 {0x00406322, "BCM5222"}, /* Broadcom 5222 */
52 {0x02a80150, "Intel82555"}, /* Intel 82555 */
53 {0x0016f870, "LSI80225"}, /* LSI 80225 */
54 {0x0016f880, "LSI80225/B"}, /* LSI 80225/B */
55 {0x78100000, "LXT970"}, /* LXT970 */
56 {0x001378e0, "LXT971"}, /* LXT971 and 972 */
57 {0x00221619, "KS8721BL"}, /* Micrel KS8721BL/SL */
58 {0x00221512, "KSZ8041NL"}, /* Micrel KSZ8041NL */
59 {0x20005CE1, "N83640"}, /* National 83640 */
60 {0x20005C90, "N83848"}, /* National 83848 */
61 {0x20005CA2, "N83849"}, /* National 83849 */
62 {0x01814400, "QS6612"}, /* QS6612 */
63 #if defined(CONFIG_SYS_UNSPEC_PHYID) && defined(CONFIG_SYS_UNSPEC_STRID)
64 {CONFIG_SYS_UNSPEC_PHYID, CONFIG_SYS_UNSPEC_STRID},
70 * mii_init -- Initialize the MII for MII command without ethernet
71 * This function is a subset of eth_init
73 void mii_reset(fec_info_t *info)
75 volatile FEC_T *fecp = (FEC_T *) (info->miibase);
78 fecp->ecr = FEC_ECR_RESET;
80 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
83 if (i == FEC_RESET_DELAY)
84 printf("FEC_RESET_DELAY timeout\n");
87 /* send command to phy using mii, wait for result */
88 uint mii_send(uint mii_cmd)
93 struct eth_device *dev;
100 /* retrieve from register structure */
104 ep = (FEC_T *) info->miibase;
106 ep->mmfr = mii_cmd; /* command to phy */
108 /* wait for mii complete */
109 while (!(ep->eir & FEC_EIR_MII) && (j < info->to_loop)) {
113 if (j >= info->to_loop) {
114 printf("MII not complete\n");
118 mii_reply = ep->mmfr; /* result from phy */
119 ep->eir = FEC_EIR_MII; /* clear MII complete */
121 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
122 __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
125 return (mii_reply & 0xffff); /* data read from phy */
127 #endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
129 #if defined(CONFIG_SYS_DISCOVER_PHY)
130 int mii_discover_phy(fec_info_t *info)
132 #define MAX_PHY_PASSES 11
137 if (info->phyname_init)
138 return info->phy_addr;
140 phyaddr = -1; /* didn't find a PHY yet */
141 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
143 /* PHY may need more time to recover from reset.
144 * The LXT970 needs 50ms typical, no maximum is
145 * specified, so wait 10ms before try again.
146 * With 11 passes this gives it 100ms to wake up.
148 udelay(10000); /* wait 10ms */
151 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
153 phytype = mii_send(mk_mii_read(phyno, MII_PHYSID1));
155 printf("PHY type 0x%x pass %d\n", phytype, pass);
157 if (phytype == 0xffff)
162 mii_send(mk_mii_read(phyno, MII_PHYSID2));
165 printf("PHY @ 0x%x pass %d\n", phyno, pass);
168 for (i = 0; (i < ARRAY_SIZE(phyinfo))
169 && (phyinfo[i].phyid != 0); i++) {
170 if (phyinfo[i].phyid == phytype) {
172 printf("phyid %x - %s\n",
176 strcpy(info->phy_name, phyinfo[i].strid);
177 info->phyname_init = 1;
185 printf("0x%08x\n", phytype);
187 strcpy(info->phy_name, "unknown");
188 info->phyname_init = 1;
195 printf("No PHY device found.\n");
199 #endif /* CONFIG_SYS_DISCOVER_PHY */
201 void mii_init(void) __attribute__((weak,alias("__mii_init")));
203 void __mii_init(void)
208 struct eth_device *dev;
211 volatile FEC_T *fecp;
212 int miispd = 0, i = 0;
216 /* retrieve from register structure */
220 fecp = (FEC_T *) info->miibase;
222 fecpin_setclear(info, 1);
226 /* We use strictly polling mode only */
229 /* Clear any pending interrupt */
230 fecp->eir = 0xffffffff;
233 miispd = (gd->bus_clk / 1000000) / 5;
234 fecp->mscr = miispd << 1;
236 #ifdef CONFIG_SYS_DISCOVER_PHY
237 info->phy_addr = mii_discover_phy(info);
239 if (info->phy_addr == -1)
242 while (i < info->to_loop) {
245 /* Read PHY control register */
246 miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status);
248 /* If phy set to autonegotiate, wait for autonegotiation done,
249 * if phy is not autonegotiating, just wait for link up.
251 if ((status & BMCR_ANENABLE) == BMCR_ANENABLE) {
252 linkgood = (BMSR_ANEGCOMPLETE | BMSR_LSTATUS);
254 linkgood = BMSR_LSTATUS;
256 /* Read PHY status register */
257 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status);
258 if ((status & linkgood) == linkgood)
263 if (i >= info->to_loop)
264 printf("Link UP timeout\n");
266 /* adapt to the duplex and speed settings of the phy */
267 info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
268 info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
272 * Read and write a MII PHY register, routines used by MII Utilities
274 * FIXME: These routines are expected to return 0 on success, but mii_send
275 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
276 * no PHY connected...
277 * For now always return 0.
278 * FIXME: These routines only work after calling eth_init() at least once!
279 * Otherwise they hang in mii_send() !!! Sorry!
282 int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
284 short rdreg; /* register working value */
287 printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
289 rdreg = mii_send(mk_mii_read(addr, reg));
292 printf("0x%04x\n", rdreg);
298 int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
302 printf("miiphy_write(0x%x) @ 0x%x = 0x%04x\n", reg, addr, value);
305 mii_send(mk_mii_write(addr, reg, value));
310 #endif /* CONFIG_CMD_NET */