1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * (C) Copyright 2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
21 #include <asm/immap.h>
22 #include <linux/mii.h>
27 /* Ethernet Transmit and Receive Buffers */
28 #define DBUF_LENGTH 1520
30 #define PKT_MAXBUF_SIZE 1518
31 #define PKT_MAXBLR_SIZE 1520
32 #define LAST_PKTBUFSRX PKTBUFSRX - 1
33 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
34 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
36 DECLARE_GLOBAL_DATA_PTR;
38 static void init_eth_info(struct fec_info_s *info)
40 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
44 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
46 info->rxbd = (cbd_t *)DBUF_LENGTH;
48 /* setup Receive and Transmit buffer descriptor */
49 info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
50 tmp = (u32)info->rxbd;
52 (cbd_t *)((u32)info->txbd + tmp +
53 (PKTBUFSRX * sizeof(cbd_t)));
54 tmp = (u32)info->txbd;
56 (char *)((u32)info->txbuf + tmp +
57 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
58 tmp = (u32)info->txbuf;
61 (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
62 (PKTBUFSRX * sizeof(cbd_t)));
64 (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
65 (TX_BUF_CNT * sizeof(cbd_t)));
67 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
71 printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
73 info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
76 static void fec_reset(struct fec_info_s *info)
78 volatile fec_t *fecp = (fec_t *)(info->iobase);
81 fecp->ecr = FEC_ECR_RESET;
82 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i)
85 if (i == FEC_RESET_DELAY)
86 printf("FEC_RESET_DELAY timeout\n");
89 static void set_fec_duplex_speed(volatile fec_t *fecp, int dup_spd)
93 if ((dup_spd >> 16) == FULL) {
94 /* Set maximum frame length */
95 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
97 fecp->tcr = FEC_TCR_FDEN;
99 /* Half duplex mode */
100 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
101 FEC_RCR_MII_MODE | FEC_RCR_DRT;
102 fecp->tcr &= ~FEC_TCR_FDEN;
105 if ((dup_spd & 0xFFFF) == _100BASET) {
106 #ifdef CONFIG_MCF5445x
107 fecp->rcr &= ~0x200; /* disabled 10T base */
112 bd->bi_ethspeed = 100;
114 #ifdef CONFIG_MCF5445x
115 fecp->rcr |= 0x200; /* enabled 10T base */
120 bd->bi_ethspeed = 10;
125 static void dbg_fec_regs(struct udevice *dev)
127 struct fec_info_s *info = dev->priv;
128 volatile fec_t *fecp = (fec_t *)(info->iobase);
131 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
132 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
133 printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
134 printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
135 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
136 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
137 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
138 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
139 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
140 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
141 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
142 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
143 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
144 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
145 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
146 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
147 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
148 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
149 printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
150 printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
151 printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
152 printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
153 printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
156 printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
158 printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
159 fecp->rmon_t_packets);
160 printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
161 fecp->rmon_t_bc_pkt);
162 printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
163 fecp->rmon_t_mc_pkt);
164 printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
165 fecp->rmon_t_crc_align);
166 printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
167 fecp->rmon_t_undersize);
168 printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
169 fecp->rmon_t_oversize);
170 printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
172 printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
174 printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
176 printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
178 printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
179 fecp->rmon_t_p65to127);
180 printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
181 fecp->rmon_t_p128to255);
182 printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
183 fecp->rmon_t_p256to511);
184 printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
185 fecp->rmon_t_p512to1023);
186 printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
187 fecp->rmon_t_p1024to2047);
188 printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
189 fecp->rmon_t_p_gte2048);
190 printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
191 fecp->rmon_t_octets);
194 printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
196 printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
197 fecp->ieee_t_frame_ok);
198 printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
200 printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
202 printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
204 printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
206 printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
208 printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
209 fecp->ieee_t_macerr);
210 printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
212 printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
214 printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
216 printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
217 fecp->ieee_t_octets_ok);
220 printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
222 printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
223 fecp->rmon_r_packets);
224 printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
225 fecp->rmon_r_bc_pkt);
226 printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
227 fecp->rmon_r_mc_pkt);
228 printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
229 fecp->rmon_r_crc_align);
230 printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
231 fecp->rmon_r_undersize);
232 printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
233 fecp->rmon_r_oversize);
234 printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
236 printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
238 printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
240 printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
241 fecp->rmon_r_p65to127);
242 printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
243 fecp->rmon_r_p128to255);
244 printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
245 fecp->rmon_r_p256to511);
246 printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
247 fecp->rmon_r_p512to1023);
248 printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
249 fecp->rmon_r_p1024to2047);
250 printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
251 fecp->rmon_r_p_gte2048);
252 printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
253 fecp->rmon_r_octets);
256 printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
258 printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
259 fecp->ieee_r_frame_ok);
260 printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
262 printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
264 printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
265 fecp->ieee_r_macerr);
266 printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
268 printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
269 fecp->ieee_r_octets_ok);
275 int mcffec_init(struct udevice *dev)
277 struct fec_info_s *info = dev->priv;
278 volatile fec_t *fecp = (fec_t *) (info->iobase);
282 fecpin_setclear(info, 1);
285 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
286 defined (CONFIG_SYS_DISCOVER_PHY)
290 set_fec_duplex_speed(fecp, info->dup_spd);
292 #ifndef CONFIG_SYS_DISCOVER_PHY
293 set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED);
294 #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
295 #endif /* CONFIG_CMD_MII || CONFIG_MII */
297 /* We use strictly polling mode only */
300 /* Clear any pending interrupt */
301 fecp->eir = 0xffffffff;
303 /* Set station address */
304 if (info->index == 0)
305 rval = eth_env_get_enetaddr("ethaddr", ea);
307 rval = eth_env_get_enetaddr("eth1addr", ea);
310 puts("Please set a valid MAC address\n");
315 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
316 fecp->paur = (ea[4] << 24) | (ea[5] << 16);
318 /* Clear unicast address hash table */
322 /* Clear multicast address hash table */
326 /* Set maximum receive buffer size. */
327 fecp->emrbr = PKT_MAXBLR_SIZE;
330 * Setup Buffers and Buffer Descriptors
336 * Setup Receiver Buffer Descriptors (13.14.24.18)
340 for (i = 0; i < PKTBUFSRX; i++) {
341 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
342 info->rxbd[i].cbd_datlen = 0; /* Reset */
343 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
345 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
348 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
352 for (i = 0; i < TX_BUF_CNT; i++) {
353 info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
354 info->txbd[i].cbd_datlen = 0; /* Reset */
355 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
357 info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
359 /* Set receive and transmit descriptor base */
360 fecp->erdsr = (unsigned int)(&info->rxbd[0]);
361 fecp->etdsr = (unsigned int)(&info->txbd[0]);
363 /* Now enable the transmit and receive processing */
364 fecp->ecr |= FEC_ECR_ETHER_EN;
366 /* And last, try to fill Rx Buffer Descriptors
367 * Descriptor polling active
369 fecp->rdar = 0x01000000;
374 static int mcffec_send(struct udevice *dev, void *packet, int length)
376 struct fec_info_s *info = dev->priv;
377 volatile fec_t *fecp = (fec_t *)info->iobase;
381 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
387 while ((info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_READY) &&
388 (j < info->to_loop)) {
392 if (j >= info->to_loop)
393 printf("TX not ready\n");
395 info->txbd[info->tx_idx].cbd_bufaddr = (uint)packet;
396 info->txbd[info->tx_idx].cbd_datlen = length;
397 info->txbd[info->tx_idx].cbd_sc |= BD_ENET_TX_RDY_LST;
399 /* Activate transmit Buffer Descriptor polling */
400 fecp->tdar = 0x01000000; /* Descriptor polling active */
402 #ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
404 * FEC unable to initial transmit data packet.
405 * A nop will ensure the descriptor polling active completed.
406 * CF Internal RAM has shorter cycle access than DRAM. If use
407 * DRAM as Buffer descriptor and data, a nop is a must.
408 * Affect only V2 and V3.
413 #ifdef CONFIG_SYS_UNIFY_CACHE
418 while ((info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_READY) &&
419 (j < info->to_loop)) {
423 if (j >= info->to_loop)
424 printf("TX timeout\n");
427 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
428 __FILE__, __LINE__, __func__, j,
429 info->txbd[info->tx_idx].cbd_sc,
430 (info->txbd[info->tx_idx].cbd_sc & 0x003C) >> 2);
433 /* return only status bits */
434 rc = (info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
435 info->tx_idx = (info->tx_idx + 1) % TX_BUF_CNT;
440 static int mcffec_recv(struct udevice *dev, int flags, uchar **packetp)
442 struct fec_info_s *info = dev->priv;
443 volatile fec_t *fecp = (fec_t *)info->iobase;
447 #ifdef CONFIG_SYS_UNIFY_CACHE
450 /* If nothing received - leave for() loop */
451 if (info->rxbd[info->rx_idx].cbd_sc & BD_ENET_RX_EMPTY)
454 length = info->rxbd[info->rx_idx].cbd_datlen;
456 if (info->rxbd[info->rx_idx].cbd_sc & 0x003f) {
457 printf("%s[%d] err: %x\n",
459 info->rxbd[info->rx_idx].cbd_sc);
464 * Pass the buffer ptr up to the protocol layers.
466 *packetp = net_rx_packets[info->rx_idx];
468 fecp->eir |= FEC_EIR_RXF;
471 /* Give the buffer back to the FEC. */
472 info->rxbd[info->rx_idx].cbd_datlen = 0;
474 /* wrap around buffer index when necessary */
475 if (info->rx_idx == LAST_PKTBUFSRX) {
476 info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
479 info->rxbd[info->rx_idx].cbd_sc = BD_ENET_RX_EMPTY;
483 /* Try to fill Buffer Descriptors
484 * Descriptor polling active
486 fecp->rdar = 0x01000000;
492 static void mcffec_halt(struct udevice *dev)
494 struct fec_info_s *info = dev->priv;
497 fecpin_setclear(info, 0);
502 memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
503 memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
504 memset(info->txbuf, 0, DBUF_LENGTH);
507 static const struct eth_ops mcffec_ops = {
508 .start = mcffec_init,
515 * Boot sequence, called just after mcffec_ofdata_to_platdata,
516 * as DM way, it replaces old mcffec_initialize.
518 static int mcffec_probe(struct udevice *dev)
520 struct eth_pdata *pdata = dev_get_platdata(dev);
521 struct fec_info_s *info = dev->priv;
522 int node = dev_of_offset(dev);
526 info->index = dev->seq;
527 info->iobase = pdata->iobase;
530 val = fdt_getprop(gd->fdt_blob, node, "mii-base", NULL);
534 fec_idx = fdt32_to_cpu(*val);
535 if (fec_idx == info->index) {
536 fec_iobase = info->iobase;
538 printf("mii base != base address, fec_idx %d\n",
540 retval = fec_get_base_addr(fec_idx, &fec_iobase);
544 info->miibase = fec_iobase;
547 val = fdt_getprop(gd->fdt_blob, node, "phy-addr", NULL);
549 info->phy_addr = fdt32_to_cpu(*val);
551 val = fdt_getprop(gd->fdt_blob, node, "timeout-loop", NULL);
553 info->to_loop = fdt32_to_cpu(*val);
557 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
558 info->bus = mdio_alloc();
561 strcpy(info->bus->name, dev->name);
562 info->bus->read = mcffec_miiphy_read;
563 info->bus->write = mcffec_miiphy_write;
565 retval = mdio_register(info->bus);
573 static int mcffec_remove(struct udevice *dev)
575 struct fec_info_s *priv = dev_get_priv(dev);
577 mdio_unregister(priv->bus);
578 mdio_free(priv->bus);
584 * Boot sequence, called 1st
586 static int mcffec_ofdata_to_platdata(struct udevice *dev)
588 struct eth_pdata *pdata = dev_get_platdata(dev);
591 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
592 /* Default to 10Mbit/s */
593 pdata->max_speed = 10;
595 val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
598 pdata->max_speed = fdt32_to_cpu(*val);
603 static const struct udevice_id mcffec_ids[] = {
604 { .compatible = "fsl,mcf-fec" },
608 U_BOOT_DRIVER(mcffec) = {
611 .of_match = mcffec_ids,
612 .ofdata_to_platdata = mcffec_ofdata_to_platdata,
613 .probe = mcffec_probe,
614 .remove = mcffec_remove,
616 .priv_auto_alloc_size = sizeof(struct fec_info_s),
617 .platdata_auto_alloc_size = sizeof(struct eth_pdata),