1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2005-2006 Atmel Corporation
10 * The u-boot networking stack is a little weird. It seems like the
11 * networking core allocates receive buffers up front without any
12 * regard to the hardware that's supposed to actually receive those
15 * The MACB receives packets into 128-byte receive buffers, so the
16 * buffers allocated by the core isn't very practical to use. We'll
17 * allocate our own, but we need one such buffer in case a packet
18 * wraps around the DMA ring so that we have to copy it.
20 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
21 * configuration header. This way, the core allocates one RX buffer
22 * and one TX buffer, each of which can hold a ethernet packet of
25 * For some reason, the networking core unconditionally specifies a
26 * 32-byte packet "alignment" (which really should be called
27 * "padding"). MACB shouldn't need that, but we'll refrain from any
28 * core modifications here...
38 #include <linux/mii.h>
40 #include <asm/dma-mapping.h>
41 #include <asm/arch/clk.h>
42 #include <linux/errno.h>
46 DECLARE_GLOBAL_DATA_PTR;
49 * These buffer sizes must be power of 2 and divisible
50 * by RX_BUFFER_MULTIPLE
52 #define MACB_RX_BUFFER_SIZE 128
53 #define GEM_RX_BUFFER_SIZE 2048
54 #define RX_BUFFER_MULTIPLE 64
56 #define MACB_RX_RING_SIZE 32
57 #define MACB_TX_RING_SIZE 16
59 #define MACB_TX_TIMEOUT 1000
60 #define MACB_AUTONEG_TIMEOUT 5000000
62 #ifdef CONFIG_MACB_ZYNQ
63 /* INCR4 AHB bursts */
64 #define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
65 /* Use full configured addressable space (8 Kb) */
66 #define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
67 /* Use full configured addressable space (4 Kb) */
68 #define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
69 /* Set RXBUF with use of 128 byte */
70 #define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
71 #define MACB_ZYNQ_GEM_DMACR_INIT \
72 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
73 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
74 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
75 MACB_ZYNQ_GEM_DMACR_RXBUF)
78 struct macb_dma_desc {
83 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
84 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
85 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
86 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
88 #define RXBUF_FRMLEN_MASK 0x00000fff
89 #define TXBUF_FRMLEN_MASK 0x000007ff
94 const struct macb_config *config;
99 unsigned int next_rx_tail;
104 struct macb_dma_desc *rx_ring;
105 struct macb_dma_desc *tx_ring;
106 size_t rx_buffer_size;
108 unsigned long rx_buffer_dma;
109 unsigned long rx_ring_dma;
110 unsigned long tx_ring_dma;
112 struct macb_dma_desc *dummy_desc;
113 unsigned long dummy_desc_dma;
115 const struct device *dev;
116 #ifndef CONFIG_DM_ETH
117 struct eth_device netdev;
119 unsigned short phy_addr;
122 struct phy_device *phydev;
127 unsigned long pclk_rate;
129 phy_interface_t phy_interface;
134 unsigned int dma_burst_length;
136 int (*clk_init)(struct udevice *dev, ulong rate);
139 #ifndef CONFIG_DM_ETH
140 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
143 static int macb_is_gem(struct macb_device *macb)
145 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
148 #ifndef cpu_is_sama5d2
149 #define cpu_is_sama5d2() 0
152 #ifndef cpu_is_sama5d4
153 #define cpu_is_sama5d4() 0
156 static int gem_is_gigabit_capable(struct macb_device *macb)
159 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
160 * configured to support only 10/100.
162 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
165 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
167 unsigned long netctl;
168 unsigned long netstat;
171 netctl = macb_readl(macb, NCR);
172 netctl |= MACB_BIT(MPE);
173 macb_writel(macb, NCR, netctl);
175 frame = (MACB_BF(SOF, 1)
177 | MACB_BF(PHYA, macb->phy_addr)
180 | MACB_BF(DATA, value));
181 macb_writel(macb, MAN, frame);
184 netstat = macb_readl(macb, NSR);
185 } while (!(netstat & MACB_BIT(IDLE)));
187 netctl = macb_readl(macb, NCR);
188 netctl &= ~MACB_BIT(MPE);
189 macb_writel(macb, NCR, netctl);
192 static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
194 unsigned long netctl;
195 unsigned long netstat;
198 netctl = macb_readl(macb, NCR);
199 netctl |= MACB_BIT(MPE);
200 macb_writel(macb, NCR, netctl);
202 frame = (MACB_BF(SOF, 1)
204 | MACB_BF(PHYA, macb->phy_addr)
207 macb_writel(macb, MAN, frame);
210 netstat = macb_readl(macb, NSR);
211 } while (!(netstat & MACB_BIT(IDLE)));
213 frame = macb_readl(macb, MAN);
215 netctl = macb_readl(macb, NCR);
216 netctl &= ~MACB_BIT(MPE);
217 macb_writel(macb, NCR, netctl);
219 return MACB_BFEXT(DATA, frame);
222 void __weak arch_get_mdio_control(const char *name)
227 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
229 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
233 struct udevice *dev = eth_get_dev_by_name(bus->name);
234 struct macb_device *macb = dev_get_priv(dev);
236 struct eth_device *dev = eth_get_dev_by_name(bus->name);
237 struct macb_device *macb = to_macb(dev);
240 if (macb->phy_addr != phy_adr)
243 arch_get_mdio_control(bus->name);
244 value = macb_mdio_read(macb, reg);
249 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
253 struct udevice *dev = eth_get_dev_by_name(bus->name);
254 struct macb_device *macb = dev_get_priv(dev);
256 struct eth_device *dev = eth_get_dev_by_name(bus->name);
257 struct macb_device *macb = to_macb(dev);
260 if (macb->phy_addr != phy_adr)
263 arch_get_mdio_control(bus->name);
264 macb_mdio_write(macb, reg, value);
272 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
275 invalidate_dcache_range(macb->rx_ring_dma,
276 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
279 invalidate_dcache_range(macb->tx_ring_dma,
280 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
284 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
287 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
288 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
290 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
291 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
294 static inline void macb_flush_rx_buffer(struct macb_device *macb)
296 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
297 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
300 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
302 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
303 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
306 #if defined(CONFIG_CMD_NET)
308 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
311 unsigned long paddr, ctrl;
312 unsigned int tx_head = macb->tx_head;
315 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
317 ctrl = length & TXBUF_FRMLEN_MASK;
318 ctrl |= MACB_BIT(TX_LAST);
319 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
320 ctrl |= MACB_BIT(TX_WRAP);
326 macb->tx_ring[tx_head].ctrl = ctrl;
327 macb->tx_ring[tx_head].addr = paddr;
329 macb_flush_ring_desc(macb, TX);
330 /* Do we need check paddr and length is dcache line aligned? */
331 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
332 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
335 * I guess this is necessary because the networking core may
336 * re-use the transmit buffer as soon as we return...
338 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
340 macb_invalidate_ring_desc(macb, TX);
341 ctrl = macb->tx_ring[tx_head].ctrl;
342 if (ctrl & MACB_BIT(TX_USED))
347 dma_unmap_single(packet, length, paddr);
349 if (i <= MACB_TX_TIMEOUT) {
350 if (ctrl & MACB_BIT(TX_UNDERRUN))
351 printf("%s: TX underrun\n", name);
352 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
353 printf("%s: TX buffers exhausted in mid frame\n", name);
355 printf("%s: TX timeout\n", name);
358 /* No one cares anyway */
362 static void reclaim_rx_buffers(struct macb_device *macb,
363 unsigned int new_tail)
369 macb_invalidate_ring_desc(macb, RX);
370 while (i > new_tail) {
371 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
373 if (i > MACB_RX_RING_SIZE)
377 while (i < new_tail) {
378 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
383 macb_flush_ring_desc(macb, RX);
384 macb->rx_tail = new_tail;
387 static int _macb_recv(struct macb_device *macb, uchar **packetp)
389 unsigned int next_rx_tail = macb->next_rx_tail;
394 macb->wrapped = false;
396 macb_invalidate_ring_desc(macb, RX);
398 if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
401 status = macb->rx_ring[next_rx_tail].ctrl;
402 if (status & MACB_BIT(RX_SOF)) {
403 if (next_rx_tail != macb->rx_tail)
404 reclaim_rx_buffers(macb, next_rx_tail);
405 macb->wrapped = false;
408 if (status & MACB_BIT(RX_EOF)) {
409 buffer = macb->rx_buffer +
410 macb->rx_buffer_size * macb->rx_tail;
411 length = status & RXBUF_FRMLEN_MASK;
413 macb_invalidate_rx_buffer(macb);
415 unsigned int headlen, taillen;
417 headlen = macb->rx_buffer_size *
418 (MACB_RX_RING_SIZE - macb->rx_tail);
419 taillen = length - headlen;
420 memcpy((void *)net_rx_packets[0],
422 memcpy((void *)net_rx_packets[0] + headlen,
423 macb->rx_buffer, taillen);
424 *packetp = (void *)net_rx_packets[0];
429 if (++next_rx_tail >= MACB_RX_RING_SIZE)
431 macb->next_rx_tail = next_rx_tail;
434 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
435 macb->wrapped = true;
443 static void macb_phy_reset(struct macb_device *macb, const char *name)
448 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
449 macb_mdio_write(macb, MII_ADVERTISE, adv);
450 printf("%s: Starting autonegotiation...\n", name);
451 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
454 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
455 status = macb_mdio_read(macb, MII_BMSR);
456 if (status & BMSR_ANEGCOMPLETE)
461 if (status & BMSR_ANEGCOMPLETE)
462 printf("%s: Autonegotiation complete\n", name);
464 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
468 static int macb_phy_find(struct macb_device *macb, const char *name)
473 /* Search for PHY... */
474 for (i = 0; i < 32; i++) {
476 phy_id = macb_mdio_read(macb, MII_PHYSID1);
477 if (phy_id != 0xffff) {
478 printf("%s: PHY present at %d\n", name, i);
483 /* PHY isn't up to snuff */
484 printf("%s: PHY not found\n", name);
490 * macb_linkspd_cb - Linkspeed change callback function
491 * @dev/@regs: MACB udevice (DM version) or
492 * Base Register of MACB devices (non-DM version)
494 * Returns 0 when operation success and negative errno number
495 * when operation failed.
498 static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
503 addr = dev_read_addr_index(dev, 1);
504 if (addr == FDT_ADDR_T_NONE)
507 gemgxl_regs = (void __iomem *)addr;
512 * SiFive GEMGXL TX clock operation mode:
514 * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
515 * and output clock on GMII output signal GTX_CLK
516 * 1 = MII mode. Use MII input signal TX_CLK in TX logic
518 writel(rate != 125000000, gemgxl_regs);
522 int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
525 struct macb_device *macb = dev_get_priv(dev);
532 rate = 2500000; /* 2.5 MHz */
535 rate = 25000000; /* 25 MHz */
538 rate = 125000000; /* 125 MHz */
541 /* does not change anything */
545 if (macb->config->clk_init)
546 return macb->config->clk_init(dev, rate);
549 * "tx_clk" is an optional clock source for MACB.
550 * Ignore if it does not exist in DT.
552 ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
557 ret = clk_set_rate(&tx_clk, rate);
566 int __weak macb_linkspd_cb(void *regs, unsigned int speed)
573 static int macb_phy_init(struct udevice *dev, const char *name)
575 static int macb_phy_init(struct macb_device *macb, const char *name)
579 struct macb_device *macb = dev_get_priv(dev);
582 u16 phy_id, status, adv, lpa;
583 int media, speed, duplex;
587 arch_get_mdio_control(name);
588 /* Auto-detect phy_addr */
589 ret = macb_phy_find(macb, name);
593 /* Check if the PHY is up to snuff... */
594 phy_id = macb_mdio_read(macb, MII_PHYSID1);
595 if (phy_id == 0xffff) {
596 printf("%s: No PHY present\n", name);
602 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
603 macb->phy_interface);
605 /* need to consider other phy interface mode */
606 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
607 PHY_INTERFACE_MODE_RGMII);
610 printf("phy_connect failed\n");
614 phy_config(macb->phydev);
617 status = macb_mdio_read(macb, MII_BMSR);
618 if (!(status & BMSR_LSTATUS)) {
619 /* Try to re-negotiate if we don't have link already. */
620 macb_phy_reset(macb, name);
622 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
623 status = macb_mdio_read(macb, MII_BMSR);
624 if (status & BMSR_LSTATUS) {
626 * Delay a bit after the link is established,
627 * so that the next xfer does not fail
636 if (!(status & BMSR_LSTATUS)) {
637 printf("%s: link down (status: 0x%04x)\n",
642 /* First check for GMAC and that it is GiB capable */
643 if (gem_is_gigabit_capable(macb)) {
644 lpa = macb_mdio_read(macb, MII_LPA);
646 if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
648 duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ?
651 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
653 duplex ? "full" : "half",
656 ncfgr = macb_readl(macb, NCFGR);
657 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
658 ncfgr |= GEM_BIT(GBE);
661 ncfgr |= MACB_BIT(FD);
663 macb_writel(macb, NCFGR, ncfgr);
666 ret = macb_linkspd_cb(dev, _1000BASET);
668 ret = macb_linkspd_cb(macb->regs, _1000BASET);
677 /* fall back for EMAC checking */
678 adv = macb_mdio_read(macb, MII_ADVERTISE);
679 lpa = macb_mdio_read(macb, MII_LPA);
680 media = mii_nway_result(lpa & adv);
681 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
683 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
684 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
686 speed ? "100" : "10",
687 duplex ? "full" : "half",
690 ncfgr = macb_readl(macb, NCFGR);
691 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
693 ncfgr |= MACB_BIT(SPD);
695 ret = macb_linkspd_cb(dev, _100BASET);
697 ret = macb_linkspd_cb(macb->regs, _100BASET);
701 ret = macb_linkspd_cb(dev, _10BASET);
703 ret = macb_linkspd_cb(macb->regs, _10BASET);
711 ncfgr |= MACB_BIT(FD);
712 macb_writel(macb, NCFGR, ncfgr);
717 static int gmac_init_multi_queues(struct macb_device *macb)
719 int i, num_queues = 1;
722 /* bit 0 is never set but queue 0 always exists */
723 queue_mask = gem_readl(macb, DCFG6) & 0xff;
726 for (i = 1; i < MACB_MAX_QUEUES; i++)
727 if (queue_mask & (1 << i))
730 macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
731 macb->dummy_desc->addr = 0;
732 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
733 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
735 for (i = 1; i < num_queues; i++)
736 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
741 static void gmac_configure_dma(struct macb_device *macb)
746 buffer_size = macb->rx_buffer_size / RX_BUFFER_MULTIPLE;
747 dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
748 dmacfg |= GEM_BF(RXBS, buffer_size);
750 if (macb->config->dma_burst_length)
751 dmacfg = GEM_BFINS(FBLDO,
752 macb->config->dma_burst_length, dmacfg);
754 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
755 dmacfg &= ~GEM_BIT(ENDIA_PKT);
757 #ifdef CONFIG_SYS_LITTLE_ENDIAN
758 dmacfg &= ~GEM_BIT(ENDIA_DESC);
760 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
763 dmacfg &= ~GEM_BIT(ADDR64);
764 gem_writel(macb, DMACFG, dmacfg);
768 static int _macb_init(struct udevice *dev, const char *name)
770 static int _macb_init(struct macb_device *macb, const char *name)
774 struct macb_device *macb = dev_get_priv(dev);
781 * macb_halt should have been called at some point before now,
782 * so we'll assume the controller is idle.
785 /* initialize DMA descriptors */
786 paddr = macb->rx_buffer_dma;
787 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
788 if (i == (MACB_RX_RING_SIZE - 1))
789 paddr |= MACB_BIT(RX_WRAP);
790 macb->rx_ring[i].addr = paddr;
791 macb->rx_ring[i].ctrl = 0;
792 paddr += macb->rx_buffer_size;
794 macb_flush_ring_desc(macb, RX);
795 macb_flush_rx_buffer(macb);
797 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
798 macb->tx_ring[i].addr = 0;
799 if (i == (MACB_TX_RING_SIZE - 1))
800 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED) |
803 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
805 macb_flush_ring_desc(macb, TX);
810 macb->next_rx_tail = 0;
812 #ifdef CONFIG_MACB_ZYNQ
813 macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
816 macb_writel(macb, RBQP, macb->rx_ring_dma);
817 macb_writel(macb, TBQP, macb->tx_ring_dma);
819 if (macb_is_gem(macb)) {
820 /* Initialize DMA properties */
821 gmac_configure_dma(macb);
822 /* Check the multi queue and initialize the queue for tx */
823 gmac_init_multi_queues(macb);
826 * When the GMAC IP with GE feature, this bit is used to
827 * select interface between RGMII and GMII.
828 * When the GMAC IP without GE feature, this bit is used
829 * to select interface between RMII and MII.
832 if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
833 (macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
834 gem_writel(macb, USRIO, GEM_BIT(RGMII));
836 gem_writel(macb, USRIO, 0);
838 if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
839 unsigned int ncfgr = macb_readl(macb, NCFGR);
841 ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
842 macb_writel(macb, NCFGR, ncfgr);
845 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
846 gem_writel(macb, USRIO, GEM_BIT(RGMII));
848 gem_writel(macb, USRIO, 0);
852 /* choose RMII or MII mode. This depends on the board */
854 #ifdef CONFIG_AT91FAMILY
855 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
856 macb_writel(macb, USRIO,
857 MACB_BIT(RMII) | MACB_BIT(CLKEN));
859 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
862 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
863 macb_writel(macb, USRIO, 0);
865 macb_writel(macb, USRIO, MACB_BIT(MII));
869 #ifdef CONFIG_AT91FAMILY
870 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
872 macb_writel(macb, USRIO, 0);
875 #ifdef CONFIG_AT91FAMILY
876 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
878 macb_writel(macb, USRIO, MACB_BIT(MII));
880 #endif /* CONFIG_RMII */
885 ret = macb_phy_init(dev, name);
887 ret = macb_phy_init(macb, name);
892 /* Enable TX and RX */
893 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
898 static void _macb_halt(struct macb_device *macb)
902 /* Halt the controller and wait for any ongoing transmission to end. */
903 ncr = macb_readl(macb, NCR);
904 ncr |= MACB_BIT(THALT);
905 macb_writel(macb, NCR, ncr);
908 tsr = macb_readl(macb, TSR);
909 } while (tsr & MACB_BIT(TGO));
911 /* Disable TX and RX, and clear statistics */
912 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
915 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
920 /* set hardware address */
921 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
922 enetaddr[2] << 16 | enetaddr[3] << 24;
923 macb_writel(macb, SA1B, hwaddr_bottom);
924 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
925 macb_writel(macb, SA1T, hwaddr_top);
929 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
932 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
933 unsigned long macb_hz = macb->pclk_rate;
935 unsigned long macb_hz = get_macb_pclk_rate(id);
938 if (macb_hz < 20000000)
939 config = MACB_BF(CLK, MACB_CLK_DIV8);
940 else if (macb_hz < 40000000)
941 config = MACB_BF(CLK, MACB_CLK_DIV16);
942 else if (macb_hz < 80000000)
943 config = MACB_BF(CLK, MACB_CLK_DIV32);
945 config = MACB_BF(CLK, MACB_CLK_DIV64);
950 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
954 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
955 unsigned long macb_hz = macb->pclk_rate;
957 unsigned long macb_hz = get_macb_pclk_rate(id);
960 if (macb_hz < 20000000)
961 config = GEM_BF(CLK, GEM_CLK_DIV8);
962 else if (macb_hz < 40000000)
963 config = GEM_BF(CLK, GEM_CLK_DIV16);
964 else if (macb_hz < 80000000)
965 config = GEM_BF(CLK, GEM_CLK_DIV32);
966 else if (macb_hz < 120000000)
967 config = GEM_BF(CLK, GEM_CLK_DIV48);
968 else if (macb_hz < 160000000)
969 config = GEM_BF(CLK, GEM_CLK_DIV64);
970 else if (macb_hz < 240000000)
971 config = GEM_BF(CLK, GEM_CLK_DIV96);
972 else if (macb_hz < 320000000)
973 config = GEM_BF(CLK, GEM_CLK_DIV128);
975 config = GEM_BF(CLK, GEM_CLK_DIV224);
981 * Get the DMA bus width field of the network configuration register that we
982 * should program. We find the width from decoding the design configuration
983 * register to find the maximum supported data bus width.
985 static u32 macb_dbw(struct macb_device *macb)
987 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
989 return GEM_BF(DBW, GEM_DBW128);
991 return GEM_BF(DBW, GEM_DBW64);
994 return GEM_BF(DBW, GEM_DBW32);
998 static void _macb_eth_initialize(struct macb_device *macb)
1000 int id = 0; /* This is not used by functions we call */
1003 if (macb_is_gem(macb))
1004 macb->rx_buffer_size = GEM_RX_BUFFER_SIZE;
1006 macb->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1008 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
1009 macb->rx_buffer = dma_alloc_coherent(macb->rx_buffer_size *
1011 &macb->rx_buffer_dma);
1012 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
1013 &macb->rx_ring_dma);
1014 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
1015 &macb->tx_ring_dma);
1016 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
1017 &macb->dummy_desc_dma);
1020 * Do some basic initialization so that we at least can talk
1023 if (macb_is_gem(macb)) {
1024 ncfgr = gem_mdc_clk_div(id, macb);
1025 ncfgr |= macb_dbw(macb);
1027 ncfgr = macb_mdc_clk_div(id, macb);
1030 macb_writel(macb, NCFGR, ncfgr);
1033 #ifndef CONFIG_DM_ETH
1034 static int macb_send(struct eth_device *netdev, void *packet, int length)
1036 struct macb_device *macb = to_macb(netdev);
1038 return _macb_send(macb, netdev->name, packet, length);
1041 static int macb_recv(struct eth_device *netdev)
1043 struct macb_device *macb = to_macb(netdev);
1047 macb->wrapped = false;
1049 macb->next_rx_tail = macb->rx_tail;
1050 length = _macb_recv(macb, &packet);
1052 net_process_received_packet(packet, length);
1053 reclaim_rx_buffers(macb, macb->next_rx_tail);
1060 static int macb_init(struct eth_device *netdev, bd_t *bd)
1062 struct macb_device *macb = to_macb(netdev);
1064 return _macb_init(macb, netdev->name);
1067 static void macb_halt(struct eth_device *netdev)
1069 struct macb_device *macb = to_macb(netdev);
1071 return _macb_halt(macb);
1074 static int macb_write_hwaddr(struct eth_device *netdev)
1076 struct macb_device *macb = to_macb(netdev);
1078 return _macb_write_hwaddr(macb, netdev->enetaddr);
1081 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
1083 struct macb_device *macb;
1084 struct eth_device *netdev;
1086 macb = malloc(sizeof(struct macb_device));
1088 printf("Error: Failed to allocate memory for MACB%d\n", id);
1091 memset(macb, 0, sizeof(struct macb_device));
1093 netdev = &macb->netdev;
1096 macb->phy_addr = phy_addr;
1098 if (macb_is_gem(macb))
1099 sprintf(netdev->name, "gmac%d", id);
1101 sprintf(netdev->name, "macb%d", id);
1103 netdev->init = macb_init;
1104 netdev->halt = macb_halt;
1105 netdev->send = macb_send;
1106 netdev->recv = macb_recv;
1107 netdev->write_hwaddr = macb_write_hwaddr;
1109 _macb_eth_initialize(macb);
1111 eth_register(netdev);
1113 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1115 struct mii_dev *mdiodev = mdio_alloc();
1118 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
1119 mdiodev->read = macb_miiphy_read;
1120 mdiodev->write = macb_miiphy_write;
1122 retval = mdio_register(mdiodev);
1125 macb->bus = miiphy_get_dev_by_name(netdev->name);
1129 #endif /* !CONFIG_DM_ETH */
1131 #ifdef CONFIG_DM_ETH
1133 static int macb_start(struct udevice *dev)
1135 return _macb_init(dev, dev->name);
1138 static int macb_send(struct udevice *dev, void *packet, int length)
1140 struct macb_device *macb = dev_get_priv(dev);
1142 return _macb_send(macb, dev->name, packet, length);
1145 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1147 struct macb_device *macb = dev_get_priv(dev);
1149 macb->next_rx_tail = macb->rx_tail;
1150 macb->wrapped = false;
1152 return _macb_recv(macb, packetp);
1155 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1157 struct macb_device *macb = dev_get_priv(dev);
1159 reclaim_rx_buffers(macb, macb->next_rx_tail);
1164 static void macb_stop(struct udevice *dev)
1166 struct macb_device *macb = dev_get_priv(dev);
1171 static int macb_write_hwaddr(struct udevice *dev)
1173 struct eth_pdata *plat = dev_get_platdata(dev);
1174 struct macb_device *macb = dev_get_priv(dev);
1176 return _macb_write_hwaddr(macb, plat->enetaddr);
1179 static const struct eth_ops macb_eth_ops = {
1180 .start = macb_start,
1184 .free_pkt = macb_free_pkt,
1185 .write_hwaddr = macb_write_hwaddr,
1189 static int macb_enable_clk(struct udevice *dev)
1191 struct macb_device *macb = dev_get_priv(dev);
1196 ret = clk_get_by_index(dev, 0, &clk);
1201 * If clock driver didn't support enable or disable then
1202 * we get -ENOSYS from clk_enable(). To handle this, we
1203 * don't fail for ret == -ENOSYS.
1205 ret = clk_enable(&clk);
1206 if (ret && ret != -ENOSYS)
1209 clk_rate = clk_get_rate(&clk);
1213 macb->pclk_rate = clk_rate;
1219 static const struct macb_config default_gem_config = {
1220 .dma_burst_length = 16,
1224 static int macb_eth_probe(struct udevice *dev)
1226 struct eth_pdata *pdata = dev_get_platdata(dev);
1227 struct macb_device *macb = dev_get_priv(dev);
1228 const char *phy_mode;
1231 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1234 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1235 if (macb->phy_interface == -1) {
1236 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1240 macb->regs = (void *)pdata->iobase;
1242 macb->config = (struct macb_config *)dev_get_driver_data(dev);
1244 macb->config = &default_gem_config;
1247 ret = macb_enable_clk(dev);
1252 _macb_eth_initialize(macb);
1254 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1255 macb->bus = mdio_alloc();
1258 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1259 macb->bus->read = macb_miiphy_read;
1260 macb->bus->write = macb_miiphy_write;
1262 ret = mdio_register(macb->bus);
1265 macb->bus = miiphy_get_dev_by_name(dev->name);
1271 static int macb_eth_remove(struct udevice *dev)
1273 struct macb_device *macb = dev_get_priv(dev);
1275 #ifdef CONFIG_PHYLIB
1278 mdio_unregister(macb->bus);
1279 mdio_free(macb->bus);
1285 * macb_late_eth_ofdata_to_platdata
1286 * @dev: udevice struct
1287 * Returns 0 when operation success and negative errno number
1288 * when operation failed.
1290 int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev)
1295 static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1297 struct eth_pdata *pdata = dev_get_platdata(dev);
1299 pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
1303 return macb_late_eth_ofdata_to_platdata(dev);
1306 static const struct macb_config sama5d4_config = {
1307 .dma_burst_length = 4,
1311 static const struct macb_config sifive_config = {
1312 .dma_burst_length = 16,
1313 .clk_init = macb_sifive_clk_init,
1316 static const struct udevice_id macb_eth_ids[] = {
1317 { .compatible = "cdns,macb" },
1318 { .compatible = "cdns,at91sam9260-macb" },
1319 { .compatible = "atmel,sama5d2-gem" },
1320 { .compatible = "atmel,sama5d3-gem" },
1321 { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
1322 { .compatible = "cdns,zynq-gem" },
1323 { .compatible = "sifive,fu540-c000-gem",
1324 .data = (ulong)&sifive_config },
1328 U_BOOT_DRIVER(eth_macb) = {
1331 .of_match = macb_eth_ids,
1332 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1333 .probe = macb_eth_probe,
1334 .remove = macb_eth_remove,
1335 .ops = &macb_eth_ops,
1336 .priv_auto_alloc_size = sizeof(struct macb_device),
1337 .platdata_auto_alloc_size = sizeof(struct eth_pdata),