1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2005-2006 Atmel Corporation
10 * The u-boot networking stack is a little weird. It seems like the
11 * networking core allocates receive buffers up front without any
12 * regard to the hardware that's supposed to actually receive those
15 * The MACB receives packets into 128-byte receive buffers, so the
16 * buffers allocated by the core isn't very practical to use. We'll
17 * allocate our own, but we need one such buffer in case a packet
18 * wraps around the DMA ring so that we have to copy it.
20 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
21 * configuration header. This way, the core allocates one RX buffer
22 * and one TX buffer, each of which can hold a ethernet packet of
25 * For some reason, the networking core unconditionally specifies a
26 * 32-byte packet "alignment" (which really should be called
27 * "padding"). MACB shouldn't need that, but we'll refrain from any
28 * core modifications here...
38 #include <linux/mii.h>
40 #include <asm/dma-mapping.h>
41 #include <asm/arch/clk.h>
42 #include <linux/errno.h>
46 DECLARE_GLOBAL_DATA_PTR;
48 #define MACB_RX_BUFFER_SIZE 4096
49 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
50 #define MACB_TX_RING_SIZE 16
51 #define MACB_TX_TIMEOUT 1000
52 #define MACB_AUTONEG_TIMEOUT 5000000
54 #ifdef CONFIG_MACB_ZYNQ
55 /* INCR4 AHB bursts */
56 #define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
57 /* Use full configured addressable space (8 Kb) */
58 #define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
59 /* Use full configured addressable space (4 Kb) */
60 #define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
61 /* Set RXBUF with use of 128 byte */
62 #define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
63 #define MACB_ZYNQ_GEM_DMACR_INIT \
64 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
65 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
66 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
67 MACB_ZYNQ_GEM_DMACR_RXBUF)
70 struct macb_dma_desc {
75 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
76 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
77 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
78 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
80 #define RXBUF_FRMLEN_MASK 0x00000fff
81 #define TXBUF_FRMLEN_MASK 0x000007ff
89 unsigned int next_rx_tail;
94 struct macb_dma_desc *rx_ring;
95 struct macb_dma_desc *tx_ring;
97 unsigned long rx_buffer_dma;
98 unsigned long rx_ring_dma;
99 unsigned long tx_ring_dma;
101 struct macb_dma_desc *dummy_desc;
102 unsigned long dummy_desc_dma;
104 const struct device *dev;
105 #ifndef CONFIG_DM_ETH
106 struct eth_device netdev;
108 unsigned short phy_addr;
111 struct phy_device *phydev;
116 unsigned long pclk_rate;
118 phy_interface_t phy_interface;
121 #ifndef CONFIG_DM_ETH
122 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
125 static int macb_is_gem(struct macb_device *macb)
127 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
130 #ifndef cpu_is_sama5d2
131 #define cpu_is_sama5d2() 0
134 #ifndef cpu_is_sama5d4
135 #define cpu_is_sama5d4() 0
138 static int gem_is_gigabit_capable(struct macb_device *macb)
141 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
142 * configured to support only 10/100.
144 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
147 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
149 unsigned long netctl;
150 unsigned long netstat;
153 netctl = macb_readl(macb, NCR);
154 netctl |= MACB_BIT(MPE);
155 macb_writel(macb, NCR, netctl);
157 frame = (MACB_BF(SOF, 1)
159 | MACB_BF(PHYA, macb->phy_addr)
162 | MACB_BF(DATA, value));
163 macb_writel(macb, MAN, frame);
166 netstat = macb_readl(macb, NSR);
167 } while (!(netstat & MACB_BIT(IDLE)));
169 netctl = macb_readl(macb, NCR);
170 netctl &= ~MACB_BIT(MPE);
171 macb_writel(macb, NCR, netctl);
174 static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
176 unsigned long netctl;
177 unsigned long netstat;
180 netctl = macb_readl(macb, NCR);
181 netctl |= MACB_BIT(MPE);
182 macb_writel(macb, NCR, netctl);
184 frame = (MACB_BF(SOF, 1)
186 | MACB_BF(PHYA, macb->phy_addr)
189 macb_writel(macb, MAN, frame);
192 netstat = macb_readl(macb, NSR);
193 } while (!(netstat & MACB_BIT(IDLE)));
195 frame = macb_readl(macb, MAN);
197 netctl = macb_readl(macb, NCR);
198 netctl &= ~MACB_BIT(MPE);
199 macb_writel(macb, NCR, netctl);
201 return MACB_BFEXT(DATA, frame);
204 void __weak arch_get_mdio_control(const char *name)
209 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
211 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
215 struct udevice *dev = eth_get_dev_by_name(bus->name);
216 struct macb_device *macb = dev_get_priv(dev);
218 struct eth_device *dev = eth_get_dev_by_name(bus->name);
219 struct macb_device *macb = to_macb(dev);
222 if (macb->phy_addr != phy_adr)
225 arch_get_mdio_control(bus->name);
226 value = macb_mdio_read(macb, reg);
231 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
235 struct udevice *dev = eth_get_dev_by_name(bus->name);
236 struct macb_device *macb = dev_get_priv(dev);
238 struct eth_device *dev = eth_get_dev_by_name(bus->name);
239 struct macb_device *macb = to_macb(dev);
242 if (macb->phy_addr != phy_adr)
245 arch_get_mdio_control(bus->name);
246 macb_mdio_write(macb, reg, value);
254 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
257 invalidate_dcache_range(macb->rx_ring_dma,
258 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
261 invalidate_dcache_range(macb->tx_ring_dma,
262 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
266 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
269 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
270 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
272 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
273 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
276 static inline void macb_flush_rx_buffer(struct macb_device *macb)
278 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
279 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
282 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
284 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
285 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
288 #if defined(CONFIG_CMD_NET)
290 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
293 unsigned long paddr, ctrl;
294 unsigned int tx_head = macb->tx_head;
297 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
299 ctrl = length & TXBUF_FRMLEN_MASK;
300 ctrl |= MACB_BIT(TX_LAST);
301 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
302 ctrl |= MACB_BIT(TX_WRAP);
308 macb->tx_ring[tx_head].ctrl = ctrl;
309 macb->tx_ring[tx_head].addr = paddr;
311 macb_flush_ring_desc(macb, TX);
312 /* Do we need check paddr and length is dcache line aligned? */
313 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
314 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
317 * I guess this is necessary because the networking core may
318 * re-use the transmit buffer as soon as we return...
320 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
322 macb_invalidate_ring_desc(macb, TX);
323 ctrl = macb->tx_ring[tx_head].ctrl;
324 if (ctrl & MACB_BIT(TX_USED))
329 dma_unmap_single(packet, length, paddr);
331 if (i <= MACB_TX_TIMEOUT) {
332 if (ctrl & MACB_BIT(TX_UNDERRUN))
333 printf("%s: TX underrun\n", name);
334 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
335 printf("%s: TX buffers exhausted in mid frame\n", name);
337 printf("%s: TX timeout\n", name);
340 /* No one cares anyway */
344 static void reclaim_rx_buffers(struct macb_device *macb,
345 unsigned int new_tail)
351 macb_invalidate_ring_desc(macb, RX);
352 while (i > new_tail) {
353 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
355 if (i > MACB_RX_RING_SIZE)
359 while (i < new_tail) {
360 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
365 macb_flush_ring_desc(macb, RX);
366 macb->rx_tail = new_tail;
369 static int _macb_recv(struct macb_device *macb, uchar **packetp)
371 unsigned int next_rx_tail = macb->next_rx_tail;
376 macb->wrapped = false;
378 macb_invalidate_ring_desc(macb, RX);
380 if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
383 status = macb->rx_ring[next_rx_tail].ctrl;
384 if (status & MACB_BIT(RX_SOF)) {
385 if (next_rx_tail != macb->rx_tail)
386 reclaim_rx_buffers(macb, next_rx_tail);
387 macb->wrapped = false;
390 if (status & MACB_BIT(RX_EOF)) {
391 buffer = macb->rx_buffer + 128 * macb->rx_tail;
392 length = status & RXBUF_FRMLEN_MASK;
394 macb_invalidate_rx_buffer(macb);
396 unsigned int headlen, taillen;
398 headlen = 128 * (MACB_RX_RING_SIZE
400 taillen = length - headlen;
401 memcpy((void *)net_rx_packets[0],
403 memcpy((void *)net_rx_packets[0] + headlen,
404 macb->rx_buffer, taillen);
405 *packetp = (void *)net_rx_packets[0];
410 if (++next_rx_tail >= MACB_RX_RING_SIZE)
412 macb->next_rx_tail = next_rx_tail;
415 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
416 macb->wrapped = true;
424 static void macb_phy_reset(struct macb_device *macb, const char *name)
429 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
430 macb_mdio_write(macb, MII_ADVERTISE, adv);
431 printf("%s: Starting autonegotiation...\n", name);
432 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
435 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
436 status = macb_mdio_read(macb, MII_BMSR);
437 if (status & BMSR_ANEGCOMPLETE)
442 if (status & BMSR_ANEGCOMPLETE)
443 printf("%s: Autonegotiation complete\n", name);
445 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
449 static int macb_phy_find(struct macb_device *macb, const char *name)
454 /* Search for PHY... */
455 for (i = 0; i < 32; i++) {
457 phy_id = macb_mdio_read(macb, MII_PHYSID1);
458 if (phy_id != 0xffff) {
459 printf("%s: PHY present at %d\n", name, i);
464 /* PHY isn't up to snuff */
465 printf("%s: PHY not found\n", name);
471 * macb_linkspd_cb - Linkspeed change callback function
472 * @dev/@regs: MACB udevice (DM version) or
473 * Base Register of MACB devices (non-DM version)
475 * Returns 0 when operation success and negative errno number
476 * when operation failed.
479 int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
487 * "tx_clk" is an optional clock source for MACB.
488 * Ignore if it does not exist in DT.
490 ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
496 rate = 2500000; /* 2.5 MHz */
499 rate = 25000000; /* 25 MHz */
502 rate = 125000000; /* 125 MHz */
505 /* does not change anything */
510 ret = clk_set_rate(&tx_clk, rate);
519 int __weak macb_linkspd_cb(void *regs, unsigned int speed)
526 static int macb_phy_init(struct udevice *dev, const char *name)
528 static int macb_phy_init(struct macb_device *macb, const char *name)
532 struct macb_device *macb = dev_get_priv(dev);
535 u16 phy_id, status, adv, lpa;
536 int media, speed, duplex;
540 arch_get_mdio_control(name);
541 /* Auto-detect phy_addr */
542 ret = macb_phy_find(macb, name);
546 /* Check if the PHY is up to snuff... */
547 phy_id = macb_mdio_read(macb, MII_PHYSID1);
548 if (phy_id == 0xffff) {
549 printf("%s: No PHY present\n", name);
555 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
556 macb->phy_interface);
558 /* need to consider other phy interface mode */
559 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
560 PHY_INTERFACE_MODE_RGMII);
563 printf("phy_connect failed\n");
567 phy_config(macb->phydev);
570 status = macb_mdio_read(macb, MII_BMSR);
571 if (!(status & BMSR_LSTATUS)) {
572 /* Try to re-negotiate if we don't have link already. */
573 macb_phy_reset(macb, name);
575 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
576 status = macb_mdio_read(macb, MII_BMSR);
577 if (status & BMSR_LSTATUS) {
579 * Delay a bit after the link is established,
580 * so that the next xfer does not fail
589 if (!(status & BMSR_LSTATUS)) {
590 printf("%s: link down (status: 0x%04x)\n",
595 /* First check for GMAC and that it is GiB capable */
596 if (gem_is_gigabit_capable(macb)) {
597 lpa = macb_mdio_read(macb, MII_LPA);
599 if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
601 duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ?
604 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
606 duplex ? "full" : "half",
609 ncfgr = macb_readl(macb, NCFGR);
610 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
611 ncfgr |= GEM_BIT(GBE);
614 ncfgr |= MACB_BIT(FD);
616 macb_writel(macb, NCFGR, ncfgr);
619 ret = macb_linkspd_cb(dev, _1000BASET);
621 ret = macb_linkspd_cb(macb->regs, _1000BASET);
630 /* fall back for EMAC checking */
631 adv = macb_mdio_read(macb, MII_ADVERTISE);
632 lpa = macb_mdio_read(macb, MII_LPA);
633 media = mii_nway_result(lpa & adv);
634 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
636 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
637 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
639 speed ? "100" : "10",
640 duplex ? "full" : "half",
643 ncfgr = macb_readl(macb, NCFGR);
644 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
646 ncfgr |= MACB_BIT(SPD);
648 ret = macb_linkspd_cb(dev, _100BASET);
650 ret = macb_linkspd_cb(macb->regs, _100BASET);
654 ret = macb_linkspd_cb(dev, _10BASET);
656 ret = macb_linkspd_cb(macb->regs, _10BASET);
664 ncfgr |= MACB_BIT(FD);
665 macb_writel(macb, NCFGR, ncfgr);
670 static int gmac_init_multi_queues(struct macb_device *macb)
672 int i, num_queues = 1;
675 /* bit 0 is never set but queue 0 always exists */
676 queue_mask = gem_readl(macb, DCFG6) & 0xff;
679 for (i = 1; i < MACB_MAX_QUEUES; i++)
680 if (queue_mask & (1 << i))
683 macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
684 macb->dummy_desc->addr = 0;
685 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
686 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
688 for (i = 1; i < num_queues; i++)
689 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
695 static int _macb_init(struct udevice *dev, const char *name)
697 static int _macb_init(struct macb_device *macb, const char *name)
701 struct macb_device *macb = dev_get_priv(dev);
708 * macb_halt should have been called at some point before now,
709 * so we'll assume the controller is idle.
712 /* initialize DMA descriptors */
713 paddr = macb->rx_buffer_dma;
714 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
715 if (i == (MACB_RX_RING_SIZE - 1))
716 paddr |= MACB_BIT(RX_WRAP);
717 macb->rx_ring[i].addr = paddr;
718 macb->rx_ring[i].ctrl = 0;
721 macb_flush_ring_desc(macb, RX);
722 macb_flush_rx_buffer(macb);
724 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
725 macb->tx_ring[i].addr = 0;
726 if (i == (MACB_TX_RING_SIZE - 1))
727 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED) |
730 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
732 macb_flush_ring_desc(macb, TX);
737 macb->next_rx_tail = 0;
739 #ifdef CONFIG_MACB_ZYNQ
740 macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
743 macb_writel(macb, RBQP, macb->rx_ring_dma);
744 macb_writel(macb, TBQP, macb->tx_ring_dma);
746 if (macb_is_gem(macb)) {
747 /* Check the multi queue and initialize the queue for tx */
748 gmac_init_multi_queues(macb);
751 * When the GMAC IP with GE feature, this bit is used to
752 * select interface between RGMII and GMII.
753 * When the GMAC IP without GE feature, this bit is used
754 * to select interface between RMII and MII.
757 if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
758 (macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
759 gem_writel(macb, USRIO, GEM_BIT(RGMII));
761 gem_writel(macb, USRIO, 0);
763 if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
764 unsigned int ncfgr = macb_readl(macb, NCFGR);
766 ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
767 macb_writel(macb, NCFGR, ncfgr);
770 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
771 gem_writel(macb, USRIO, GEM_BIT(RGMII));
773 gem_writel(macb, USRIO, 0);
777 /* choose RMII or MII mode. This depends on the board */
779 #ifdef CONFIG_AT91FAMILY
780 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
781 macb_writel(macb, USRIO,
782 MACB_BIT(RMII) | MACB_BIT(CLKEN));
784 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
787 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
788 macb_writel(macb, USRIO, 0);
790 macb_writel(macb, USRIO, MACB_BIT(MII));
794 #ifdef CONFIG_AT91FAMILY
795 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
797 macb_writel(macb, USRIO, 0);
800 #ifdef CONFIG_AT91FAMILY
801 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
803 macb_writel(macb, USRIO, MACB_BIT(MII));
805 #endif /* CONFIG_RMII */
810 ret = macb_phy_init(dev, name);
812 ret = macb_phy_init(macb, name);
817 /* Enable TX and RX */
818 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
823 static void _macb_halt(struct macb_device *macb)
827 /* Halt the controller and wait for any ongoing transmission to end. */
828 ncr = macb_readl(macb, NCR);
829 ncr |= MACB_BIT(THALT);
830 macb_writel(macb, NCR, ncr);
833 tsr = macb_readl(macb, TSR);
834 } while (tsr & MACB_BIT(TGO));
836 /* Disable TX and RX, and clear statistics */
837 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
840 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
845 /* set hardware address */
846 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
847 enetaddr[2] << 16 | enetaddr[3] << 24;
848 macb_writel(macb, SA1B, hwaddr_bottom);
849 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
850 macb_writel(macb, SA1T, hwaddr_top);
854 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
857 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
858 unsigned long macb_hz = macb->pclk_rate;
860 unsigned long macb_hz = get_macb_pclk_rate(id);
863 if (macb_hz < 20000000)
864 config = MACB_BF(CLK, MACB_CLK_DIV8);
865 else if (macb_hz < 40000000)
866 config = MACB_BF(CLK, MACB_CLK_DIV16);
867 else if (macb_hz < 80000000)
868 config = MACB_BF(CLK, MACB_CLK_DIV32);
870 config = MACB_BF(CLK, MACB_CLK_DIV64);
875 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
879 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
880 unsigned long macb_hz = macb->pclk_rate;
882 unsigned long macb_hz = get_macb_pclk_rate(id);
885 if (macb_hz < 20000000)
886 config = GEM_BF(CLK, GEM_CLK_DIV8);
887 else if (macb_hz < 40000000)
888 config = GEM_BF(CLK, GEM_CLK_DIV16);
889 else if (macb_hz < 80000000)
890 config = GEM_BF(CLK, GEM_CLK_DIV32);
891 else if (macb_hz < 120000000)
892 config = GEM_BF(CLK, GEM_CLK_DIV48);
893 else if (macb_hz < 160000000)
894 config = GEM_BF(CLK, GEM_CLK_DIV64);
895 else if (macb_hz < 240000000)
896 config = GEM_BF(CLK, GEM_CLK_DIV96);
897 else if (macb_hz < 320000000)
898 config = GEM_BF(CLK, GEM_CLK_DIV128);
900 config = GEM_BF(CLK, GEM_CLK_DIV224);
906 * Get the DMA bus width field of the network configuration register that we
907 * should program. We find the width from decoding the design configuration
908 * register to find the maximum supported data bus width.
910 static u32 macb_dbw(struct macb_device *macb)
912 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
914 return GEM_BF(DBW, GEM_DBW128);
916 return GEM_BF(DBW, GEM_DBW64);
919 return GEM_BF(DBW, GEM_DBW32);
923 static void _macb_eth_initialize(struct macb_device *macb)
925 int id = 0; /* This is not used by functions we call */
928 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
929 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
930 &macb->rx_buffer_dma);
931 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
933 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
935 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
936 &macb->dummy_desc_dma);
939 * Do some basic initialization so that we at least can talk
942 if (macb_is_gem(macb)) {
943 ncfgr = gem_mdc_clk_div(id, macb);
944 ncfgr |= macb_dbw(macb);
946 ncfgr = macb_mdc_clk_div(id, macb);
949 macb_writel(macb, NCFGR, ncfgr);
952 #ifndef CONFIG_DM_ETH
953 static int macb_send(struct eth_device *netdev, void *packet, int length)
955 struct macb_device *macb = to_macb(netdev);
957 return _macb_send(macb, netdev->name, packet, length);
960 static int macb_recv(struct eth_device *netdev)
962 struct macb_device *macb = to_macb(netdev);
966 macb->wrapped = false;
968 macb->next_rx_tail = macb->rx_tail;
969 length = _macb_recv(macb, &packet);
971 net_process_received_packet(packet, length);
972 reclaim_rx_buffers(macb, macb->next_rx_tail);
979 static int macb_init(struct eth_device *netdev, bd_t *bd)
981 struct macb_device *macb = to_macb(netdev);
983 return _macb_init(macb, netdev->name);
986 static void macb_halt(struct eth_device *netdev)
988 struct macb_device *macb = to_macb(netdev);
990 return _macb_halt(macb);
993 static int macb_write_hwaddr(struct eth_device *netdev)
995 struct macb_device *macb = to_macb(netdev);
997 return _macb_write_hwaddr(macb, netdev->enetaddr);
1000 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
1002 struct macb_device *macb;
1003 struct eth_device *netdev;
1005 macb = malloc(sizeof(struct macb_device));
1007 printf("Error: Failed to allocate memory for MACB%d\n", id);
1010 memset(macb, 0, sizeof(struct macb_device));
1012 netdev = &macb->netdev;
1015 macb->phy_addr = phy_addr;
1017 if (macb_is_gem(macb))
1018 sprintf(netdev->name, "gmac%d", id);
1020 sprintf(netdev->name, "macb%d", id);
1022 netdev->init = macb_init;
1023 netdev->halt = macb_halt;
1024 netdev->send = macb_send;
1025 netdev->recv = macb_recv;
1026 netdev->write_hwaddr = macb_write_hwaddr;
1028 _macb_eth_initialize(macb);
1030 eth_register(netdev);
1032 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1034 struct mii_dev *mdiodev = mdio_alloc();
1037 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
1038 mdiodev->read = macb_miiphy_read;
1039 mdiodev->write = macb_miiphy_write;
1041 retval = mdio_register(mdiodev);
1044 macb->bus = miiphy_get_dev_by_name(netdev->name);
1048 #endif /* !CONFIG_DM_ETH */
1050 #ifdef CONFIG_DM_ETH
1052 static int macb_start(struct udevice *dev)
1054 return _macb_init(dev, dev->name);
1057 static int macb_send(struct udevice *dev, void *packet, int length)
1059 struct macb_device *macb = dev_get_priv(dev);
1061 return _macb_send(macb, dev->name, packet, length);
1064 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1066 struct macb_device *macb = dev_get_priv(dev);
1068 macb->next_rx_tail = macb->rx_tail;
1069 macb->wrapped = false;
1071 return _macb_recv(macb, packetp);
1074 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1076 struct macb_device *macb = dev_get_priv(dev);
1078 reclaim_rx_buffers(macb, macb->next_rx_tail);
1083 static void macb_stop(struct udevice *dev)
1085 struct macb_device *macb = dev_get_priv(dev);
1090 static int macb_write_hwaddr(struct udevice *dev)
1092 struct eth_pdata *plat = dev_get_platdata(dev);
1093 struct macb_device *macb = dev_get_priv(dev);
1095 return _macb_write_hwaddr(macb, plat->enetaddr);
1098 static const struct eth_ops macb_eth_ops = {
1099 .start = macb_start,
1103 .free_pkt = macb_free_pkt,
1104 .write_hwaddr = macb_write_hwaddr,
1108 static int macb_enable_clk(struct udevice *dev)
1110 struct macb_device *macb = dev_get_priv(dev);
1115 ret = clk_get_by_index(dev, 0, &clk);
1120 * If clock driver didn't support enable or disable then
1121 * we get -ENOSYS from clk_enable(). To handle this, we
1122 * don't fail for ret == -ENOSYS.
1124 ret = clk_enable(&clk);
1125 if (ret && ret != -ENOSYS)
1128 clk_rate = clk_get_rate(&clk);
1132 macb->pclk_rate = clk_rate;
1138 static int macb_eth_probe(struct udevice *dev)
1140 struct eth_pdata *pdata = dev_get_platdata(dev);
1141 struct macb_device *macb = dev_get_priv(dev);
1142 const char *phy_mode;
1143 __maybe_unused int ret;
1145 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1148 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1149 if (macb->phy_interface == -1) {
1150 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1154 macb->regs = (void *)pdata->iobase;
1157 ret = macb_enable_clk(dev);
1162 _macb_eth_initialize(macb);
1164 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1165 macb->bus = mdio_alloc();
1168 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1169 macb->bus->read = macb_miiphy_read;
1170 macb->bus->write = macb_miiphy_write;
1172 ret = mdio_register(macb->bus);
1175 macb->bus = miiphy_get_dev_by_name(dev->name);
1181 static int macb_eth_remove(struct udevice *dev)
1183 struct macb_device *macb = dev_get_priv(dev);
1185 #ifdef CONFIG_PHYLIB
1188 mdio_unregister(macb->bus);
1189 mdio_free(macb->bus);
1195 * macb_late_eth_ofdata_to_platdata
1196 * @dev: udevice struct
1197 * Returns 0 when operation success and negative errno number
1198 * when operation failed.
1200 int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev)
1205 static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1207 struct eth_pdata *pdata = dev_get_platdata(dev);
1209 pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
1213 return macb_late_eth_ofdata_to_platdata(dev);
1216 static const struct udevice_id macb_eth_ids[] = {
1217 { .compatible = "cdns,macb" },
1218 { .compatible = "cdns,at91sam9260-macb" },
1219 { .compatible = "atmel,sama5d2-gem" },
1220 { .compatible = "atmel,sama5d3-gem" },
1221 { .compatible = "atmel,sama5d4-gem" },
1222 { .compatible = "cdns,zynq-gem" },
1226 U_BOOT_DRIVER(eth_macb) = {
1229 .of_match = macb_eth_ids,
1230 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1231 .probe = macb_eth_probe,
1232 .remove = macb_eth_remove,
1233 .ops = &macb_eth_ops,
1234 .priv_auto_alloc_size = sizeof(struct macb_device),
1235 .platdata_auto_alloc_size = sizeof(struct eth_pdata),