1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2005-2006 Atmel Corporation
10 * The u-boot networking stack is a little weird. It seems like the
11 * networking core allocates receive buffers up front without any
12 * regard to the hardware that's supposed to actually receive those
15 * The MACB receives packets into 128-byte receive buffers, so the
16 * buffers allocated by the core isn't very practical to use. We'll
17 * allocate our own, but we need one such buffer in case a packet
18 * wraps around the DMA ring so that we have to copy it.
20 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
21 * configuration header. This way, the core allocates one RX buffer
22 * and one TX buffer, each of which can hold a ethernet packet of
25 * For some reason, the networking core unconditionally specifies a
26 * 32-byte packet "alignment" (which really should be called
27 * "padding"). MACB shouldn't need that, but we'll refrain from any
28 * core modifications here...
38 #include <linux/mii.h>
40 #include <asm/dma-mapping.h>
41 #include <asm/arch/clk.h>
42 #include <linux/errno.h>
46 DECLARE_GLOBAL_DATA_PTR;
48 #define MACB_RX_BUFFER_SIZE 4096
49 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
50 #define MACB_TX_RING_SIZE 16
51 #define MACB_TX_TIMEOUT 1000
52 #define MACB_AUTONEG_TIMEOUT 5000000
54 #ifdef CONFIG_MACB_ZYNQ
55 /* INCR4 AHB bursts */
56 #define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
57 /* Use full configured addressable space (8 Kb) */
58 #define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
59 /* Use full configured addressable space (4 Kb) */
60 #define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
61 /* Set RXBUF with use of 128 byte */
62 #define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
63 #define MACB_ZYNQ_GEM_DMACR_INIT \
64 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
65 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
66 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
67 MACB_ZYNQ_GEM_DMACR_RXBUF)
70 struct macb_dma_desc {
75 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
76 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
77 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
78 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
80 #define RXADDR_USED 0x00000001
81 #define RXADDR_WRAP 0x00000002
83 #define RXBUF_FRMLEN_MASK 0x00000fff
84 #define RXBUF_FRAME_START 0x00004000
85 #define RXBUF_FRAME_END 0x00008000
86 #define RXBUF_TYPEID_MATCH 0x00400000
87 #define RXBUF_ADDR4_MATCH 0x00800000
88 #define RXBUF_ADDR3_MATCH 0x01000000
89 #define RXBUF_ADDR2_MATCH 0x02000000
90 #define RXBUF_ADDR1_MATCH 0x04000000
91 #define RXBUF_BROADCAST 0x80000000
93 #define TXBUF_FRMLEN_MASK 0x000007ff
94 #define TXBUF_FRAME_END 0x00008000
95 #define TXBUF_NOCRC 0x00010000
96 #define TXBUF_EXHAUSTED 0x08000000
97 #define TXBUF_UNDERRUN 0x10000000
98 #define TXBUF_MAXRETRY 0x20000000
99 #define TXBUF_WRAP 0x40000000
100 #define TXBUF_USED 0x80000000
105 unsigned int rx_tail;
106 unsigned int tx_head;
107 unsigned int tx_tail;
108 unsigned int next_rx_tail;
113 struct macb_dma_desc *rx_ring;
114 struct macb_dma_desc *tx_ring;
116 unsigned long rx_buffer_dma;
117 unsigned long rx_ring_dma;
118 unsigned long tx_ring_dma;
120 struct macb_dma_desc *dummy_desc;
121 unsigned long dummy_desc_dma;
123 const struct device *dev;
124 #ifndef CONFIG_DM_ETH
125 struct eth_device netdev;
127 unsigned short phy_addr;
130 struct phy_device *phydev;
135 unsigned long pclk_rate;
137 phy_interface_t phy_interface;
140 #ifndef CONFIG_DM_ETH
141 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
144 static int macb_is_gem(struct macb_device *macb)
146 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
149 #ifndef cpu_is_sama5d2
150 #define cpu_is_sama5d2() 0
153 #ifndef cpu_is_sama5d4
154 #define cpu_is_sama5d4() 0
157 static int gem_is_gigabit_capable(struct macb_device *macb)
160 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
161 * configured to support only 10/100.
163 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
166 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
168 unsigned long netctl;
169 unsigned long netstat;
172 netctl = macb_readl(macb, NCR);
173 netctl |= MACB_BIT(MPE);
174 macb_writel(macb, NCR, netctl);
176 frame = (MACB_BF(SOF, 1)
178 | MACB_BF(PHYA, macb->phy_addr)
181 | MACB_BF(DATA, value));
182 macb_writel(macb, MAN, frame);
185 netstat = macb_readl(macb, NSR);
186 } while (!(netstat & MACB_BIT(IDLE)));
188 netctl = macb_readl(macb, NCR);
189 netctl &= ~MACB_BIT(MPE);
190 macb_writel(macb, NCR, netctl);
193 static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
195 unsigned long netctl;
196 unsigned long netstat;
199 netctl = macb_readl(macb, NCR);
200 netctl |= MACB_BIT(MPE);
201 macb_writel(macb, NCR, netctl);
203 frame = (MACB_BF(SOF, 1)
205 | MACB_BF(PHYA, macb->phy_addr)
208 macb_writel(macb, MAN, frame);
211 netstat = macb_readl(macb, NSR);
212 } while (!(netstat & MACB_BIT(IDLE)));
214 frame = macb_readl(macb, MAN);
216 netctl = macb_readl(macb, NCR);
217 netctl &= ~MACB_BIT(MPE);
218 macb_writel(macb, NCR, netctl);
220 return MACB_BFEXT(DATA, frame);
223 void __weak arch_get_mdio_control(const char *name)
228 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
230 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
234 struct udevice *dev = eth_get_dev_by_name(bus->name);
235 struct macb_device *macb = dev_get_priv(dev);
237 struct eth_device *dev = eth_get_dev_by_name(bus->name);
238 struct macb_device *macb = to_macb(dev);
241 if (macb->phy_addr != phy_adr)
244 arch_get_mdio_control(bus->name);
245 value = macb_mdio_read(macb, reg);
250 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
254 struct udevice *dev = eth_get_dev_by_name(bus->name);
255 struct macb_device *macb = dev_get_priv(dev);
257 struct eth_device *dev = eth_get_dev_by_name(bus->name);
258 struct macb_device *macb = to_macb(dev);
261 if (macb->phy_addr != phy_adr)
264 arch_get_mdio_control(bus->name);
265 macb_mdio_write(macb, reg, value);
273 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
276 invalidate_dcache_range(macb->rx_ring_dma,
277 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
280 invalidate_dcache_range(macb->tx_ring_dma,
281 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
285 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
288 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
289 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
291 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
292 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
295 static inline void macb_flush_rx_buffer(struct macb_device *macb)
297 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
298 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
301 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
303 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
304 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
307 #if defined(CONFIG_CMD_NET)
309 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
312 unsigned long paddr, ctrl;
313 unsigned int tx_head = macb->tx_head;
316 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
318 ctrl = length & TXBUF_FRMLEN_MASK;
319 ctrl |= TXBUF_FRAME_END;
320 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
327 macb->tx_ring[tx_head].ctrl = ctrl;
328 macb->tx_ring[tx_head].addr = paddr;
330 macb_flush_ring_desc(macb, TX);
331 /* Do we need check paddr and length is dcache line aligned? */
332 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
333 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
336 * I guess this is necessary because the networking core may
337 * re-use the transmit buffer as soon as we return...
339 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
341 macb_invalidate_ring_desc(macb, TX);
342 ctrl = macb->tx_ring[tx_head].ctrl;
343 if (ctrl & TXBUF_USED)
348 dma_unmap_single(packet, length, paddr);
350 if (i <= MACB_TX_TIMEOUT) {
351 if (ctrl & TXBUF_UNDERRUN)
352 printf("%s: TX underrun\n", name);
353 if (ctrl & TXBUF_EXHAUSTED)
354 printf("%s: TX buffers exhausted in mid frame\n", name);
356 printf("%s: TX timeout\n", name);
359 /* No one cares anyway */
363 static void reclaim_rx_buffers(struct macb_device *macb,
364 unsigned int new_tail)
370 macb_invalidate_ring_desc(macb, RX);
371 while (i > new_tail) {
372 macb->rx_ring[i].addr &= ~RXADDR_USED;
374 if (i > MACB_RX_RING_SIZE)
378 while (i < new_tail) {
379 macb->rx_ring[i].addr &= ~RXADDR_USED;
384 macb_flush_ring_desc(macb, RX);
385 macb->rx_tail = new_tail;
388 static int _macb_recv(struct macb_device *macb, uchar **packetp)
390 unsigned int next_rx_tail = macb->next_rx_tail;
395 macb->wrapped = false;
397 macb_invalidate_ring_desc(macb, RX);
399 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
402 status = macb->rx_ring[next_rx_tail].ctrl;
403 if (status & RXBUF_FRAME_START) {
404 if (next_rx_tail != macb->rx_tail)
405 reclaim_rx_buffers(macb, next_rx_tail);
406 macb->wrapped = false;
409 if (status & RXBUF_FRAME_END) {
410 buffer = macb->rx_buffer + 128 * macb->rx_tail;
411 length = status & RXBUF_FRMLEN_MASK;
413 macb_invalidate_rx_buffer(macb);
415 unsigned int headlen, taillen;
417 headlen = 128 * (MACB_RX_RING_SIZE
419 taillen = length - headlen;
420 memcpy((void *)net_rx_packets[0],
422 memcpy((void *)net_rx_packets[0] + headlen,
423 macb->rx_buffer, taillen);
424 *packetp = (void *)net_rx_packets[0];
429 if (++next_rx_tail >= MACB_RX_RING_SIZE)
431 macb->next_rx_tail = next_rx_tail;
434 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
435 macb->wrapped = true;
443 static void macb_phy_reset(struct macb_device *macb, const char *name)
448 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
449 macb_mdio_write(macb, MII_ADVERTISE, adv);
450 printf("%s: Starting autonegotiation...\n", name);
451 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
454 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
455 status = macb_mdio_read(macb, MII_BMSR);
456 if (status & BMSR_ANEGCOMPLETE)
461 if (status & BMSR_ANEGCOMPLETE)
462 printf("%s: Autonegotiation complete\n", name);
464 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
468 static int macb_phy_find(struct macb_device *macb, const char *name)
473 /* Search for PHY... */
474 for (i = 0; i < 32; i++) {
476 phy_id = macb_mdio_read(macb, MII_PHYSID1);
477 if (phy_id != 0xffff) {
478 printf("%s: PHY present at %d\n", name, i);
483 /* PHY isn't up to snuff */
484 printf("%s: PHY not found\n", name);
490 * macb_linkspd_cb - Linkspeed change callback function
491 * @dev/@regs: MACB udevice (DM version) or
492 * Base Register of MACB devices (non-DM version)
494 * Returns 0 when operation success and negative errno number
495 * when operation failed.
498 int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
506 * "tx_clk" is an optional clock source for MACB.
507 * Ignore if it does not exist in DT.
509 ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
515 rate = 2500000; /* 2.5 MHz */
518 rate = 25000000; /* 25 MHz */
521 rate = 125000000; /* 125 MHz */
524 /* does not change anything */
529 ret = clk_set_rate(&tx_clk, rate);
538 int __weak macb_linkspd_cb(void *regs, unsigned int speed)
545 static int macb_phy_init(struct udevice *dev, const char *name)
547 static int macb_phy_init(struct macb_device *macb, const char *name)
551 struct macb_device *macb = dev_get_priv(dev);
554 u16 phy_id, status, adv, lpa;
555 int media, speed, duplex;
559 arch_get_mdio_control(name);
560 /* Auto-detect phy_addr */
561 ret = macb_phy_find(macb, name);
565 /* Check if the PHY is up to snuff... */
566 phy_id = macb_mdio_read(macb, MII_PHYSID1);
567 if (phy_id == 0xffff) {
568 printf("%s: No PHY present\n", name);
574 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
575 macb->phy_interface);
577 /* need to consider other phy interface mode */
578 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
579 PHY_INTERFACE_MODE_RGMII);
582 printf("phy_connect failed\n");
586 phy_config(macb->phydev);
589 status = macb_mdio_read(macb, MII_BMSR);
590 if (!(status & BMSR_LSTATUS)) {
591 /* Try to re-negotiate if we don't have link already. */
592 macb_phy_reset(macb, name);
594 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
595 status = macb_mdio_read(macb, MII_BMSR);
596 if (status & BMSR_LSTATUS) {
598 * Delay a bit after the link is established,
599 * so that the next xfer does not fail
608 if (!(status & BMSR_LSTATUS)) {
609 printf("%s: link down (status: 0x%04x)\n",
614 /* First check for GMAC and that it is GiB capable */
615 if (gem_is_gigabit_capable(macb)) {
616 lpa = macb_mdio_read(macb, MII_LPA);
618 if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
620 duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ?
623 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
625 duplex ? "full" : "half",
628 ncfgr = macb_readl(macb, NCFGR);
629 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
630 ncfgr |= GEM_BIT(GBE);
633 ncfgr |= MACB_BIT(FD);
635 macb_writel(macb, NCFGR, ncfgr);
638 ret = macb_linkspd_cb(dev, _1000BASET);
640 ret = macb_linkspd_cb(macb->regs, _1000BASET);
649 /* fall back for EMAC checking */
650 adv = macb_mdio_read(macb, MII_ADVERTISE);
651 lpa = macb_mdio_read(macb, MII_LPA);
652 media = mii_nway_result(lpa & adv);
653 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
655 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
656 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
658 speed ? "100" : "10",
659 duplex ? "full" : "half",
662 ncfgr = macb_readl(macb, NCFGR);
663 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
665 ncfgr |= MACB_BIT(SPD);
667 ret = macb_linkspd_cb(dev, _100BASET);
669 ret = macb_linkspd_cb(macb->regs, _100BASET);
673 ret = macb_linkspd_cb(dev, _10BASET);
675 ret = macb_linkspd_cb(macb->regs, _10BASET);
683 ncfgr |= MACB_BIT(FD);
684 macb_writel(macb, NCFGR, ncfgr);
689 static int gmac_init_multi_queues(struct macb_device *macb)
691 int i, num_queues = 1;
694 /* bit 0 is never set but queue 0 always exists */
695 queue_mask = gem_readl(macb, DCFG6) & 0xff;
698 for (i = 1; i < MACB_MAX_QUEUES; i++)
699 if (queue_mask & (1 << i))
702 macb->dummy_desc->ctrl = TXBUF_USED;
703 macb->dummy_desc->addr = 0;
704 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
705 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
707 for (i = 1; i < num_queues; i++)
708 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
714 static int _macb_init(struct udevice *dev, const char *name)
716 static int _macb_init(struct macb_device *macb, const char *name)
720 struct macb_device *macb = dev_get_priv(dev);
727 * macb_halt should have been called at some point before now,
728 * so we'll assume the controller is idle.
731 /* initialize DMA descriptors */
732 paddr = macb->rx_buffer_dma;
733 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
734 if (i == (MACB_RX_RING_SIZE - 1))
735 paddr |= RXADDR_WRAP;
736 macb->rx_ring[i].addr = paddr;
737 macb->rx_ring[i].ctrl = 0;
740 macb_flush_ring_desc(macb, RX);
741 macb_flush_rx_buffer(macb);
743 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
744 macb->tx_ring[i].addr = 0;
745 if (i == (MACB_TX_RING_SIZE - 1))
746 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
748 macb->tx_ring[i].ctrl = TXBUF_USED;
750 macb_flush_ring_desc(macb, TX);
755 macb->next_rx_tail = 0;
757 #ifdef CONFIG_MACB_ZYNQ
758 macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
761 macb_writel(macb, RBQP, macb->rx_ring_dma);
762 macb_writel(macb, TBQP, macb->tx_ring_dma);
764 if (macb_is_gem(macb)) {
765 /* Check the multi queue and initialize the queue for tx */
766 gmac_init_multi_queues(macb);
769 * When the GMAC IP with GE feature, this bit is used to
770 * select interface between RGMII and GMII.
771 * When the GMAC IP without GE feature, this bit is used
772 * to select interface between RMII and MII.
775 if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
776 (macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
777 gem_writel(macb, UR, GEM_BIT(RGMII));
779 gem_writel(macb, UR, 0);
781 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
782 gem_writel(macb, UR, GEM_BIT(RGMII));
784 gem_writel(macb, UR, 0);
788 /* choose RMII or MII mode. This depends on the board */
790 #ifdef CONFIG_AT91FAMILY
791 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
792 macb_writel(macb, USRIO,
793 MACB_BIT(RMII) | MACB_BIT(CLKEN));
795 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
798 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
799 macb_writel(macb, USRIO, 0);
801 macb_writel(macb, USRIO, MACB_BIT(MII));
805 #ifdef CONFIG_AT91FAMILY
806 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
808 macb_writel(macb, USRIO, 0);
811 #ifdef CONFIG_AT91FAMILY
812 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
814 macb_writel(macb, USRIO, MACB_BIT(MII));
816 #endif /* CONFIG_RMII */
821 ret = macb_phy_init(dev, name);
823 ret = macb_phy_init(macb, name);
828 /* Enable TX and RX */
829 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
834 static void _macb_halt(struct macb_device *macb)
838 /* Halt the controller and wait for any ongoing transmission to end. */
839 ncr = macb_readl(macb, NCR);
840 ncr |= MACB_BIT(THALT);
841 macb_writel(macb, NCR, ncr);
844 tsr = macb_readl(macb, TSR);
845 } while (tsr & MACB_BIT(TGO));
847 /* Disable TX and RX, and clear statistics */
848 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
851 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
856 /* set hardware address */
857 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
858 enetaddr[2] << 16 | enetaddr[3] << 24;
859 macb_writel(macb, SA1B, hwaddr_bottom);
860 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
861 macb_writel(macb, SA1T, hwaddr_top);
865 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
868 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
869 unsigned long macb_hz = macb->pclk_rate;
871 unsigned long macb_hz = get_macb_pclk_rate(id);
874 if (macb_hz < 20000000)
875 config = MACB_BF(CLK, MACB_CLK_DIV8);
876 else if (macb_hz < 40000000)
877 config = MACB_BF(CLK, MACB_CLK_DIV16);
878 else if (macb_hz < 80000000)
879 config = MACB_BF(CLK, MACB_CLK_DIV32);
881 config = MACB_BF(CLK, MACB_CLK_DIV64);
886 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
890 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
891 unsigned long macb_hz = macb->pclk_rate;
893 unsigned long macb_hz = get_macb_pclk_rate(id);
896 if (macb_hz < 20000000)
897 config = GEM_BF(CLK, GEM_CLK_DIV8);
898 else if (macb_hz < 40000000)
899 config = GEM_BF(CLK, GEM_CLK_DIV16);
900 else if (macb_hz < 80000000)
901 config = GEM_BF(CLK, GEM_CLK_DIV32);
902 else if (macb_hz < 120000000)
903 config = GEM_BF(CLK, GEM_CLK_DIV48);
904 else if (macb_hz < 160000000)
905 config = GEM_BF(CLK, GEM_CLK_DIV64);
907 config = GEM_BF(CLK, GEM_CLK_DIV96);
913 * Get the DMA bus width field of the network configuration register that we
914 * should program. We find the width from decoding the design configuration
915 * register to find the maximum supported data bus width.
917 static u32 macb_dbw(struct macb_device *macb)
919 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
921 return GEM_BF(DBW, GEM_DBW128);
923 return GEM_BF(DBW, GEM_DBW64);
926 return GEM_BF(DBW, GEM_DBW32);
930 static void _macb_eth_initialize(struct macb_device *macb)
932 int id = 0; /* This is not used by functions we call */
935 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
936 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
937 &macb->rx_buffer_dma);
938 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
940 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
942 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
943 &macb->dummy_desc_dma);
946 * Do some basic initialization so that we at least can talk
949 if (macb_is_gem(macb)) {
950 ncfgr = gem_mdc_clk_div(id, macb);
951 ncfgr |= macb_dbw(macb);
953 ncfgr = macb_mdc_clk_div(id, macb);
956 macb_writel(macb, NCFGR, ncfgr);
959 #ifndef CONFIG_DM_ETH
960 static int macb_send(struct eth_device *netdev, void *packet, int length)
962 struct macb_device *macb = to_macb(netdev);
964 return _macb_send(macb, netdev->name, packet, length);
967 static int macb_recv(struct eth_device *netdev)
969 struct macb_device *macb = to_macb(netdev);
973 macb->wrapped = false;
975 macb->next_rx_tail = macb->rx_tail;
976 length = _macb_recv(macb, &packet);
978 net_process_received_packet(packet, length);
979 reclaim_rx_buffers(macb, macb->next_rx_tail);
986 static int macb_init(struct eth_device *netdev, bd_t *bd)
988 struct macb_device *macb = to_macb(netdev);
990 return _macb_init(macb, netdev->name);
993 static void macb_halt(struct eth_device *netdev)
995 struct macb_device *macb = to_macb(netdev);
997 return _macb_halt(macb);
1000 static int macb_write_hwaddr(struct eth_device *netdev)
1002 struct macb_device *macb = to_macb(netdev);
1004 return _macb_write_hwaddr(macb, netdev->enetaddr);
1007 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
1009 struct macb_device *macb;
1010 struct eth_device *netdev;
1012 macb = malloc(sizeof(struct macb_device));
1014 printf("Error: Failed to allocate memory for MACB%d\n", id);
1017 memset(macb, 0, sizeof(struct macb_device));
1019 netdev = &macb->netdev;
1022 macb->phy_addr = phy_addr;
1024 if (macb_is_gem(macb))
1025 sprintf(netdev->name, "gmac%d", id);
1027 sprintf(netdev->name, "macb%d", id);
1029 netdev->init = macb_init;
1030 netdev->halt = macb_halt;
1031 netdev->send = macb_send;
1032 netdev->recv = macb_recv;
1033 netdev->write_hwaddr = macb_write_hwaddr;
1035 _macb_eth_initialize(macb);
1037 eth_register(netdev);
1039 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1041 struct mii_dev *mdiodev = mdio_alloc();
1044 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
1045 mdiodev->read = macb_miiphy_read;
1046 mdiodev->write = macb_miiphy_write;
1048 retval = mdio_register(mdiodev);
1051 macb->bus = miiphy_get_dev_by_name(netdev->name);
1055 #endif /* !CONFIG_DM_ETH */
1057 #ifdef CONFIG_DM_ETH
1059 static int macb_start(struct udevice *dev)
1061 return _macb_init(dev, dev->name);
1064 static int macb_send(struct udevice *dev, void *packet, int length)
1066 struct macb_device *macb = dev_get_priv(dev);
1068 return _macb_send(macb, dev->name, packet, length);
1071 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1073 struct macb_device *macb = dev_get_priv(dev);
1075 macb->next_rx_tail = macb->rx_tail;
1076 macb->wrapped = false;
1078 return _macb_recv(macb, packetp);
1081 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1083 struct macb_device *macb = dev_get_priv(dev);
1085 reclaim_rx_buffers(macb, macb->next_rx_tail);
1090 static void macb_stop(struct udevice *dev)
1092 struct macb_device *macb = dev_get_priv(dev);
1097 static int macb_write_hwaddr(struct udevice *dev)
1099 struct eth_pdata *plat = dev_get_platdata(dev);
1100 struct macb_device *macb = dev_get_priv(dev);
1102 return _macb_write_hwaddr(macb, plat->enetaddr);
1105 static const struct eth_ops macb_eth_ops = {
1106 .start = macb_start,
1110 .free_pkt = macb_free_pkt,
1111 .write_hwaddr = macb_write_hwaddr,
1115 static int macb_enable_clk(struct udevice *dev)
1117 struct macb_device *macb = dev_get_priv(dev);
1122 ret = clk_get_by_index(dev, 0, &clk);
1127 * If clock driver didn't support enable or disable then
1128 * we get -ENOSYS from clk_enable(). To handle this, we
1129 * don't fail for ret == -ENOSYS.
1131 ret = clk_enable(&clk);
1132 if (ret && ret != -ENOSYS)
1135 clk_rate = clk_get_rate(&clk);
1139 macb->pclk_rate = clk_rate;
1145 static int macb_eth_probe(struct udevice *dev)
1147 struct eth_pdata *pdata = dev_get_platdata(dev);
1148 struct macb_device *macb = dev_get_priv(dev);
1149 const char *phy_mode;
1150 __maybe_unused int ret;
1152 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1155 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1156 if (macb->phy_interface == -1) {
1157 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1161 macb->regs = (void *)pdata->iobase;
1164 ret = macb_enable_clk(dev);
1169 _macb_eth_initialize(macb);
1171 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1172 macb->bus = mdio_alloc();
1175 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1176 macb->bus->read = macb_miiphy_read;
1177 macb->bus->write = macb_miiphy_write;
1179 ret = mdio_register(macb->bus);
1182 macb->bus = miiphy_get_dev_by_name(dev->name);
1188 static int macb_eth_remove(struct udevice *dev)
1190 struct macb_device *macb = dev_get_priv(dev);
1192 #ifdef CONFIG_PHYLIB
1195 mdio_unregister(macb->bus);
1196 mdio_free(macb->bus);
1202 * macb_late_eth_ofdata_to_platdata
1203 * @dev: udevice struct
1204 * Returns 0 when operation success and negative errno number
1205 * when operation failed.
1207 int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev)
1212 static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1214 struct eth_pdata *pdata = dev_get_platdata(dev);
1216 pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
1220 return macb_late_eth_ofdata_to_platdata(dev);
1223 static const struct udevice_id macb_eth_ids[] = {
1224 { .compatible = "cdns,macb" },
1225 { .compatible = "cdns,at91sam9260-macb" },
1226 { .compatible = "atmel,sama5d2-gem" },
1227 { .compatible = "atmel,sama5d3-gem" },
1228 { .compatible = "atmel,sama5d4-gem" },
1229 { .compatible = "cdns,zynq-gem" },
1233 U_BOOT_DRIVER(eth_macb) = {
1236 .of_match = macb_eth_ids,
1237 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1238 .probe = macb_eth_probe,
1239 .remove = macb_eth_remove,
1240 .ops = &macb_eth_ops,
1241 .priv_auto_alloc_size = sizeof(struct macb_device),
1242 .platdata_auto_alloc_size = sizeof(struct eth_pdata),