2 * Copyright (C) 2005-2006 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
10 * The u-boot networking stack is a little weird. It seems like the
11 * networking core allocates receive buffers up front without any
12 * regard to the hardware that's supposed to actually receive those
15 * The MACB receives packets into 128-byte receive buffers, so the
16 * buffers allocated by the core isn't very practical to use. We'll
17 * allocate our own, but we need one such buffer in case a packet
18 * wraps around the DMA ring so that we have to copy it.
20 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
21 * configuration header. This way, the core allocates one RX buffer
22 * and one TX buffer, each of which can hold a ethernet packet of
25 * For some reason, the networking core unconditionally specifies a
26 * 32-byte packet "alignment" (which really should be called
27 * "padding"). MACB shouldn't need that, but we'll refrain from any
28 * core modifications here...
38 #include <linux/mii.h>
40 #include <asm/dma-mapping.h>
41 #include <asm/arch/clk.h>
42 #include <asm-generic/errno.h>
46 #define MACB_RX_BUFFER_SIZE 4096
47 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
48 #define MACB_TX_RING_SIZE 16
49 #define MACB_TX_TIMEOUT 1000
50 #define MACB_AUTONEG_TIMEOUT 5000000
52 struct macb_dma_desc {
57 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
58 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
59 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
60 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
62 #define RXADDR_USED 0x00000001
63 #define RXADDR_WRAP 0x00000002
65 #define RXBUF_FRMLEN_MASK 0x00000fff
66 #define RXBUF_FRAME_START 0x00004000
67 #define RXBUF_FRAME_END 0x00008000
68 #define RXBUF_TYPEID_MATCH 0x00400000
69 #define RXBUF_ADDR4_MATCH 0x00800000
70 #define RXBUF_ADDR3_MATCH 0x01000000
71 #define RXBUF_ADDR2_MATCH 0x02000000
72 #define RXBUF_ADDR1_MATCH 0x04000000
73 #define RXBUF_BROADCAST 0x80000000
75 #define TXBUF_FRMLEN_MASK 0x000007ff
76 #define TXBUF_FRAME_END 0x00008000
77 #define TXBUF_NOCRC 0x00010000
78 #define TXBUF_EXHAUSTED 0x08000000
79 #define TXBUF_UNDERRUN 0x10000000
80 #define TXBUF_MAXRETRY 0x20000000
81 #define TXBUF_WRAP 0x40000000
82 #define TXBUF_USED 0x80000000
90 unsigned int next_rx_tail;
95 struct macb_dma_desc *rx_ring;
96 struct macb_dma_desc *tx_ring;
98 unsigned long rx_buffer_dma;
99 unsigned long rx_ring_dma;
100 unsigned long tx_ring_dma;
102 struct macb_dma_desc *dummy_desc;
103 unsigned long dummy_desc_dma;
105 const struct device *dev;
106 #ifndef CONFIG_DM_ETH
107 struct eth_device netdev;
109 unsigned short phy_addr;
112 #ifndef CONFIG_DM_ETH
113 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
116 static int macb_is_gem(struct macb_device *macb)
118 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
121 #ifndef cpu_is_sama5d2
122 #define cpu_is_sama5d2() 0
125 #ifndef cpu_is_sama5d4
126 #define cpu_is_sama5d4() 0
129 static int gem_is_gigabit_capable(struct macb_device *macb)
132 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
133 * configured to support only 10/100.
135 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
138 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
140 unsigned long netctl;
141 unsigned long netstat;
144 netctl = macb_readl(macb, NCR);
145 netctl |= MACB_BIT(MPE);
146 macb_writel(macb, NCR, netctl);
148 frame = (MACB_BF(SOF, 1)
150 | MACB_BF(PHYA, macb->phy_addr)
153 | MACB_BF(DATA, value));
154 macb_writel(macb, MAN, frame);
157 netstat = macb_readl(macb, NSR);
158 } while (!(netstat & MACB_BIT(IDLE)));
160 netctl = macb_readl(macb, NCR);
161 netctl &= ~MACB_BIT(MPE);
162 macb_writel(macb, NCR, netctl);
165 static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
167 unsigned long netctl;
168 unsigned long netstat;
171 netctl = macb_readl(macb, NCR);
172 netctl |= MACB_BIT(MPE);
173 macb_writel(macb, NCR, netctl);
175 frame = (MACB_BF(SOF, 1)
177 | MACB_BF(PHYA, macb->phy_addr)
180 macb_writel(macb, MAN, frame);
183 netstat = macb_readl(macb, NSR);
184 } while (!(netstat & MACB_BIT(IDLE)));
186 frame = macb_readl(macb, MAN);
188 netctl = macb_readl(macb, NCR);
189 netctl &= ~MACB_BIT(MPE);
190 macb_writel(macb, NCR, netctl);
192 return MACB_BFEXT(DATA, frame);
195 void __weak arch_get_mdio_control(const char *name)
200 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
202 int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
205 struct udevice *dev = eth_get_dev_by_name(devname);
206 struct macb_device *macb = dev_get_priv(dev);
208 struct eth_device *dev = eth_get_dev_by_name(devname);
209 struct macb_device *macb = to_macb(dev);
212 if (macb->phy_addr != phy_adr)
215 arch_get_mdio_control(devname);
216 *value = macb_mdio_read(macb, reg);
221 int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
224 struct udevice *dev = eth_get_dev_by_name(devname);
225 struct macb_device *macb = dev_get_priv(dev);
227 struct eth_device *dev = eth_get_dev_by_name(devname);
228 struct macb_device *macb = to_macb(dev);
231 if (macb->phy_addr != phy_adr)
234 arch_get_mdio_control(devname);
235 macb_mdio_write(macb, reg, value);
243 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
246 invalidate_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
247 MACB_RX_DMA_DESC_SIZE);
249 invalidate_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
250 MACB_TX_DMA_DESC_SIZE);
253 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
256 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
257 MACB_RX_DMA_DESC_SIZE);
259 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
260 MACB_TX_DMA_DESC_SIZE);
263 static inline void macb_flush_rx_buffer(struct macb_device *macb)
265 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
266 MACB_RX_BUFFER_SIZE);
269 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
271 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
272 MACB_RX_BUFFER_SIZE);
275 #if defined(CONFIG_CMD_NET)
277 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
280 unsigned long paddr, ctrl;
281 unsigned int tx_head = macb->tx_head;
284 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
286 ctrl = length & TXBUF_FRMLEN_MASK;
287 ctrl |= TXBUF_FRAME_END;
288 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
295 macb->tx_ring[tx_head].ctrl = ctrl;
296 macb->tx_ring[tx_head].addr = paddr;
298 macb_flush_ring_desc(macb, TX);
299 /* Do we need check paddr and length is dcache line aligned? */
300 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
301 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
304 * I guess this is necessary because the networking core may
305 * re-use the transmit buffer as soon as we return...
307 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
309 macb_invalidate_ring_desc(macb, TX);
310 ctrl = macb->tx_ring[tx_head].ctrl;
311 if (ctrl & TXBUF_USED)
316 dma_unmap_single(packet, length, paddr);
318 if (i <= MACB_TX_TIMEOUT) {
319 if (ctrl & TXBUF_UNDERRUN)
320 printf("%s: TX underrun\n", name);
321 if (ctrl & TXBUF_EXHAUSTED)
322 printf("%s: TX buffers exhausted in mid frame\n", name);
324 printf("%s: TX timeout\n", name);
327 /* No one cares anyway */
331 static void reclaim_rx_buffers(struct macb_device *macb,
332 unsigned int new_tail)
338 macb_invalidate_ring_desc(macb, RX);
339 while (i > new_tail) {
340 macb->rx_ring[i].addr &= ~RXADDR_USED;
342 if (i > MACB_RX_RING_SIZE)
346 while (i < new_tail) {
347 macb->rx_ring[i].addr &= ~RXADDR_USED;
352 macb_flush_ring_desc(macb, RX);
353 macb->rx_tail = new_tail;
356 static int _macb_recv(struct macb_device *macb, uchar **packetp)
358 unsigned int next_rx_tail = macb->next_rx_tail;
363 macb->wrapped = false;
365 macb_invalidate_ring_desc(macb, RX);
367 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
370 status = macb->rx_ring[next_rx_tail].ctrl;
371 if (status & RXBUF_FRAME_START) {
372 if (next_rx_tail != macb->rx_tail)
373 reclaim_rx_buffers(macb, next_rx_tail);
374 macb->wrapped = false;
377 if (status & RXBUF_FRAME_END) {
378 buffer = macb->rx_buffer + 128 * macb->rx_tail;
379 length = status & RXBUF_FRMLEN_MASK;
381 macb_invalidate_rx_buffer(macb);
383 unsigned int headlen, taillen;
385 headlen = 128 * (MACB_RX_RING_SIZE
387 taillen = length - headlen;
388 memcpy((void *)net_rx_packets[0],
390 memcpy((void *)net_rx_packets[0] + headlen,
391 macb->rx_buffer, taillen);
392 *packetp = (void *)net_rx_packets[0];
397 if (++next_rx_tail >= MACB_RX_RING_SIZE)
399 macb->next_rx_tail = next_rx_tail;
402 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
403 macb->wrapped = true;
411 static void macb_phy_reset(struct macb_device *macb, const char *name)
416 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
417 macb_mdio_write(macb, MII_ADVERTISE, adv);
418 printf("%s: Starting autonegotiation...\n", name);
419 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
422 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
423 status = macb_mdio_read(macb, MII_BMSR);
424 if (status & BMSR_ANEGCOMPLETE)
429 if (status & BMSR_ANEGCOMPLETE)
430 printf("%s: Autonegotiation complete\n", name);
432 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
436 #ifdef CONFIG_MACB_SEARCH_PHY
437 static int macb_phy_find(struct macb_device *macb)
442 /* Search for PHY... */
443 for (i = 0; i < 32; i++) {
445 phy_id = macb_mdio_read(macb, MII_PHYSID1);
446 if (phy_id != 0xffff) {
447 printf("%s: PHY present at %d\n", macb->netdev.name, i);
452 /* PHY isn't up to snuff */
453 printf("%s: PHY not found\n", macb->netdev.name);
457 #endif /* CONFIG_MACB_SEARCH_PHY */
460 static int macb_phy_init(struct macb_device *macb, const char *name)
463 struct phy_device *phydev;
466 u16 phy_id, status, adv, lpa;
467 int media, speed, duplex;
470 arch_get_mdio_control(name);
471 #ifdef CONFIG_MACB_SEARCH_PHY
472 /* Auto-detect phy_addr */
473 if (!macb_phy_find(macb))
475 #endif /* CONFIG_MACB_SEARCH_PHY */
477 /* Check if the PHY is up to snuff... */
478 phy_id = macb_mdio_read(macb, MII_PHYSID1);
479 if (phy_id == 0xffff) {
480 printf("%s: No PHY present\n", name);
485 /* need to consider other phy interface mode */
486 phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
487 PHY_INTERFACE_MODE_RGMII);
489 printf("phy_connect failed\n");
496 status = macb_mdio_read(macb, MII_BMSR);
497 if (!(status & BMSR_LSTATUS)) {
498 /* Try to re-negotiate if we don't have link already. */
499 macb_phy_reset(macb, name);
501 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
502 status = macb_mdio_read(macb, MII_BMSR);
503 if (status & BMSR_LSTATUS)
509 if (!(status & BMSR_LSTATUS)) {
510 printf("%s: link down (status: 0x%04x)\n",
515 /* First check for GMAC and that it is GiB capable */
516 if (gem_is_gigabit_capable(macb)) {
517 lpa = macb_mdio_read(macb, MII_STAT1000);
519 if (lpa & (LPA_1000FULL | LPA_1000HALF)) {
520 duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
522 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
524 duplex ? "full" : "half",
527 ncfgr = macb_readl(macb, NCFGR);
528 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
529 ncfgr |= GEM_BIT(GBE);
532 ncfgr |= MACB_BIT(FD);
534 macb_writel(macb, NCFGR, ncfgr);
540 /* fall back for EMAC checking */
541 adv = macb_mdio_read(macb, MII_ADVERTISE);
542 lpa = macb_mdio_read(macb, MII_LPA);
543 media = mii_nway_result(lpa & adv);
544 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
546 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
547 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
549 speed ? "100" : "10",
550 duplex ? "full" : "half",
553 ncfgr = macb_readl(macb, NCFGR);
554 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
556 ncfgr |= MACB_BIT(SPD);
558 ncfgr |= MACB_BIT(FD);
559 macb_writel(macb, NCFGR, ncfgr);
564 static int gmac_init_multi_queues(struct macb_device *macb)
566 int i, num_queues = 1;
569 /* bit 0 is never set but queue 0 always exists */
570 queue_mask = gem_readl(macb, DCFG6) & 0xff;
573 for (i = 1; i < MACB_MAX_QUEUES; i++)
574 if (queue_mask & (1 << i))
577 macb->dummy_desc->ctrl = TXBUF_USED;
578 macb->dummy_desc->addr = 0;
579 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
580 MACB_TX_DUMMY_DMA_DESC_SIZE);
582 for (i = 1; i < num_queues; i++)
583 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
588 static int _macb_init(struct macb_device *macb, const char *name)
594 * macb_halt should have been called at some point before now,
595 * so we'll assume the controller is idle.
598 /* initialize DMA descriptors */
599 paddr = macb->rx_buffer_dma;
600 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
601 if (i == (MACB_RX_RING_SIZE - 1))
602 paddr |= RXADDR_WRAP;
603 macb->rx_ring[i].addr = paddr;
604 macb->rx_ring[i].ctrl = 0;
607 macb_flush_ring_desc(macb, RX);
608 macb_flush_rx_buffer(macb);
610 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
611 macb->tx_ring[i].addr = 0;
612 if (i == (MACB_TX_RING_SIZE - 1))
613 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
615 macb->tx_ring[i].ctrl = TXBUF_USED;
617 macb_flush_ring_desc(macb, TX);
622 macb->next_rx_tail = 0;
624 macb_writel(macb, RBQP, macb->rx_ring_dma);
625 macb_writel(macb, TBQP, macb->tx_ring_dma);
627 if (macb_is_gem(macb)) {
628 /* Check the multi queue and initialize the queue for tx */
629 gmac_init_multi_queues(macb);
632 * When the GMAC IP with GE feature, this bit is used to
633 * select interface between RGMII and GMII.
634 * When the GMAC IP without GE feature, this bit is used
635 * to select interface between RMII and MII.
637 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
638 gem_writel(macb, UR, GEM_BIT(RGMII));
640 gem_writel(macb, UR, 0);
643 /* choose RMII or MII mode. This depends on the board */
645 #ifdef CONFIG_AT91FAMILY
646 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
648 macb_writel(macb, USRIO, 0);
651 #ifdef CONFIG_AT91FAMILY
652 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
654 macb_writel(macb, USRIO, MACB_BIT(MII));
656 #endif /* CONFIG_RMII */
659 if (!macb_phy_init(macb, name))
662 /* Enable TX and RX */
663 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
668 static void _macb_halt(struct macb_device *macb)
672 /* Halt the controller and wait for any ongoing transmission to end. */
673 ncr = macb_readl(macb, NCR);
674 ncr |= MACB_BIT(THALT);
675 macb_writel(macb, NCR, ncr);
678 tsr = macb_readl(macb, TSR);
679 } while (tsr & MACB_BIT(TGO));
681 /* Disable TX and RX, and clear statistics */
682 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
685 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
690 /* set hardware address */
691 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
692 enetaddr[2] << 16 | enetaddr[3] << 24;
693 macb_writel(macb, SA1B, hwaddr_bottom);
694 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
695 macb_writel(macb, SA1T, hwaddr_top);
699 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
702 unsigned long macb_hz = get_macb_pclk_rate(id);
704 if (macb_hz < 20000000)
705 config = MACB_BF(CLK, MACB_CLK_DIV8);
706 else if (macb_hz < 40000000)
707 config = MACB_BF(CLK, MACB_CLK_DIV16);
708 else if (macb_hz < 80000000)
709 config = MACB_BF(CLK, MACB_CLK_DIV32);
711 config = MACB_BF(CLK, MACB_CLK_DIV64);
716 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
719 unsigned long macb_hz = get_macb_pclk_rate(id);
721 if (macb_hz < 20000000)
722 config = GEM_BF(CLK, GEM_CLK_DIV8);
723 else if (macb_hz < 40000000)
724 config = GEM_BF(CLK, GEM_CLK_DIV16);
725 else if (macb_hz < 80000000)
726 config = GEM_BF(CLK, GEM_CLK_DIV32);
727 else if (macb_hz < 120000000)
728 config = GEM_BF(CLK, GEM_CLK_DIV48);
729 else if (macb_hz < 160000000)
730 config = GEM_BF(CLK, GEM_CLK_DIV64);
732 config = GEM_BF(CLK, GEM_CLK_DIV96);
738 * Get the DMA bus width field of the network configuration register that we
739 * should program. We find the width from decoding the design configuration
740 * register to find the maximum supported data bus width.
742 static u32 macb_dbw(struct macb_device *macb)
744 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
746 return GEM_BF(DBW, GEM_DBW128);
748 return GEM_BF(DBW, GEM_DBW64);
751 return GEM_BF(DBW, GEM_DBW32);
755 static void _macb_eth_initialize(struct macb_device *macb)
757 int id = 0; /* This is not used by functions we call */
760 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
761 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
762 &macb->rx_buffer_dma);
763 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
765 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
767 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
768 &macb->dummy_desc_dma);
771 * Do some basic initialization so that we at least can talk
774 if (macb_is_gem(macb)) {
775 ncfgr = gem_mdc_clk_div(id, macb);
776 ncfgr |= macb_dbw(macb);
778 ncfgr = macb_mdc_clk_div(id, macb);
781 macb_writel(macb, NCFGR, ncfgr);
784 #ifndef CONFIG_DM_ETH
785 static int macb_send(struct eth_device *netdev, void *packet, int length)
787 struct macb_device *macb = to_macb(netdev);
789 return _macb_send(macb, netdev->name, packet, length);
792 static int macb_recv(struct eth_device *netdev)
794 struct macb_device *macb = to_macb(netdev);
798 macb->wrapped = false;
800 macb->next_rx_tail = macb->rx_tail;
801 length = _macb_recv(macb, &packet);
803 net_process_received_packet(packet, length);
804 reclaim_rx_buffers(macb, macb->next_rx_tail);
805 } else if (length < 0) {
811 static int macb_init(struct eth_device *netdev, bd_t *bd)
813 struct macb_device *macb = to_macb(netdev);
815 return _macb_init(macb, netdev->name);
818 static void macb_halt(struct eth_device *netdev)
820 struct macb_device *macb = to_macb(netdev);
822 return _macb_halt(macb);
825 static int macb_write_hwaddr(struct eth_device *netdev)
827 struct macb_device *macb = to_macb(netdev);
829 return _macb_write_hwaddr(macb, netdev->enetaddr);
832 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
834 struct macb_device *macb;
835 struct eth_device *netdev;
837 macb = malloc(sizeof(struct macb_device));
839 printf("Error: Failed to allocate memory for MACB%d\n", id);
842 memset(macb, 0, sizeof(struct macb_device));
844 netdev = &macb->netdev;
847 macb->phy_addr = phy_addr;
849 if (macb_is_gem(macb))
850 sprintf(netdev->name, "gmac%d", id);
852 sprintf(netdev->name, "macb%d", id);
854 netdev->init = macb_init;
855 netdev->halt = macb_halt;
856 netdev->send = macb_send;
857 netdev->recv = macb_recv;
858 netdev->write_hwaddr = macb_write_hwaddr;
860 _macb_eth_initialize(macb);
862 eth_register(netdev);
864 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
865 miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write);
866 macb->bus = miiphy_get_dev_by_name(netdev->name);
870 #endif /* !CONFIG_DM_ETH */
874 static int macb_start(struct udevice *dev)
876 struct macb_device *macb = dev_get_priv(dev);
878 return _macb_init(macb, dev->name);
881 static int macb_send(struct udevice *dev, void *packet, int length)
883 struct macb_device *macb = dev_get_priv(dev);
885 return _macb_send(macb, dev->name, packet, length);
888 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
890 struct macb_device *macb = dev_get_priv(dev);
892 macb->next_rx_tail = macb->rx_tail;
893 macb->wrapped = false;
895 return _macb_recv(macb, packetp);
898 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
900 struct macb_device *macb = dev_get_priv(dev);
902 reclaim_rx_buffers(macb, macb->next_rx_tail);
907 static void macb_stop(struct udevice *dev)
909 struct macb_device *macb = dev_get_priv(dev);
914 static int macb_write_hwaddr(struct udevice *dev)
916 struct eth_pdata *plat = dev_get_platdata(dev);
917 struct macb_device *macb = dev_get_priv(dev);
919 return _macb_write_hwaddr(macb, plat->enetaddr);
922 static const struct eth_ops macb_eth_ops = {
927 .free_pkt = macb_free_pkt,
928 .write_hwaddr = macb_write_hwaddr,
931 static int macb_eth_probe(struct udevice *dev)
933 struct eth_pdata *pdata = dev_get_platdata(dev);
934 struct macb_device *macb = dev_get_priv(dev);
936 macb->regs = (void *)pdata->iobase;
938 _macb_eth_initialize(macb);
939 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
940 miiphy_register(dev->name, macb_miiphy_read, macb_miiphy_write);
941 macb->bus = miiphy_get_dev_by_name(dev->name);
947 static int macb_eth_ofdata_to_platdata(struct udevice *dev)
949 struct eth_pdata *pdata = dev_get_platdata(dev);
951 pdata->iobase = dev_get_addr(dev);
955 static const struct udevice_id macb_eth_ids[] = {
956 { .compatible = "cdns,macb" },
960 U_BOOT_DRIVER(eth_macb) = {
963 .of_match = macb_eth_ids,
964 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
965 .probe = macb_eth_probe,
966 .ops = &macb_eth_ops,
967 .priv_auto_alloc_size = sizeof(struct macb_device),
968 .platdata_auto_alloc_size = sizeof(struct eth_pdata),