drivers/net/ldpaa_eth/ls2085a.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <phy.h>
   8 #include <fsl-mc/ldpaa_wriop.h>
   9 #include <asm/io.h>
  10 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #include <fsl-mc/ldpaa_wriop.h>
  13
  14 u32 dpmac_to_devdisr[] = {
  15         [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
  16         [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
  17         [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
  18         [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
  19         [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
  20         [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
  21         [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
  22         [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
  23         [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
  24         [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
  25         [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
  26         [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
  27         [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
  28         [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
  29         [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
  30         [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
  31         [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
  32         [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
  33         [WRIOP1_DPMAC19] = FSL_CHASSIS3_DEVDISR2_DPMAC19,
  34         [WRIOP1_DPMAC20] = FSL_CHASSIS3_DEVDISR2_DPMAC20,
  35         [WRIOP1_DPMAC21] = FSL_CHASSIS3_DEVDISR2_DPMAC21,
  36         [WRIOP1_DPMAC22] = FSL_CHASSIS3_DEVDISR2_DPMAC22,
  37         [WRIOP1_DPMAC23] = FSL_CHASSIS3_DEVDISR2_DPMAC23,
  38         [WRIOP1_DPMAC24] = FSL_CHASSIS3_DEVDISR2_DPMAC24,
  39 };
  40
  41 static int is_device_disabled(int dpmac_id)
  42 {
  43         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  44         u32 devdisr2 = in_le32(&gur->devdisr2);
  45
  46         return dpmac_to_devdisr[dpmac_id] & devdisr2;
  47 }
  48
  49 void wriop_dpmac_disable(int dpmac_id)
  50 {
  51         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  52
  53         setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
  54 }
  55
  56 void wriop_dpmac_enable(int dpmac_id)
  57 {
  58         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  59
  60         clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
  61 }
  62
  63 phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
  64 {
  65         enum srds_prtcl;
  66
  67         if (is_device_disabled(dpmac_id + 1))
  68                 return PHY_INTERFACE_MODE_NONE;
  69
  70         if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16)
  71                 return PHY_INTERFACE_MODE_SGMII;
  72
  73         if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
  74                 return PHY_INTERFACE_MODE_XGMII;
  75
  76         if (lane_prtcl >= XAUI1 && lane_prtcl <= XAUI2)
  77                 return PHY_INTERFACE_MODE_XGMII;
  78
  79         if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D)
  80                 return PHY_INTERFACE_MODE_QSGMII;
  81
  82         return PHY_INTERFACE_MODE_NONE;
  83 }