1 // SPDX-License-Identifier: GPL-2.0+
3 * Micrel KS8851_MLL 16bit Network driver
4 * Copyright (c) 2011 Roberto Cerati <roberto.cerati@bticino.it>
14 #include <linux/delay.h>
16 #include "ks8851_mll.h"
18 #define DRIVERNAME "ks8851_mll"
20 #define RX_BUF_SIZE 2000
23 * struct ks_net - KS8851 driver private data
24 * @bus_width : i/o bus width.
25 * @sharedbus : Multipex(addr and data bus) mode indicator.
26 * @extra_byte : number of extra byte prepended rx pkt.
34 #define BE3 0x8000 /* Byte Enable 3 */
35 #define BE2 0x4000 /* Byte Enable 2 */
36 #define BE1 0x2000 /* Byte Enable 1 */
37 #define BE0 0x1000 /* Byte Enable 0 */
39 static u8 ks_rdreg8(struct eth_device *dev, u16 offset)
41 u8 shift_bit = offset & 0x03;
42 u8 shift_data = (offset & 1) << 3;
44 writew(offset | (BE0 << shift_bit), dev->iobase + 2);
46 return (u8)(readw(dev->iobase) >> shift_data);
49 static u16 ks_rdreg16(struct eth_device *dev, u16 offset)
51 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
53 return readw(dev->iobase);
56 static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val)
58 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
59 writew(val, dev->iobase);
63 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode
66 * @wptr: buffer address to save data
67 * @len: length in byte to read
69 static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len)
74 *wptr++ = readw(dev->iobase);
78 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
79 * @ks: The chip information
80 * @wptr: buffer address
81 * @len: length in byte to write
83 static inline void ks_outblk(struct eth_device *dev, u16 *wptr, u32 len)
88 writew(*wptr++, dev->iobase);
91 static void ks_enable_int(struct eth_device *dev)
93 ks_wrreg16(dev, KS_IER, IRQ_LCI | IRQ_TXI | IRQ_RXI);
96 static void ks_set_powermode(struct eth_device *dev, unsigned pwrmode)
100 ks_rdreg16(dev, KS_GRR);
101 pmecr = ks_rdreg16(dev, KS_PMECR);
102 pmecr &= ~PMECR_PM_MASK;
105 ks_wrreg16(dev, KS_PMECR, pmecr);
109 * ks_read_config - read chip configuration of bus width.
110 * @ks: The chip information
112 static void ks_read_config(struct eth_device *dev)
116 /* Regardless of bus width, 8 bit read should always work. */
117 reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF;
118 reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8;
120 /* addr/data bus are multiplexed */
121 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
124 * There are garbage data when reading data from QMU,
125 * depending on bus-width.
127 if (reg_data & CCR_8BIT) {
128 ks->bus_width = ENUM_BUS_8BIT;
130 } else if (reg_data & CCR_16BIT) {
131 ks->bus_width = ENUM_BUS_16BIT;
134 ks->bus_width = ENUM_BUS_32BIT;
140 * ks_soft_reset - issue one of the soft reset to the device
141 * @ks: The device state.
142 * @op: The bit(s) to set in the GRR
144 * Issue the relevant soft-reset command to the device's GRR register
147 * Note, the delays are in there as a caution to ensure that the reset
148 * has time to take effect and then complete. Since the datasheet does
149 * not currently specify the exact sequence, we have chosen something
150 * that seems to work with our device.
152 static void ks_soft_reset(struct eth_device *dev, unsigned op)
154 /* Disable interrupt first */
155 ks_wrreg16(dev, KS_IER, 0x0000);
156 ks_wrreg16(dev, KS_GRR, op);
157 mdelay(10); /* wait a short time to effect reset */
158 ks_wrreg16(dev, KS_GRR, 0);
159 mdelay(1); /* wait for condition to clear */
162 void ks_enable_qmu(struct eth_device *dev)
166 w = ks_rdreg16(dev, KS_TXCR);
168 /* Enables QMU Transmit (TXCR). */
169 ks_wrreg16(dev, KS_TXCR, w | TXCR_TXE);
171 /* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */
172 w = ks_rdreg16(dev, KS_RXQCR);
173 ks_wrreg16(dev, KS_RXQCR, w | RXQCR_RXFCTE);
175 /* Enables QMU Receive (RXCR1). */
176 w = ks_rdreg16(dev, KS_RXCR1);
177 ks_wrreg16(dev, KS_RXCR1, w | RXCR1_RXE);
180 static void ks_disable_qmu(struct eth_device *dev)
184 w = ks_rdreg16(dev, KS_TXCR);
186 /* Disables QMU Transmit (TXCR). */
188 ks_wrreg16(dev, KS_TXCR, w);
190 /* Disables QMU Receive (RXCR1). */
191 w = ks_rdreg16(dev, KS_RXCR1);
193 ks_wrreg16(dev, KS_RXCR1, w);
196 static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len)
198 u32 r = ks->extra_byte & 0x1;
199 u32 w = ks->extra_byte - r;
201 /* 1. set sudo DMA mode */
202 ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
203 ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
206 * 2. read prepend data
208 * read 4 + extra bytes and discard them.
209 * extra bytes for dummy, 2 for status, 2 for len
215 ks_inblk(dev, buf, w + 2 + 2);
217 /* 3. read pkt data */
218 ks_inblk(dev, buf, ALIGN(len, 4));
220 /* 4. reset sudo DMA Mode */
221 ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL);
224 static void ks_rcv(struct eth_device *dev, uchar **pv_data)
226 unsigned int frame_cnt;
230 frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8;
232 /* read all header information */
233 for (i = 0; i < frame_cnt; i++) {
234 /* Checking Received packet status */
235 sts = ks_rdreg16(dev, KS_RXFHSR);
236 /* Get packet len from hardware */
237 len = ks_rdreg16(dev, KS_RXFHBCR);
239 if ((sts & RXFSHR_RXFV) && len && (len < RX_BUF_SIZE)) {
240 /* read data block including CRC 4 bytes */
241 ks_read_qmu(dev, (u16 *)(*pv_data), len);
243 /* net_rx_packets buffer size is ok (*pv_data) */
244 net_process_received_packet(*pv_data, len);
247 ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF);
248 printf(DRIVERNAME ": bad packet\n");
254 * ks_read_selftest - read the selftest memory info.
255 * @ks: The device state
257 * Read and check the TX/RX memory selftest information.
259 static int ks_read_selftest(struct eth_device *dev)
261 u16 both_done = MBIR_TXMBF | MBIR_RXMBF;
265 mbir = ks_rdreg16(dev, KS_MBIR);
267 if ((mbir & both_done) != both_done) {
268 printf(DRIVERNAME ": Memory selftest not finished\n");
272 if (mbir & MBIR_TXMBFA) {
273 printf(DRIVERNAME ": TX memory selftest fails\n");
277 if (mbir & MBIR_RXMBFA) {
278 printf(DRIVERNAME ": RX memory selftest fails\n");
282 debug(DRIVERNAME ": the selftest passes\n");
287 static void ks_setup(struct eth_device *dev)
291 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
292 ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
294 /* Setup Receive Frame Data Pointer Auto-Increment */
295 ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
297 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
298 ks_wrreg16(dev, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
300 /* Setup RxQ Command Control (RXQCR) */
301 ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL);
304 * set the force mode to half duplex, default is full duplex
305 * because if the auto-negotiation fails, most switch uses
308 w = ks_rdreg16(dev, KS_P1MBCR);
309 w &= ~P1MBCR_FORCE_FDX;
310 ks_wrreg16(dev, KS_P1MBCR, w);
312 w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
313 ks_wrreg16(dev, KS_TXCR, w);
315 w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
320 ks_wrreg16(dev, KS_RXCR1, w);
323 static void ks_setup_int(struct eth_device *dev)
325 /* Clear the interrupts status of the hardware. */
326 ks_wrreg16(dev, KS_ISR, 0xffff);
329 static int ks8851_mll_detect_chip(struct eth_device *dev)
335 val = ks_rdreg16(dev, KS_CIDER);
338 /* Special case -- no chip present */
339 printf(DRIVERNAME ": is chip mounted ?\n");
341 } else if ((val & 0xfff0) != CIDER_ID) {
342 printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val);
346 debug("Read back KS8851 id 0x%x\n", val);
348 if ((val & 0xfff0) != CIDER_ID) {
349 printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
356 static void ks8851_mll_reset(struct eth_device *dev)
358 /* wake up powermode to normal mode */
359 ks_set_powermode(dev, PMECR_PM_NORMAL);
360 mdelay(1); /* wait for normal mode to take effect */
362 /* Disable interrupt and reset */
363 ks_soft_reset(dev, GRR_GSR);
365 /* turn off the IRQs and ack any outstanding */
366 ks_wrreg16(dev, KS_IER, 0x0000);
367 ks_wrreg16(dev, KS_ISR, 0xffff);
369 /* shutdown RX/TX QMU */
373 static void ks8851_mll_phy_configure(struct eth_device *dev)
380 /* Probing the phy */
381 data = ks_rdreg16(dev, KS_OBCR);
382 ks_wrreg16(dev, KS_OBCR, data | OBCR_ODS_16MA);
384 debug(DRIVERNAME ": phy initialized\n");
387 static void ks8851_mll_enable(struct eth_device *dev)
389 ks_wrreg16(dev, KS_ISR, 0xffff);
394 static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
396 if (ks_read_selftest(dev)) {
397 printf(DRIVERNAME ": Selftest failed\n");
401 ks8851_mll_reset(dev);
403 /* Configure the PHY, initialize the link state */
404 ks8851_mll_phy_configure(dev);
406 /* Turn on Tx + Rx */
407 ks8851_mll_enable(dev);
412 static void ks_write_qmu(struct eth_device *dev, u8 *pdata, u16 len)
415 /* start header at txb[0] to align txw entries */
417 txw[1] = cpu_to_le16(len);
419 /* 1. set sudo-DMA mode */
420 ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
421 ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
422 /* 2. write status/lenth info */
423 ks_outblk(dev, txw, 4);
424 /* 3. write pkt data */
425 ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4));
426 /* 4. reset sudo-DMA mode */
427 ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL);
428 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
429 ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE);
430 /* 6. wait until TXQCR_METFE is auto-cleared */
431 do { } while (ks_rdreg16(dev, KS_TXQCR) & TXQCR_METFE);
434 static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
436 u8 *data = (u8 *)packet;
437 u16 tmplen = (u16)length;
441 * Extra space are required:
442 * 4 byte for alignment, 4 for status/length, 4 for CRC
444 retv = ks_rdreg16(dev, KS_TXMIR) & 0x1fff;
445 if (retv >= tmplen + 12) {
446 ks_write_qmu(dev, data, tmplen);
449 printf(DRIVERNAME ": failed to send packet: No buffer\n");
454 static void ks8851_mll_halt(struct eth_device *dev)
456 ks8851_mll_reset(dev);
460 * Maximum receive ring size; that is, the number of packets
461 * we can buffer before overflow happens. Basically, this just
462 * needs to be enough to prevent a packet being discarded while
463 * we are processing the previous one.
465 static int ks8851_mll_recv(struct eth_device *dev)
469 status = ks_rdreg16(dev, KS_ISR);
471 ks_wrreg16(dev, KS_ISR, status);
473 if ((status & IRQ_RXI))
474 ks_rcv(dev, (uchar **)net_rx_packets);
476 if ((status & IRQ_LDI)) {
477 u16 pmecr = ks_rdreg16(dev, KS_PMECR);
478 pmecr &= ~PMECR_WKEVT_MASK;
479 ks_wrreg16(dev, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
485 static int ks8851_mll_write_hwaddr(struct eth_device *dev)
487 u16 addrl, addrm, addrh;
489 addrh = (dev->enetaddr[0] << 8) | dev->enetaddr[1];
490 addrm = (dev->enetaddr[2] << 8) | dev->enetaddr[3];
491 addrl = (dev->enetaddr[4] << 8) | dev->enetaddr[5];
493 ks_wrreg16(dev, KS_MARH, addrh);
494 ks_wrreg16(dev, KS_MARM, addrm);
495 ks_wrreg16(dev, KS_MARL, addrl);
500 int ks8851_mll_initialize(u8 dev_num, int base_addr)
502 struct eth_device *dev;
504 dev = calloc(1, sizeof(*dev));
508 dev->iobase = base_addr;
512 /* Try to detect chip. Will fail if not present. */
513 if (ks8851_mll_detect_chip(dev)) {
518 dev->init = ks8851_mll_init;
519 dev->halt = ks8851_mll_halt;
520 dev->send = ks8851_mll_send;
521 dev->recv = ks8851_mll_recv;
522 dev->write_hwaddr = ks8851_mll_write_hwaddr;
523 sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);