1 // SPDX-License-Identifier: GPL-2.0+
3 * Micrel KS8851_MLL 16bit Network driver
4 * Copyright (c) 2011 Roberto Cerati <roberto.cerati@bticino.it>
14 #include <linux/delay.h>
16 #include "ks8851_mll.h"
18 #define DRIVERNAME "ks8851_mll"
20 #define RX_BUF_SIZE 2000
22 static const struct chip_id chip_ids[] = {
23 {CIDER_ID, "KSZ8851"},
28 * struct ks_net - KS8851 driver private data
29 * @bus_width : i/o bus width.
30 * @sharedbus : Multipex(addr and data bus) mode indicator.
31 * @extra_byte : number of extra byte prepended rx pkt.
39 #define BE3 0x8000 /* Byte Enable 3 */
40 #define BE2 0x4000 /* Byte Enable 2 */
41 #define BE1 0x2000 /* Byte Enable 1 */
42 #define BE0 0x1000 /* Byte Enable 0 */
44 static u8 ks_rdreg8(struct eth_device *dev, u16 offset)
46 u8 shift_bit = offset & 0x03;
47 u8 shift_data = (offset & 1) << 3;
49 writew(offset | (BE0 << shift_bit), dev->iobase + 2);
51 return (u8)(readw(dev->iobase) >> shift_data);
54 static u16 ks_rdreg16(struct eth_device *dev, u16 offset)
56 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
58 return readw(dev->iobase);
61 static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val)
63 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
64 writew(val, dev->iobase);
68 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode
71 * @wptr: buffer address to save data
72 * @len: length in byte to read
74 static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len)
79 *wptr++ = readw(dev->iobase);
83 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
84 * @ks: The chip information
85 * @wptr: buffer address
86 * @len: length in byte to write
88 static inline void ks_outblk(struct eth_device *dev, u16 *wptr, u32 len)
93 writew(*wptr++, dev->iobase);
96 static void ks_enable_int(struct eth_device *dev)
98 ks_wrreg16(dev, KS_IER, IRQ_LCI | IRQ_TXI | IRQ_RXI);
101 static void ks_set_powermode(struct eth_device *dev, unsigned pwrmode)
105 ks_rdreg16(dev, KS_GRR);
106 pmecr = ks_rdreg16(dev, KS_PMECR);
107 pmecr &= ~PMECR_PM_MASK;
110 ks_wrreg16(dev, KS_PMECR, pmecr);
114 * ks_read_config - read chip configuration of bus width.
115 * @ks: The chip information
117 static void ks_read_config(struct eth_device *dev)
121 /* Regardless of bus width, 8 bit read should always work. */
122 reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF;
123 reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8;
125 /* addr/data bus are multiplexed */
126 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
129 * There are garbage data when reading data from QMU,
130 * depending on bus-width.
132 if (reg_data & CCR_8BIT) {
133 ks->bus_width = ENUM_BUS_8BIT;
135 } else if (reg_data & CCR_16BIT) {
136 ks->bus_width = ENUM_BUS_16BIT;
139 ks->bus_width = ENUM_BUS_32BIT;
145 * ks_soft_reset - issue one of the soft reset to the device
146 * @ks: The device state.
147 * @op: The bit(s) to set in the GRR
149 * Issue the relevant soft-reset command to the device's GRR register
152 * Note, the delays are in there as a caution to ensure that the reset
153 * has time to take effect and then complete. Since the datasheet does
154 * not currently specify the exact sequence, we have chosen something
155 * that seems to work with our device.
157 static void ks_soft_reset(struct eth_device *dev, unsigned op)
159 /* Disable interrupt first */
160 ks_wrreg16(dev, KS_IER, 0x0000);
161 ks_wrreg16(dev, KS_GRR, op);
162 mdelay(10); /* wait a short time to effect reset */
163 ks_wrreg16(dev, KS_GRR, 0);
164 mdelay(1); /* wait for condition to clear */
167 void ks_enable_qmu(struct eth_device *dev)
171 w = ks_rdreg16(dev, KS_TXCR);
173 /* Enables QMU Transmit (TXCR). */
174 ks_wrreg16(dev, KS_TXCR, w | TXCR_TXE);
176 /* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */
177 w = ks_rdreg16(dev, KS_RXQCR);
178 ks_wrreg16(dev, KS_RXQCR, w | RXQCR_RXFCTE);
180 /* Enables QMU Receive (RXCR1). */
181 w = ks_rdreg16(dev, KS_RXCR1);
182 ks_wrreg16(dev, KS_RXCR1, w | RXCR1_RXE);
185 static void ks_disable_qmu(struct eth_device *dev)
189 w = ks_rdreg16(dev, KS_TXCR);
191 /* Disables QMU Transmit (TXCR). */
193 ks_wrreg16(dev, KS_TXCR, w);
195 /* Disables QMU Receive (RXCR1). */
196 w = ks_rdreg16(dev, KS_RXCR1);
198 ks_wrreg16(dev, KS_RXCR1, w);
201 static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len)
203 u32 r = ks->extra_byte & 0x1;
204 u32 w = ks->extra_byte - r;
206 /* 1. set sudo DMA mode */
207 ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
208 ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
211 * 2. read prepend data
213 * read 4 + extra bytes and discard them.
214 * extra bytes for dummy, 2 for status, 2 for len
220 ks_inblk(dev, buf, w + 2 + 2);
222 /* 3. read pkt data */
223 ks_inblk(dev, buf, ALIGN(len, 4));
225 /* 4. reset sudo DMA Mode */
226 ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL);
229 static void ks_rcv(struct eth_device *dev, uchar **pv_data)
231 unsigned int frame_cnt;
235 frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8;
237 /* read all header information */
238 for (i = 0; i < frame_cnt; i++) {
239 /* Checking Received packet status */
240 sts = ks_rdreg16(dev, KS_RXFHSR);
241 /* Get packet len from hardware */
242 len = ks_rdreg16(dev, KS_RXFHBCR);
244 if ((sts & RXFSHR_RXFV) && len && (len < RX_BUF_SIZE)) {
245 /* read data block including CRC 4 bytes */
246 ks_read_qmu(dev, (u16 *)(*pv_data), len);
248 /* net_rx_packets buffer size is ok (*pv_data) */
249 net_process_received_packet(*pv_data, len);
252 ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF);
253 printf(DRIVERNAME ": bad packet\n");
259 * ks_read_selftest - read the selftest memory info.
260 * @ks: The device state
262 * Read and check the TX/RX memory selftest information.
264 static int ks_read_selftest(struct eth_device *dev)
266 u16 both_done = MBIR_TXMBF | MBIR_RXMBF;
270 mbir = ks_rdreg16(dev, KS_MBIR);
272 if ((mbir & both_done) != both_done) {
273 printf(DRIVERNAME ": Memory selftest not finished\n");
277 if (mbir & MBIR_TXMBFA) {
278 printf(DRIVERNAME ": TX memory selftest fails\n");
282 if (mbir & MBIR_RXMBFA) {
283 printf(DRIVERNAME ": RX memory selftest fails\n");
287 debug(DRIVERNAME ": the selftest passes\n");
292 static void ks_setup(struct eth_device *dev)
296 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
297 ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
299 /* Setup Receive Frame Data Pointer Auto-Increment */
300 ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
302 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
303 ks_wrreg16(dev, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
305 /* Setup RxQ Command Control (RXQCR) */
306 ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL);
309 * set the force mode to half duplex, default is full duplex
310 * because if the auto-negotiation fails, most switch uses
313 w = ks_rdreg16(dev, KS_P1MBCR);
314 w &= ~P1MBCR_FORCE_FDX;
315 ks_wrreg16(dev, KS_P1MBCR, w);
317 w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
318 ks_wrreg16(dev, KS_TXCR, w);
320 w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
325 ks_wrreg16(dev, KS_RXCR1, w);
328 static void ks_setup_int(struct eth_device *dev)
330 /* Clear the interrupts status of the hardware. */
331 ks_wrreg16(dev, KS_ISR, 0xffff);
334 static int ks8851_mll_detect_chip(struct eth_device *dev)
336 unsigned short val, i;
340 val = ks_rdreg16(dev, KS_CIDER);
343 /* Special case -- no chip present */
344 printf(DRIVERNAME ": is chip mounted ?\n");
346 } else if ((val & 0xfff0) != CIDER_ID) {
347 printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val);
351 debug("Read back KS8851 id 0x%x\n", val);
353 /* only one entry in the table */
355 for (i = 0; chip_ids[i].id != 0; i++) {
356 if (chip_ids[i].id == val)
359 if (!chip_ids[i].id) {
360 printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
364 dev->priv = (void *)&chip_ids[i];
369 static void ks8851_mll_reset(struct eth_device *dev)
371 /* wake up powermode to normal mode */
372 ks_set_powermode(dev, PMECR_PM_NORMAL);
373 mdelay(1); /* wait for normal mode to take effect */
375 /* Disable interrupt and reset */
376 ks_soft_reset(dev, GRR_GSR);
378 /* turn off the IRQs and ack any outstanding */
379 ks_wrreg16(dev, KS_IER, 0x0000);
380 ks_wrreg16(dev, KS_ISR, 0xffff);
382 /* shutdown RX/TX QMU */
386 static void ks8851_mll_phy_configure(struct eth_device *dev)
393 /* Probing the phy */
394 data = ks_rdreg16(dev, KS_OBCR);
395 ks_wrreg16(dev, KS_OBCR, data | OBCR_ODS_16MA);
397 debug(DRIVERNAME ": phy initialized\n");
400 static void ks8851_mll_enable(struct eth_device *dev)
402 ks_wrreg16(dev, KS_ISR, 0xffff);
407 static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
409 struct chip_id *id = dev->priv;
411 debug(DRIVERNAME ": detected %s controller\n", id->name);
413 if (ks_read_selftest(dev)) {
414 printf(DRIVERNAME ": Selftest failed\n");
418 ks8851_mll_reset(dev);
420 /* Configure the PHY, initialize the link state */
421 ks8851_mll_phy_configure(dev);
423 /* Turn on Tx + Rx */
424 ks8851_mll_enable(dev);
429 static void ks_write_qmu(struct eth_device *dev, u8 *pdata, u16 len)
432 /* start header at txb[0] to align txw entries */
434 txw[1] = cpu_to_le16(len);
436 /* 1. set sudo-DMA mode */
437 ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
438 ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
439 /* 2. write status/lenth info */
440 ks_outblk(dev, txw, 4);
441 /* 3. write pkt data */
442 ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4));
443 /* 4. reset sudo-DMA mode */
444 ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL);
445 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
446 ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE);
447 /* 6. wait until TXQCR_METFE is auto-cleared */
448 do { } while (ks_rdreg16(dev, KS_TXQCR) & TXQCR_METFE);
451 static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
453 u8 *data = (u8 *)packet;
454 u16 tmplen = (u16)length;
458 * Extra space are required:
459 * 4 byte for alignment, 4 for status/length, 4 for CRC
461 retv = ks_rdreg16(dev, KS_TXMIR) & 0x1fff;
462 if (retv >= tmplen + 12) {
463 ks_write_qmu(dev, data, tmplen);
466 printf(DRIVERNAME ": failed to send packet: No buffer\n");
471 static void ks8851_mll_halt(struct eth_device *dev)
473 ks8851_mll_reset(dev);
477 * Maximum receive ring size; that is, the number of packets
478 * we can buffer before overflow happens. Basically, this just
479 * needs to be enough to prevent a packet being discarded while
480 * we are processing the previous one.
482 static int ks8851_mll_recv(struct eth_device *dev)
486 status = ks_rdreg16(dev, KS_ISR);
488 ks_wrreg16(dev, KS_ISR, status);
490 if ((status & IRQ_RXI))
491 ks_rcv(dev, (uchar **)net_rx_packets);
493 if ((status & IRQ_LDI)) {
494 u16 pmecr = ks_rdreg16(dev, KS_PMECR);
495 pmecr &= ~PMECR_WKEVT_MASK;
496 ks_wrreg16(dev, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
502 static int ks8851_mll_write_hwaddr(struct eth_device *dev)
504 u16 addrl, addrm, addrh;
506 addrh = (dev->enetaddr[0] << 8) | dev->enetaddr[1];
507 addrm = (dev->enetaddr[2] << 8) | dev->enetaddr[3];
508 addrl = (dev->enetaddr[4] << 8) | dev->enetaddr[5];
510 ks_wrreg16(dev, KS_MARH, addrh);
511 ks_wrreg16(dev, KS_MARM, addrm);
512 ks_wrreg16(dev, KS_MARL, addrl);
517 int ks8851_mll_initialize(u8 dev_num, int base_addr)
519 struct eth_device *dev;
521 dev = calloc(1, sizeof(*dev));
525 dev->iobase = base_addr;
529 /* Try to detect chip. Will fail if not present. */
530 if (ks8851_mll_detect_chip(dev)) {
535 dev->init = ks8851_mll_init;
536 dev->halt = ks8851_mll_halt;
537 dev->send = ks8851_mll_send;
538 dev->recv = ks8851_mll_recv;
539 dev->write_hwaddr = ks8851_mll_write_hwaddr;
540 sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);