1 // SPDX-License-Identifier: GPL-2.0+
3 * Micrel KS8851_MLL 16bit Network driver
4 * Copyright (c) 2011 Roberto Cerati <roberto.cerati@bticino.it>
14 #include <linux/delay.h>
16 #include "ks8851_mll.h"
18 #define DRIVERNAME "ks8851_mll"
20 #define RX_BUF_SIZE 2000
23 * struct ks_net - KS8851 driver private data
24 * @dev : legacy non-DM ethernet device structure
25 * @iobase : register base
26 * @bus_width : i/o bus width.
27 * @sharedbus : Multipex(addr and data bus) mode indicator.
28 * @extra_byte : number of extra byte prepended rx pkt.
31 struct eth_device dev;
39 #define BE3 0x8000 /* Byte Enable 3 */
40 #define BE2 0x4000 /* Byte Enable 2 */
41 #define BE1 0x2000 /* Byte Enable 1 */
42 #define BE0 0x1000 /* Byte Enable 0 */
44 static u8 ks_rdreg8(struct ks_net *ks, u16 offset)
46 u8 shift_bit = offset & 0x03;
47 u8 shift_data = (offset & 1) << 3;
49 writew(offset | (BE0 << shift_bit), ks->iobase + 2);
51 return (u8)(readw(ks->iobase) >> shift_data);
54 static u16 ks_rdreg16(struct ks_net *ks, u16 offset)
56 writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
58 return readw(ks->iobase);
61 static void ks_wrreg16(struct ks_net *ks, u16 offset, u16 val)
63 writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
64 writew(val, ks->iobase);
68 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode
71 * @wptr: buffer address to save data
72 * @len: length in byte to read
74 static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len)
79 *wptr++ = readw(ks->iobase);
83 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
84 * @ks: The chip information
85 * @wptr: buffer address
86 * @len: length in byte to write
88 static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
93 writew(*wptr++, ks->iobase);
96 static void ks_enable_int(struct ks_net *ks)
98 ks_wrreg16(ks, KS_IER, IRQ_LCI | IRQ_TXI | IRQ_RXI);
101 static void ks_set_powermode(struct ks_net *ks, unsigned int pwrmode)
105 ks_rdreg16(ks, KS_GRR);
106 pmecr = ks_rdreg16(ks, KS_PMECR);
107 pmecr &= ~PMECR_PM_MASK;
110 ks_wrreg16(ks, KS_PMECR, pmecr);
114 * ks_read_config - read chip configuration of bus width.
115 * @ks: The chip information
117 static void ks_read_config(struct ks_net *ks)
121 /* Regardless of bus width, 8 bit read should always work. */
122 reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF;
123 reg_data |= ks_rdreg8(ks, KS_CCR + 1) << 8;
125 /* addr/data bus are multiplexed */
126 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
129 * There are garbage data when reading data from QMU,
130 * depending on bus-width.
132 if (reg_data & CCR_8BIT) {
133 ks->bus_width = ENUM_BUS_8BIT;
135 } else if (reg_data & CCR_16BIT) {
136 ks->bus_width = ENUM_BUS_16BIT;
139 ks->bus_width = ENUM_BUS_32BIT;
145 * ks_soft_reset - issue one of the soft reset to the device
146 * @ks: The device state.
147 * @op: The bit(s) to set in the GRR
149 * Issue the relevant soft-reset command to the device's GRR register
152 * Note, the delays are in there as a caution to ensure that the reset
153 * has time to take effect and then complete. Since the datasheet does
154 * not currently specify the exact sequence, we have chosen something
155 * that seems to work with our device.
157 static void ks_soft_reset(struct ks_net *ks, unsigned int op)
159 /* Disable interrupt first */
160 ks_wrreg16(ks, KS_IER, 0x0000);
161 ks_wrreg16(ks, KS_GRR, op);
162 mdelay(10); /* wait a short time to effect reset */
163 ks_wrreg16(ks, KS_GRR, 0);
164 mdelay(1); /* wait for condition to clear */
167 void ks_enable_qmu(struct ks_net *ks)
171 w = ks_rdreg16(ks, KS_TXCR);
173 /* Enables QMU Transmit (TXCR). */
174 ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
176 /* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */
177 w = ks_rdreg16(ks, KS_RXQCR);
178 ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
180 /* Enables QMU Receive (RXCR1). */
181 w = ks_rdreg16(ks, KS_RXCR1);
182 ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
185 static void ks_disable_qmu(struct ks_net *ks)
189 w = ks_rdreg16(ks, KS_TXCR);
191 /* Disables QMU Transmit (TXCR). */
193 ks_wrreg16(ks, KS_TXCR, w);
195 /* Disables QMU Receive (RXCR1). */
196 w = ks_rdreg16(ks, KS_RXCR1);
198 ks_wrreg16(ks, KS_RXCR1, w);
201 static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len)
203 u32 r = ks->extra_byte & 0x1;
204 u32 w = ks->extra_byte - r;
206 /* 1. set sudo DMA mode */
207 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
208 ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
211 * 2. read prepend data
213 * read 4 + extra bytes and discard them.
214 * extra bytes for dummy, 2 for status, 2 for len
220 ks_inblk(ks, buf, w + 2 + 2);
222 /* 3. read pkt data */
223 ks_inblk(ks, buf, ALIGN(len, 4));
225 /* 4. reset sudo DMA Mode */
226 ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
229 static int ks_rcv(struct ks_net *ks, uchar *data)
234 ks->rxfc = ks_rdreg16(ks, KS_RXFCTR) >> 8;
239 /* Checking Received packet status */
240 sts = ks_rdreg16(ks, KS_RXFHSR);
241 /* Get packet len from hardware */
242 len = ks_rdreg16(ks, KS_RXFHBCR);
244 if ((sts & RXFSHR_RXFV) && len && (len < RX_BUF_SIZE)) {
245 /* read data block including CRC 4 bytes */
246 ks_read_qmu(ks, (u16 *)data, len);
251 ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF);
252 printf(DRIVERNAME ": bad packet\n");
257 * ks_read_selftest - read the selftest memory info.
258 * @ks: The device state
260 * Read and check the TX/RX memory selftest information.
262 static int ks_read_selftest(struct ks_net *ks)
264 u16 both_done = MBIR_TXMBF | MBIR_RXMBF;
268 mbir = ks_rdreg16(ks, KS_MBIR);
270 if ((mbir & both_done) != both_done) {
271 printf(DRIVERNAME ": Memory selftest not finished\n");
275 if (mbir & MBIR_TXMBFA) {
276 printf(DRIVERNAME ": TX memory selftest fails\n");
280 if (mbir & MBIR_RXMBFA) {
281 printf(DRIVERNAME ": RX memory selftest fails\n");
285 debug(DRIVERNAME ": the selftest passes\n");
290 static void ks_setup(struct ks_net *ks)
294 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
295 ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
297 /* Setup Receive Frame Data Pointer Auto-Increment */
298 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
300 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
301 ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
303 /* Setup RxQ Command Control (RXQCR) */
304 ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
307 * set the force mode to half duplex, default is full duplex
308 * because if the auto-negotiation fails, most switch uses
311 w = ks_rdreg16(ks, KS_P1MBCR);
312 w &= ~P1MBCR_FORCE_FDX;
313 ks_wrreg16(ks, KS_P1MBCR, w);
315 w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
316 ks_wrreg16(ks, KS_TXCR, w);
318 w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
323 ks_wrreg16(ks, KS_RXCR1, w);
326 static void ks_setup_int(struct ks_net *ks)
328 /* Clear the interrupts status of the hardware. */
329 ks_wrreg16(ks, KS_ISR, 0xffff);
332 static int ks8851_mll_detect_chip(struct ks_net *ks)
338 val = ks_rdreg16(ks, KS_CIDER);
341 /* Special case -- no chip present */
342 printf(DRIVERNAME ": is chip mounted ?\n");
344 } else if ((val & 0xfff0) != CIDER_ID) {
345 printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val);
349 debug("Read back KS8851 id 0x%x\n", val);
351 if ((val & 0xfff0) != CIDER_ID) {
352 printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
359 static void ks8851_mll_reset(struct ks_net *ks)
361 /* wake up powermode to normal mode */
362 ks_set_powermode(ks, PMECR_PM_NORMAL);
363 mdelay(1); /* wait for normal mode to take effect */
365 /* Disable interrupt and reset */
366 ks_soft_reset(ks, GRR_GSR);
368 /* turn off the IRQs and ack any outstanding */
369 ks_wrreg16(ks, KS_IER, 0x0000);
370 ks_wrreg16(ks, KS_ISR, 0xffff);
372 /* shutdown RX/TX QMU */
376 static void ks8851_mll_phy_configure(struct ks_net *ks)
383 /* Probing the phy */
384 data = ks_rdreg16(ks, KS_OBCR);
385 ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA);
387 debug(DRIVERNAME ": phy initialized\n");
390 static void ks8851_mll_enable(struct ks_net *ks)
392 ks_wrreg16(ks, KS_ISR, 0xffff);
397 static int ks8851_mll_init_common(struct ks_net *ks)
399 if (ks_read_selftest(ks)) {
400 printf(DRIVERNAME ": Selftest failed\n");
404 ks8851_mll_reset(ks);
406 /* Configure the PHY, initialize the link state */
407 ks8851_mll_phy_configure(ks);
411 /* Turn on Tx + Rx */
412 ks8851_mll_enable(ks);
417 static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
420 /* start header at txb[0] to align txw entries */
422 txw[1] = cpu_to_le16(len);
424 /* 1. set sudo-DMA mode */
425 ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
426 ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
427 /* 2. write status/length info */
428 ks_outblk(ks, txw, 4);
429 /* 3. write pkt data */
430 ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4));
431 /* 4. reset sudo-DMA mode */
432 ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
433 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
434 ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
435 /* 6. wait until TXQCR_METFE is auto-cleared */
436 do { } while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE);
439 static int ks8851_mll_send_common(struct ks_net *ks, void *packet, int length)
441 u8 *data = (u8 *)packet;
442 u16 tmplen = (u16)length;
446 * Extra space are required:
447 * 4 byte for alignment, 4 for status/length, 4 for CRC
449 retv = ks_rdreg16(ks, KS_TXMIR) & 0x1fff;
450 if (retv >= tmplen + 12) {
451 ks_write_qmu(ks, data, tmplen);
455 printf(DRIVERNAME ": failed to send packet: No buffer\n");
459 static void ks8851_mll_halt_common(struct ks_net *ks)
461 ks8851_mll_reset(ks);
465 * Maximum receive ring size; that is, the number of packets
466 * we can buffer before overflow happens. Basically, this just
467 * needs to be enough to prevent a packet being discarded while
468 * we are processing the previous one.
470 static int ks8851_mll_recv_common(struct ks_net *ks, uchar *data)
475 status = ks_rdreg16(ks, KS_ISR);
477 ks_wrreg16(ks, KS_ISR, status);
479 if (ks->rxfc || (status & IRQ_RXI))
480 ret = ks_rcv(ks, data);
482 if (status & IRQ_LDI) {
483 u16 pmecr = ks_rdreg16(ks, KS_PMECR);
485 pmecr &= ~PMECR_WKEVT_MASK;
486 ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
492 static void ks8851_mll_write_hwaddr_common(struct ks_net *ks, u8 enetaddr[6])
494 u16 addrl, addrm, addrh;
496 addrh = (enetaddr[0] << 8) | enetaddr[1];
497 addrm = (enetaddr[2] << 8) | enetaddr[3];
498 addrl = (enetaddr[4] << 8) | enetaddr[5];
500 ks_wrreg16(ks, KS_MARH, addrh);
501 ks_wrreg16(ks, KS_MARM, addrm);
502 ks_wrreg16(ks, KS_MARL, addrl);
505 static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
507 struct ks_net *ks = container_of(dev, struct ks_net, dev);
509 return ks8851_mll_init_common(ks);
512 static void ks8851_mll_halt(struct eth_device *dev)
514 struct ks_net *ks = container_of(dev, struct ks_net, dev);
516 ks8851_mll_halt_common(ks);
519 static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
521 struct ks_net *ks = container_of(dev, struct ks_net, dev);
523 return ks8851_mll_send_common(ks, packet, length);
526 static int ks8851_mll_recv(struct eth_device *dev)
528 struct ks_net *ks = container_of(dev, struct ks_net, dev);
531 ret = ks8851_mll_recv_common(ks, net_rx_packets[0]);
533 net_process_received_packet(net_rx_packets[0], ret);
538 static int ks8851_mll_write_hwaddr(struct eth_device *dev)
540 struct ks_net *ks = container_of(dev, struct ks_net, dev);
542 ks8851_mll_write_hwaddr_common(ks, ks->dev.enetaddr);
547 int ks8851_mll_initialize(u8 dev_num, int base_addr)
551 ks = calloc(1, sizeof(*ks));
555 ks->iobase = base_addr;
557 /* Try to detect chip. Will fail if not present. */
558 if (ks8851_mll_detect_chip(ks)) {
563 ks->dev.init = ks8851_mll_init;
564 ks->dev.halt = ks8851_mll_halt;
565 ks->dev.send = ks8851_mll_send;
566 ks->dev.recv = ks8851_mll_recv;
567 ks->dev.write_hwaddr = ks8851_mll_write_hwaddr;
568 sprintf(ks->dev.name, "%s-%hu", DRIVERNAME, dev_num);
570 eth_register(&ks->dev);