2 * Ethernet driver for TI K2HK EVM.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/ti-common/keystone_nav.h>
16 #include <asm/ti-common/keystone_net.h>
17 #include <asm/ti-common/keystone_serdes.h>
19 unsigned int emac_open;
20 static unsigned int sys_has_mdio = 1;
22 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
23 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
25 #define emac_gigabit_enable(x) /* no gigabit to enable */
28 #define RX_BUFF_NUMS 24
29 #define RX_BUFF_LEN 1520
30 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
32 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
34 struct rx_buff_desc net_rx_buffs = {
36 .num_buffs = RX_BUFF_NUMS,
37 .buff_len = RX_BUFF_LEN,
41 static void keystone2_net_serdes_setup(void);
43 static int gen_get_link_speed(int phy_addr);
46 static volatile struct mdio_regs *adap_mdio =
47 (struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
49 int keystone2_eth_read_mac_addr(struct eth_device *dev)
51 struct eth_priv_t *eth_priv;
55 eth_priv = (struct eth_priv_t *)dev->priv;
57 /* Read the e-fuse mac address */
58 if (eth_priv->slave_port == 1) {
59 maca = __raw_readl(MAC_ID_BASE_ADDR);
60 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
63 dev->enetaddr[0] = (macb >> 8) & 0xff;
64 dev->enetaddr[1] = (macb >> 0) & 0xff;
65 dev->enetaddr[2] = (maca >> 24) & 0xff;
66 dev->enetaddr[3] = (maca >> 16) & 0xff;
67 dev->enetaddr[4] = (maca >> 8) & 0xff;
68 dev->enetaddr[5] = (maca >> 0) & 0xff;
73 static void keystone2_mdio_reset(void)
77 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
79 writel((clkdiv & 0xffff) |
82 MDIO_CONTROL_FAULT_ENABLE,
85 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
89 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
90 int keystone2_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
94 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
97 writel(MDIO_USERACCESS0_GO |
98 MDIO_USERACCESS0_WRITE_READ |
99 ((reg_num & 0x1f) << 21) |
100 ((phy_addr & 0x1f) << 16),
101 &adap_mdio->useraccess0);
103 /* Wait for command to complete */
104 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
107 if (tmp & MDIO_USERACCESS0_ACK) {
108 *data = tmp & 0xffff;
117 * Write to a PHY register via MDIO inteface.
118 * Blocks until operation is complete.
120 int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
122 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
125 writel(MDIO_USERACCESS0_GO |
126 MDIO_USERACCESS0_WRITE_WRITE |
127 ((reg_num & 0x1f) << 21) |
128 ((phy_addr & 0x1f) << 16) |
130 &adap_mdio->useraccess0);
132 /* Wait for command to complete */
133 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
139 /* PHY functions for a generic PHY */
140 static int gen_get_link_speed(int phy_addr)
144 if ((!keystone2_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp)) &&
152 static void __attribute__((unused))
153 keystone2_eth_gigabit_enable(struct eth_device *dev)
156 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
159 if (keystone2_eth_phy_read(eth_priv->phy_addr, 0, &data) ||
160 !(data & (1 << 6))) /* speed selection MSB */
165 * Check if link detected is giga-bit
166 * If Gigabit mode detected, enable gigbit in MAC
168 writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
170 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
171 DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
174 int keystone_sgmii_link_status(int port)
178 status = __raw_readl(SGMII_STATUS_REG(port));
180 return status & SGMII_REG_STATUS_LINK;
184 int keystone_get_link_status(struct eth_device *dev)
186 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
189 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
192 for (j = 0; (j < CONFIG_GET_LINK_STATUS_ATTEMPTS) && (link_state == 0);
196 keystone_sgmii_link_status(eth_priv->slave_port - 1);
201 if (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY)
202 if (gen_get_link_speed(eth_priv->phy_addr))
205 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
211 int keystone_sgmii_config(int port, int interface)
213 unsigned int i, status, mask;
214 unsigned int mr_adv_ability, control;
217 case SGMII_LINK_MAC_MAC_AUTONEG:
218 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
219 SGMII_REG_MR_ADV_LINK |
220 SGMII_REG_MR_ADV_FULL_DUPLEX |
221 SGMII_REG_MR_ADV_GIG_MODE);
222 control = (SGMII_REG_CONTROL_MASTER |
223 SGMII_REG_CONTROL_AUTONEG);
226 case SGMII_LINK_MAC_PHY:
227 case SGMII_LINK_MAC_PHY_FORCED:
228 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
229 control = SGMII_REG_CONTROL_AUTONEG;
232 case SGMII_LINK_MAC_MAC_FORCED:
233 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
234 SGMII_REG_MR_ADV_LINK |
235 SGMII_REG_MR_ADV_FULL_DUPLEX |
236 SGMII_REG_MR_ADV_GIG_MODE);
237 control = SGMII_REG_CONTROL_MASTER;
240 case SGMII_LINK_MAC_FIBER:
241 mr_adv_ability = 0x20;
242 control = SGMII_REG_CONTROL_AUTONEG;
246 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
247 control = SGMII_REG_CONTROL_AUTONEG;
250 __raw_writel(0, SGMII_CTL_REG(port));
253 * Wait for the SerDes pll to lock,
254 * but don't trap if lock is never read
256 for (i = 0; i < 1000; i++) {
258 status = __raw_readl(SGMII_STATUS_REG(port));
259 if ((status & SGMII_REG_STATUS_LOCK) != 0)
263 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
264 __raw_writel(control, SGMII_CTL_REG(port));
267 mask = SGMII_REG_STATUS_LINK;
269 if (control & SGMII_REG_CONTROL_AUTONEG)
270 mask |= SGMII_REG_STATUS_AUTONEG;
272 for (i = 0; i < 1000; i++) {
273 status = __raw_readl(SGMII_STATUS_REG(port));
274 if ((status & mask) == mask)
281 int mac_sl_reset(u32 port)
285 if (port >= DEVICE_N_GMACSL_PORTS)
286 return GMACSL_RET_INVALID_PORT;
288 /* Set the soft reset bit */
289 writel(CPGMAC_REG_RESET_VAL_RESET,
290 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
292 /* Wait for the bit to clear */
293 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
294 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
295 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
296 CPGMAC_REG_RESET_VAL_RESET)
297 return GMACSL_RET_OK;
300 /* Timeout on the reset */
301 return GMACSL_RET_WARN_RESET_INCOMPLETE;
304 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
307 int ret = GMACSL_RET_OK;
309 if (port >= DEVICE_N_GMACSL_PORTS)
310 return GMACSL_RET_INVALID_PORT;
312 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
313 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
314 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
317 /* Must wait if the device is undergoing reset */
318 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
319 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
320 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
321 CPGMAC_REG_RESET_VAL_RESET)
325 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
326 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
328 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
329 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
334 int ethss_config(u32 ctl, u32 max_pkt_size)
338 /* Max length register */
339 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
341 /* Control register */
342 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
344 /* All statistics enabled by default */
345 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
346 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
348 /* Reset and enable the ALE */
349 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
350 CPSW_REG_VAL_ALE_CTL_BYPASS,
351 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
353 /* All ports put into forward mode */
354 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
355 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
356 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
361 int ethss_start(void)
364 struct mac_sl_cfg cfg;
366 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
367 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
369 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
371 mac_sl_config(i, &cfg);
381 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
387 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
389 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
390 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
392 return ksnav_send(&netcp_pktdma, buffer,
393 num_bytes, (slave_port_num) << 16);
396 /* Eth device open */
397 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
400 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
402 debug("+ emac_open\n");
404 net_rx_buffs.rx_flow = eth_priv->rx_flow;
407 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
409 keystone2_net_serdes_setup();
411 keystone_sgmii_config(eth_priv->slave_port - 1,
412 eth_priv->sgmii_link_type);
416 /* On chip switch configuration */
417 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
419 /* TODO: add error handling code */
421 printf("ERROR: qm_init()\n");
424 if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
426 printf("ERROR: netcp_init()\n");
431 * Streaming switch configuration. If not present this
432 * statement is defined to void in target.h.
433 * If present this is usually defined to a series of register writes
435 hw_config_streaming_switch();
438 keystone2_mdio_reset();
440 link = keystone_get_link_status(dev);
442 ksnav_close(&netcp_pktdma);
448 emac_gigabit_enable(dev);
452 debug("- emac_open\n");
459 /* Eth device close */
460 void keystone2_eth_close(struct eth_device *dev)
462 debug("+ emac_close\n");
469 ksnav_close(&netcp_pktdma);
474 debug("- emac_close\n");
478 * This function sends a single packet on the network and returns
479 * positive number (number of bytes transmitted) or negative for error
481 static int keystone2_eth_send_packet(struct eth_device *dev,
482 void *packet, int length)
485 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
487 if (keystone_get_link_status(dev) == 0)
490 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
497 * This function handles receipt of a packet from the network
499 static int keystone2_eth_rcv_packet(struct eth_device *dev)
505 hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
509 NetReceive((uchar *)pkt, pkt_size);
511 ksnav_release_rxhd(&netcp_pktdma, hd);
517 * This function initializes the EMAC hardware.
519 int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
521 struct eth_device *dev;
523 dev = malloc(sizeof(struct eth_device));
527 memset(dev, 0, sizeof(struct eth_device));
529 strcpy(dev->name, eth_priv->int_name);
530 dev->priv = eth_priv;
532 keystone2_eth_read_mac_addr(dev);
535 dev->init = keystone2_eth_open;
536 dev->halt = keystone2_eth_close;
537 dev->send = keystone2_eth_send_packet;
538 dev->recv = keystone2_eth_rcv_packet;
545 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
546 .clk = SERDES_CLOCK_156P25M,
547 .rate = SERDES_RATE_5G,
548 .rate_mode = SERDES_QUARTER_RATE,
549 .intf = SERDES_PHY_SGMII,
553 static void keystone2_net_serdes_setup(void)
555 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
556 &ks2_serdes_sgmii_156p25mhz,
557 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
559 /* wait till setup */